mirror of
https://github.com/transistorfet/moa.git
synced 2024-12-23 03:29:24 +00:00
Refactored and fixed some warnings
This commit is contained in:
parent
91825e1cb9
commit
e558fc01bf
@ -124,7 +124,7 @@ impl M68k {
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},
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"dis" | "disassemble" => {
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let mut decoder = M68kDecoder::new(self.cputype, 0, 0);
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decoder.dump_disassembly(system, self.state.pc, 0x1000);
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//decoder.dump_disassembly(system, self.state.pc, 0x1000);
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},
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"so" | "stepout" => {
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self.debugger.step_until_return = Some(self.debugger.stack_tracer.calls.len() - 1);
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@ -3,10 +3,10 @@ use std::fmt;
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use crate::error::Error;
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use crate::system::System;
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use crate::memory::Address;
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use crate::memory::{Address, Addressable};
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use crate::devices::AddressableDeviceRefMut;
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use super::state::{M68kType, ERR_ILLEGAL_INSTRUCTION};
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use super::state::{M68kType, Exceptions};
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const OPCG_BIT_OPS: u8 = 0x0;
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@ -19,11 +19,14 @@ const OPCG_BRANCH: u8 = 0x6;
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const OPCG_MOVEQ: u8 = 0x7;
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const OPCG_DIV_OR: u8 = 0x8;
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const OPCG_SUB: u8 = 0x9;
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const OPCG_RESERVED1: u8 = 0xA;
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const OPCG_CMP_EOR: u8 = 0xB;
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const OPCG_MUL_AND: u8 = 0xC;
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const OPCG_ADD: u8 = 0xD;
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const OPCG_SHIFT: u8 = 0xE;
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#[allow(dead_code)]
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const OPCG_RESERVED1: u8 = 0xA;
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#[allow(dead_code)]
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const OPCG_RESERVED2: u8 = 0xF;
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@ -236,7 +239,7 @@ impl M68kDecoder {
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0b0000 => Ok(Instruction::ORtoCCR(data as u8)),
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0b0001 => Ok(Instruction::ANDtoCCR(data as u8)),
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0b1010 => Ok(Instruction::EORtoCCR(data as u8)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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},
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0b01 => {
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@ -245,10 +248,10 @@ impl M68kDecoder {
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0b0000 => Ok(Instruction::ORtoSR(data)),
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0b0010 => Ok(Instruction::ANDtoSR(data)),
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0b1010 => Ok(Instruction::EORtoSR(data)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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} else if (ins & 0x138) == 0x108 {
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let dreg = get_high_reg(ins);
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@ -275,7 +278,7 @@ impl M68kDecoder {
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0b01 => Ok(Instruction::BCHG(bitnum, target, size)),
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0b10 => Ok(Instruction::BCLR(bitnum, target, size)),
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0b11 => Ok(Instruction::BSET(bitnum, target, size)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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} else {
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let size = get_size(ins);
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@ -283,7 +286,7 @@ impl M68kDecoder {
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Some(Size::Byte) => (self.read_instruction_word(system)? as u32 & 0xFF),
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Some(Size::Word) => self.read_instruction_word(system)? as u32,
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Some(Size::Long) => self.read_instruction_long(system)?,
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None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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None => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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};
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let target = self.decode_lower_effective_address(system, ins, size)?;
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@ -294,7 +297,7 @@ impl M68kDecoder {
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0b0110 => Ok(Instruction::ADD(Target::Immediate(data), target, size.unwrap())),
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0b1010 => Ok(Instruction::EOR(Target::Immediate(data), target, size.unwrap())),
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0b1100 => Ok(Instruction::CMP(Target::Immediate(data), target, size.unwrap())),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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}
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},
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@ -330,7 +333,7 @@ impl M68kDecoder {
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let size = match get_size(ins) {
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Some(Size::Word) => Size::Word,
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Some(Size::Long) if self.cputype >= M68kType::MC68020 => Size::Long,
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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};
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let reg = get_high_reg(ins);
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@ -362,7 +365,7 @@ impl M68kDecoder {
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match get_size(ins) {
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Some(size) => Ok(Instruction::CLR(target, size)),
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None if self.cputype >= M68kType::MC68010 => Ok(Instruction::MOVEfromCCR(target)),
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None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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None => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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},
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0b100 => {
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@ -377,7 +380,7 @@ impl M68kDecoder {
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None => Ok(Instruction::MOVEtoSR(target)),
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}
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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} else if ins_0f00 == 0x800 {
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let subselect = (ins & 0x01C0) >> 6;
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@ -402,7 +405,7 @@ impl M68kDecoder {
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let size = if (ins & 0x0040) == 0 { Size::Word } else { Size::Long };
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Ok(Instruction::EXT(get_low_reg(ins), size))
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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} else if ins_0f00 == 0xA00 {
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if (ins & 0x0FF) == 0xFC {
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@ -461,15 +464,15 @@ impl M68kDecoder {
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};
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let creg = match ins2 & 0xFFF {
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0x801 => ControlRegister::VBR,
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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};
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Ok(Instruction::MOVEC(target, creg, dir))
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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}
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} else {
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return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION));
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return Err(Error::processor(Exceptions::IllegalInstruction as u32));
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}
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},
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OPCG_ADDQ_SUBQ => {
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@ -518,7 +521,7 @@ impl M68kDecoder {
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},
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OPCG_MOVEQ => {
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if (ins & 0x0100) != 0 {
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return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION));
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return Err(Error::processor(Exceptions::IllegalInstruction as u32));
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}
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let reg = get_high_reg(ins);
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let data = (ins & 0xFF) as u8;
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@ -596,7 +599,7 @@ impl M68kDecoder {
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let target = self.decode_lower_effective_address(system, ins, Some(size))?;
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Ok(Instruction::CMPA(target, reg, size))
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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},
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OPCG_MUL_AND => {
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@ -617,7 +620,7 @@ impl M68kDecoder {
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0b01000 => Ok(Instruction::EXG(Target::DirectDReg(regx), Target::DirectDReg(regy))),
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0b01001 => Ok(Instruction::EXG(Target::DirectAReg(regx), Target::DirectAReg(regy))),
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0b10001 => Ok(Instruction::EXG(Target::DirectDReg(regx), Target::DirectAReg(regy))),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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} else if size.is_none() {
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let sign = if (ins & 0x0100) == 0 { Sign::Unsigned } else { Sign::Signed };
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@ -675,7 +678,7 @@ impl M68kDecoder {
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0b01 => Ok(Instruction::LSd(count, Target::DirectDReg(reg), size, dir)),
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0b10 => Ok(Instruction::ROXd(count, Target::DirectDReg(reg), size, dir)),
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0b11 => Ok(Instruction::ROd(count, Target::DirectDReg(reg), size, dir)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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},
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None => {
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@ -687,12 +690,12 @@ impl M68kDecoder {
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0b01 => Ok(Instruction::LSd(count, target, Size::Word, dir)),
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0b10 => Ok(Instruction::ROXd(count, target, Size::Word, dir)),
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0b11 => Ok(Instruction::ROd(count, target, Size::Word, dir)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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},
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}
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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}
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@ -742,7 +745,7 @@ impl M68kDecoder {
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panic!("Not Implemented");
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} else {
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Err(Error::processor(ERR_ILLEGAL_INSTRUCTION))
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Err(Error::processor(Exceptions::IllegalInstruction as u32))
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}
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}
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@ -781,18 +784,47 @@ impl M68kDecoder {
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let data = match size {
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Some(Size::Byte) | Some(Size::Word) => self.read_instruction_word(system)? as u32,
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Some(Size::Long) => self.read_instruction_long(system)?,
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None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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None => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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};
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Target::Immediate(data)
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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};
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Ok(value)
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}
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pub fn dump_disassembly(&mut self, system: &System, start: u32, length: u32) {
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let mut next = start;
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while next < (start + length) {
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match self.decode_at(&system, next) {
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Ok(()) => {
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self.dump_decoded(system);
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next = self.end;
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},
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Err(err) => {
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println!("{:?}", err);
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match err {
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Error { native, .. } if native == Exceptions::IllegalInstruction as u32 => {
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println!(" at {:08x}: {:04x}", self.start, system.get_bus().read_beu16(self.start as Address).unwrap());
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},
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_ => { },
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}
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return;
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},
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}
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}
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}
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pub fn dump_decoded(&mut self, system: &System) {
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let ins_data: Result<String, Error> =
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(0..((self.end - self.start) / 2)).map(|offset|
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Ok(format!("{:04x} ", system.get_bus().read_beu16((self.start + (offset * 2)) as Address).unwrap()))
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).collect();
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debug!("{:#010x}: {}\n\t{:?}\n", self.start, ins_data.unwrap(), self.instruction);
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}
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}
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#[inline(always)]
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@ -5,7 +5,6 @@ use crate::memory::{Address, Addressable};
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use crate::devices::{Clock, Steppable, Interruptable};
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use super::decode::{
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M68kDecoder,
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Instruction,
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Target,
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Size,
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@ -18,7 +17,7 @@ use super::decode::{
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sign_extend_to_long
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};
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use super::state::{M68k, Status, Flags, InterruptPriority};
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use super::state::{M68k, Status, Flags, Exceptions, InterruptPriority};
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impl Steppable for M68k {
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fn step(&mut self, system: &System) -> Result<Clock, Error> {
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@ -50,24 +49,15 @@ impl Interruptable for M68k {
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}
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impl M68k {
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#[allow(dead_code)]
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pub fn is_running(&self) -> bool {
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self.state.status != Status::Stopped
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}
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pub fn init(&mut self, system: &System) -> Result<(), Error> {
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println!("Initializing CPU");
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self.state.msp = system.get_bus().read_beu32(0)?;
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self.state.pc = system.get_bus().read_beu32(4)?;
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self.state.status = Status::Running;
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Ok(())
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}
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pub fn step_internal(&mut self, system: &System) -> Result<(), Error> {
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match self.state.status {
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Status::Init => self.init(system),
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Status::Stopped | Status::Halted => Err(Error::new("CPU stopped")),
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Status::Stopped => Err(Error::new("CPU stopped")),
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Status::Running => {
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let timer = self.timer.cycle.start();
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self.decode_next(system)?;
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@ -85,6 +75,13 @@ impl M68k {
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}
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}
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pub fn init(&mut self, system: &System) -> Result<(), Error> {
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self.state.msp = system.get_bus().read_beu32(0)?;
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self.state.pc = system.get_bus().read_beu32(4)?;
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self.state.status = Status::Running;
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Ok(())
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}
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pub fn check_pending_interrupts(&mut self, system: &System) -> Result<(), Error> {
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let current_ipl = self.state.current_ipl as u8;
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let pending_ipl = self.state.pending_ipl as u8;
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@ -126,12 +123,7 @@ impl M68k {
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self.timer.decode.end(timer);
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if self.debugger.use_tracing {
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// Print instruction bytes for debugging
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let ins_data: Result<String, Error> =
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(0..((self.decoder.end - self.decoder.start) / 2)).map(|offset|
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Ok(format!("{:04x} ", system.get_bus().read_beu16((self.decoder.start + (offset * 2)) as Address)?))
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).collect();
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debug!("{:#010x}: {}\n\t{:?}\n", self.decoder.start, ins_data?, self.decoder.instruction);
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self.decoder.dump_decoded(system);
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}
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if self.debugger.use_debugger {
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@ -259,6 +251,11 @@ impl M68k {
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}
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let value = self.get_target_value(system, src, size)?;
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if value == 0 {
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self.exception(system, Exceptions::ZeroDivide as u8)?;
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return Ok(());
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}
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let existing = self.get_target_value(system, dest, Size::Long)?;
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let result = match sign {
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Sign::Signed => {
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@ -537,7 +534,7 @@ impl M68k {
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},
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Instruction::TRAPV => {
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if self.get_flag(Flags::Overflow) {
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self.exception(system, 7)?;
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self.exception(system, Exceptions::TrapvInstruction as u8)?;
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}
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},
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Instruction::UNLK(reg) => {
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@ -9,9 +9,13 @@ use super::debugger::M68kDebugger;
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#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord)]
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pub enum M68kType {
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#[allow(dead_code)]
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MC68000,
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#[allow(dead_code)]
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MC68010,
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#[allow(dead_code)]
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MC68020,
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#[allow(dead_code)]
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MC68030,
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}
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@ -31,9 +35,17 @@ pub enum Flags {
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Tracing = 0x8000,
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}
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pub const ERR_BUS_ERROR: u32 = 2;
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pub const ERR_ADDRESS_ERROR: u32 = 3;
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pub const ERR_ILLEGAL_INSTRUCTION: u32 = 4;
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#[repr(u8)]
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Exceptions {
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BusError = 2,
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AddressError = 3,
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IllegalInstruction = 4,
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ZeroDivide = 5,
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ChkInstruction = 6,
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TrapvInstruction = 7,
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PrivilegeViolation = 8,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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@ -41,7 +53,6 @@ pub enum Status {
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Init,
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Running,
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Stopped,
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Halted,
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}
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#[repr(u8)]
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@ -72,6 +83,7 @@ impl InterruptPriority {
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}
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}
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#[derive(Clone, Debug, PartialEq)]
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pub struct M68kState {
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pub status: Status,
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pub current_ipl: InterruptPriority,
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@ -127,6 +139,7 @@ impl M68k {
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}
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}
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#[allow(dead_code)]
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pub fn reset(&mut self) {
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self.state = M68kState::new();
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self.decoder = M68kDecoder::new(self.cputype, 0, 0);
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@ -7,8 +7,6 @@ use crate::memory::{Address, Addressable};
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use crate::devices::{Clock, Steppable};
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const ATA_REG_DEV_CONTROL: Address = 0x1D;
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const ATA_REG_DEV_ADDRESS: Address = 0x1F;
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const ATA_REG_DATA_WORD: Address = 0x20;
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const ATA_REG_DATA_BYTE: Address = 0x21;
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const ATA_REG_FEATURE: Address = 0x23;
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@ -26,8 +24,11 @@ const ATA_CMD_WRITE_SECTORS: u8 = 0x30;
|
||||
const ATA_CMD_IDENTIFY: u8 = 0xEC;
|
||||
const ATA_CMD_SET_FEATURE: u8 = 0xEF;
|
||||
|
||||
#[allow(dead_code)]
|
||||
const ATA_ST_BUSY: u8 = 0x80;
|
||||
#[allow(dead_code)]
|
||||
const ATA_ST_DATA_READY: u8 = 0x08;
|
||||
#[allow(dead_code)]
|
||||
const ATA_ST_ERROR: u8 = 0x01;
|
||||
|
||||
const ATA_SECTOR_SIZE: u32 = 512;
|
||||
@ -37,6 +38,7 @@ const DEV_NAME: &'static str = "ata";
|
||||
pub struct AtaDevice {
|
||||
pub selected_sector: u32,
|
||||
pub selected_count: u32,
|
||||
pub last_error: u8,
|
||||
pub contents: Vec<u8>,
|
||||
}
|
||||
|
||||
@ -46,6 +48,7 @@ impl AtaDevice {
|
||||
AtaDevice {
|
||||
selected_sector: 0,
|
||||
selected_count: 0,
|
||||
last_error: 0,
|
||||
contents: vec![],
|
||||
}
|
||||
}
|
||||
@ -92,6 +95,9 @@ impl Addressable for AtaDevice {
|
||||
ATA_REG_STATUS => {
|
||||
data[0] = ATA_ST_DATA_READY;
|
||||
},
|
||||
ATA_REG_ERROR => {
|
||||
data[0] = self.last_error;
|
||||
},
|
||||
_ => { println!("{}: reading from {:0x}", DEV_NAME, addr); },
|
||||
}
|
||||
|
||||
|
@ -45,13 +45,21 @@ const REG_IVR_WR: Address = 0x19;
|
||||
|
||||
|
||||
// Status Register Bits (SRA/SRB)
|
||||
#[allow(dead_code)]
|
||||
const SR_RECEIVED_BREAK: u8 = 0x80;
|
||||
#[allow(dead_code)]
|
||||
const SR_FRAMING_ERROR: u8 = 0x40;
|
||||
#[allow(dead_code)]
|
||||
const SR_PARITY_ERROR: u8 = 0x20;
|
||||
#[allow(dead_code)]
|
||||
const SR_OVERRUN_ERROR: u8 = 0x10;
|
||||
#[allow(dead_code)]
|
||||
const SR_TX_EMPTY: u8 = 0x08;
|
||||
#[allow(dead_code)]
|
||||
const SR_TX_READY: u8 = 0x04;
|
||||
#[allow(dead_code)]
|
||||
const SR_RX_FULL: u8 = 0x02;
|
||||
#[allow(dead_code)]
|
||||
const SR_RX_READY: u8 = 0x01;
|
||||
|
||||
|
||||
@ -160,6 +168,11 @@ pub struct MC68681 {
|
||||
pub timer_preload: u16,
|
||||
pub timer_count: u16,
|
||||
pub is_timing: bool,
|
||||
|
||||
pub input_pin_change: u8,
|
||||
pub input_state: u8,
|
||||
pub output_conf: u8,
|
||||
pub output_state: u8,
|
||||
}
|
||||
|
||||
impl MC68681 {
|
||||
@ -176,6 +189,11 @@ impl MC68681 {
|
||||
timer_preload: 0,
|
||||
timer_count: 0,
|
||||
is_timing: true,
|
||||
|
||||
input_pin_change: 0,
|
||||
input_state: 0,
|
||||
output_conf: 0,
|
||||
output_state: 0,
|
||||
}
|
||||
}
|
||||
|
||||
@ -247,6 +265,12 @@ impl Addressable for MC68681 {
|
||||
REG_ISR_RD => {
|
||||
data[0] = self.int_status;
|
||||
},
|
||||
REG_IPCR_RD => {
|
||||
data[0] = self.input_pin_change;
|
||||
},
|
||||
REG_INPUT_RD => {
|
||||
data[0] = self.input_state;
|
||||
},
|
||||
REG_START_RD => {
|
||||
self.timer_count = self.timer_preload;
|
||||
self.is_timing = true;
|
||||
@ -271,9 +295,9 @@ impl Addressable for MC68681 {
|
||||
fn write(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
|
||||
println!("{}: writing {:0x} to {:0x}", DEV_NAME, data[0], addr);
|
||||
match addr {
|
||||
//REG_MR1A_MR2A | REG_ACR_WR => {
|
||||
// // TODO config
|
||||
//},
|
||||
REG_MR1A_MR2A | REG_MR1B_MR2B | REG_CSRA_WR | REG_CSRB_WR => {
|
||||
// NOTE we aren't simulating the serial speeds, so we aren't doing anything with these settings atm
|
||||
},
|
||||
REG_ACR_WR => {
|
||||
self.acr = data[0];
|
||||
}
|
||||
@ -309,6 +333,15 @@ impl Addressable for MC68681 {
|
||||
REG_IVR_WR => {
|
||||
self.int_vector = data[0];
|
||||
},
|
||||
REG_OPCR_WR => {
|
||||
self.output_conf = data[0];
|
||||
},
|
||||
REG_OUT_SET => {
|
||||
self.output_state |= data[0];
|
||||
},
|
||||
REG_OUT_RESET => {
|
||||
self.output_state &= !data[0];
|
||||
},
|
||||
_ => { },
|
||||
}
|
||||
Ok(())
|
||||
|
Loading…
Reference in New Issue
Block a user