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Minor fix to RTE

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transistor 2022-09-15 20:56:52 -07:00
parent 5304df2a9f
commit ef6fde2a4f
2 changed files with 7 additions and 5 deletions
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8
src/cpus/m68k/execute.rs
View File

@ -754,17 +754,19 @@ impl M68k {
Instruction::RTE => {
self.require_supervisor()?;
let sr = self.pop_word()?;
self.set_sr(sr);
let addr = self.pop_long()?;
self.set_pc(addr)?;
if self.cputype >= M68kType::MC68010 {
let _ = self.pop_word()?;
}
self.set_sr(sr);
self.set_pc(addr)?;
},
Instruction::RTR => {
let ccr = self.pop_word()?;
self.set_sr((self.state.sr & 0xFF00) | (ccr & 0x00FF));
let addr = self.pop_long()?;
self.set_sr((self.state.sr & 0xFF00) | (ccr & 0x00FF));
self.set_pc(addr)?;
},
Instruction::RTS => {

4
tests/harte_tests/src/main.rs
View File

@ -231,13 +231,13 @@ fn assert_state(cpu: &M68k, system: &System, expected: &TestState) -> Result<(),
for (i, ins) in expected.prefetch.iter().enumerate() {
let addr = expected.pc + (i as u32 * 2);
let actual = system.get_bus().read_beu16(addr as Address & addr_mask)?;
assert_value(actual, *ins, &format!("prefetch at {}", addr))?;
assert_value(actual, *ins, &format!("prefetch at {:x}", addr))?;
}
// Load data bytes into memory
for (addr, byte) in expected.ram.iter() {
let actual = system.get_bus().read_u8(*addr as Address & addr_mask)?;
assert_value(actual, *byte, &format!("ram at {}", addr))?;
assert_value(actual, *byte, &format!("ram at {:x}", addr))?;
}
Ok(())