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Fixed minor bug

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This commit is contained in:
transistor 2021-12-22 19:27:20 -08:00
parent d0b5d9047e
commit f08c4fc4a9
1 changed files with 2 additions and 2 deletions
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4
src/peripherals/genesis/ym7101.rs
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@ -631,6 +631,7 @@ impl Steppable for Ym7101 {
if (self.state.status & STATUS_IN_HBLANK) == 0 && self.state.h_clock >= 61_160 { if (self.state.status & STATUS_IN_HBLANK) == 0 && self.state.h_clock >= 61_160 {
self.state.status |= STATUS_IN_HBLANK; self.state.status |= STATUS_IN_HBLANK;
self.state.h_scanlines = self.state.h_scanlines.wrapping_sub(1);
if self.state.hsync_int_enabled() && self.state.h_scanlines == 0 { if self.state.hsync_int_enabled() && self.state.h_scanlines == 0 {
self.state.h_scanlines = self.state.h_int_lines; self.state.h_scanlines = self.state.h_int_lines;
system.get_interrupt_controller().set(true, 4, 28)?; system.get_interrupt_controller().set(true, 4, 28)?;
@ -638,7 +639,6 @@ impl Steppable for Ym7101 {
} }
if self.state.h_clock > 63_500 { if self.state.h_clock > 63_500 {
self.state.h_clock -= 63_500; self.state.h_clock -= 63_500;
self.state.h_scanlines = self.state.h_scanlines.wrapping_sub(1);
} }
self.state.v_clock += diff; self.state.v_clock += diff;
@ -776,7 +776,7 @@ impl Addressable for Ym7101 {
if data.len() == 4 { if data.len() == 4 {
let value = read_beu16(&data[2..]); let value = read_beu16(&data[2..]);
if (value & 0xC000) != 0x8000 { if (value & 0xC000) != 0x8000 {
Err(Error:new(&format!("{}: unexpected second byte {:x}", DEV_NAME, value))); return Err(Error::new(&format!("{}: unexpected second byte {:x}", DEV_NAME, value)));
} }
self.state.set_register(value); self.state.set_register(value);
} }