Completed most of the instruction decode
This commit is contained in:
transistor
parent
6a4f53ca2b
commit
f22aa23dfa
587
src/m68k.rs
587
src/m68k.rs
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@ -43,6 +43,22 @@ enum Sign {
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Unsigned,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum Direction {
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FromTarget,
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ToTarget,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum ShiftDirection {
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Right,
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Left,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum ControlRegister {
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VBR,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum Size {
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Byte,
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@ -52,18 +68,22 @@ enum Size {
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum Condition {
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True,
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False,
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High,
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LowOrSame,
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CarryClear,
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CarrySet,
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Equal,
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NotEqual,
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GreaterThanOrEqual,
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GreaterThan,
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LessThanOrEqual,
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LessThan,
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Minus,
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Plus,
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Equal,
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OverflowClear,
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OverflowSet,
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Plus,
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Minus,
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GreaterThanOrEqual,
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LessThan,
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GreaterThan,
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LessThanOrEqual,
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}
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#[derive(Clone, Debug, PartialEq)]
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@ -75,22 +95,28 @@ enum Target {
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IndirectARegInc(u8),
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IndirectARegDec(u8),
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IndirectARegOffset(u8, u16),
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IndirectARegDRegOffset(u8, u8, u16),
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IndirectARegXRegOffset(u8, Box<Target>, u16, Size),
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IndirectMemory(u32),
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IndirectPCOffset(u16),
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IndirectPCRegOffset(u8, u16),
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IndirectPCXRegOffset(Box<Target>, u16, Size),
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}
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#[derive(Clone, Debug, PartialEq)]
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enum Instruction {
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//ABCD
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ADD(Target, Target, Size),
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AND(Target, Target, Size),
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ANDCCR(u8),
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ANDSR(u16),
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ANDtoCCR(u8),
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ANDtoSR(u16),
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ASd(Target, Target, Size, ShiftDirection),
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Bcc(Condition, u16),
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BRA(u16),
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BSR(u16),
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BTST(Target, Target, Size),
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BCHG(Target, Target, Size),
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BCLR(Target, Target, Size),
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BSET(Target, Target, Size),
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CLR(Target, Size),
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CMP(Target, Target, Size),
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@ -98,16 +124,70 @@ enum Instruction {
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DBcc(Condition, u16),
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DIV(Target, Target, Size, Sign),
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LEA(Target, u8),
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JSR(Target),
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EOR(Target, Target, Size),
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EORtoCCR(u8),
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EORtoSR(u16),
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EXG(Target, Target),
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EXT(u8, Size),
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ILLEGAL,
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JMP(Target),
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JSR(Target),
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LEA(Target, u8),
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LINK(u8, u16),
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LSd(Target, Target, Size, ShiftDirection),
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MOVE(Target, Target, Size),
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MOVEfromSR(Target),
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MOVEtoSR(Target),
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MOVEtoCCR(Target),
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MOVEC(Target, ControlRegister, Direction),
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MOVEUSP(Target, Direction),
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MOVEM(Target, Size, Direction, u16),
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MOVEQ(u8, u8),
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MUL(Target, Target, Size, Sign),
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NBCD(Target),
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NEG(Target, Size),
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NEGX(Target, Size),
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NOP,
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NOT(Target, Size),
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OR(Target, Target, Size),
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ORtoCCR(u8),
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ORtoSR(u16),
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PEA(Target),
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RESET,
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ROd(Target, Target, Size, ShiftDirection),
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ROXd(Target, Target, Size, ShiftDirection),
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RTE,
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RTR,
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RTS,
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//SBCD
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//Scc
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STOP(u16),
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SUB(Target, Target, Size),
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SWAP(u8),
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TAS(Target),
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TST(Target, Size),
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TRAP(u8),
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TRAPV,
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UNLK(u8),
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}
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const OPCG_BIT_OPS: u8 = 0x0;
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const OPCG_MOVE_BYTE: u8 = 0x1;
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const OPCG_MOVE_WORD: u8 = 0x2;
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const OPCG_MOVE_LONG: u8 = 0x3;
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const OPCG_MOVE_LONG: u8 = 0x2;
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const OPCG_MOVE_WORD: u8 = 0x3;
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const OPCG_MISC: u8 = 0x04;
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const OPCG_ADDQ_SUBQ: u8 = 0x5;
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const OPCG_BRANCH: u8 = 0x6;
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@ -116,7 +196,7 @@ const OPCG_DIV_OR: u8 = 0x8;
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const OPCG_SUB: u8 = 0x9;
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const OPCG_RESERVED1: u8 = 0xA;
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const OPCG_CMP_EOR: u8 = 0xB;
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const OPCG_MUL_EXCH: u8 = 0xC;
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const OPCG_MUL_AND: u8 = 0xC;
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const OPCG_ADD: u8 = 0xD;
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const OPCG_SHIFT: u8 = 0xE;
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const OPCG_RESERVED2: u8 = 0xF;
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@ -195,14 +275,18 @@ impl MC68010 {
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}
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fn execute_one(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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let addr = self.pc;
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let ins = self.decode_one(space)?;
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println!("{:08x}: {:?}", addr, ins);
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match ins {
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/*
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Instruction::JSR(target) => {
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self.push_long(space, self.pc)?;
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self.pc = self.get_target_value(space, target)?;
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},
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_ => panic!(""),
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*/
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_ => { /* panic!(""); */ },
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}
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Ok(())
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@ -221,105 +305,423 @@ impl MC68010 {
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match ((ins & 0xF000) >> 12) as u8 {
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OPCG_BIT_OPS => {
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panic!("");
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let optype = (ins & 0x0F00) >> 8;
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if (ins & 0x3F) == 0b111100 {
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match (ins & 0x00C0) >> 6 {
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0b00 => {
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let data = self.read_instruction_word(space)?;
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match optype {
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0b0000 => Ok(Instruction::ORtoCCR(data as u8)),
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0b0001 => Ok(Instruction::ANDtoCCR(data as u8)),
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0b1010 => Ok(Instruction::EORtoCCR(data as u8)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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},
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0b01 => {
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let data = self.read_instruction_word(space)?;
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match optype {
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0b0000 => Ok(Instruction::ORtoSR(data)),
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0b0001 => Ok(Instruction::ANDtoSR(data)),
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0b1010 => Ok(Instruction::EORtoSR(data)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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} else if (ins & 0x0100) == 0x0100 || (ins & 0x0F00) == 0x0800 {
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let bitnum = if (ins & 0x0100) == 0x0100 {
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Target::DirectDReg(get_high_reg(ins))
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} else {
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Target::Immediate(self.read_instruction_word(space)? as u32)
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};
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let target = self.decode_lower_effective_address(space, ins, Some(Size::Byte))?;
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let size = match target {
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Target::DirectAReg(_) | Target::DirectDReg(_) => Size::Long,
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_ => Size::Byte,
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};
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match (ins & 0x00C0) >> 6 {
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0b00 => Ok(Instruction::BTST(bitnum, target, size)),
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0b01 => Ok(Instruction::BCHG(bitnum, target, size)),
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0b10 => Ok(Instruction::BCLR(bitnum, target, size)),
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0b11 => Ok(Instruction::BSET(bitnum, target, size)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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} else {
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let size = get_size(ins);
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let target = self.decode_lower_effective_address(space, ins, size)?;
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let data = match size {
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Some(Size::Long) => self.read_instruction_long(space)?,
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Some(size) => self.read_instruction_word(space)? as u32,
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None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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};
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match optype {
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0b0000 => Ok(Instruction::OR(Target::Immediate(data), target, size.unwrap())),
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0b0010 => Ok(Instruction::AND(Target::Immediate(data), target, size.unwrap())),
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0b0100 => Ok(Instruction::SUB(Target::Immediate(data), target, size.unwrap())),
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0b0110 => Ok(Instruction::ADD(Target::Immediate(data), target, size.unwrap())),
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0b1010 => Ok(Instruction::EOR(Target::Immediate(data), target, size.unwrap())),
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0b1100 => Ok(Instruction::CMP(Target::Immediate(data), target, size.unwrap())),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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}
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},
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OPCG_MOVE_BYTE => {
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let data = self.read_instruction_word(space)?;
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panic!("");
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},
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OPCG_MOVE_WORD => {
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let data = self.read_instruction_word(space)?;
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panic!("");
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let src = self.decode_lower_effective_address(space, ins, Some(Size::Byte))?;
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let dest = self.decode_upper_effective_address(space, ins, Some(Size::Byte))?;
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Ok(Instruction::MOVE(src, dest, Size::Byte))
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},
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OPCG_MOVE_LONG => {
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let data = self.read_instruction_long(space)?;
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panic!("");
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let src = self.decode_lower_effective_address(space, ins, Some(Size::Long))?;
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let dest = self.decode_upper_effective_address(space, ins, Some(Size::Long))?;
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Ok(Instruction::MOVE(src, dest, Size::Long))
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},
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OPCG_MOVE_WORD => {
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let src = self.decode_lower_effective_address(space, ins, Some(Size::Word))?;
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let dest = self.decode_upper_effective_address(space, ins, Some(Size::Word))?;
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Ok(Instruction::MOVE(src, dest, Size::Word))
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},
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OPCG_MISC => {
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if (ins & 0b111000000) == 0b111000000 {
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// LEA Instruction
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debug!("LEA");
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let src = self.decode_lower_effective_address(space, ins)?;
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if (ins & 0b000101000000) == 0b000100000000 {
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// CHK Instruction
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panic!("Not Implemented");
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} else if (ins & 0b000111000000) == 0b000111000000 {
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let src = self.decode_lower_effective_address(space, ins, None)?;
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let dest = get_high_reg(ins);
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Ok(Instruction::LEA(src, dest))
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} else if (ins & 0b101000000) == 0b100000000 {
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// CHK Instruction
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panic!("");
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} else if (ins & 0b101110000000) == 0b100010000000 {
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// MOVEM Instruction
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panic!("");
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let target = self.decode_lower_effective_address(space, ins, None)?;
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let data = self.read_instruction_word(space)?;
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let size = if (ins & 0x0040) == 0 { Size::Word } else { Size::Long };
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let dir = if (ins & 0x0200) == 0 { Direction::ToTarget } else { Direction::FromTarget };
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Ok(Instruction::MOVEM(target, size, dir, data))
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} else if (ins & 0b100000000000) == 0 {
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let target = self.decode_lower_effective_address(space, ins, Some(Size::Word))?;
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match (ins & 0x0700) >> 8 {
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0b000 => {
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match get_size(ins) {
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Some(size) => Ok(Instruction::NEGX(target, size)),
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None => Ok(Instruction::MOVEfromSR(target)),
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}
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},
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0b010 => {
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match get_size(ins) {
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Some(size) => Ok(Instruction::CLR(target, size)),
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None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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},
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0b100 => {
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match get_size(ins) {
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Some(size) => Ok(Instruction::NEG(target, size)),
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None => Ok(Instruction::MOVEtoCCR(target)),
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}
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},
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0b110 => {
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match get_size(ins) {
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Some(size) => Ok(Instruction::NOT(target, size)),
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None => Ok(Instruction::MOVEtoSR(target)),
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}
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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} else if (ins & 0b111100000000) == 0b101000000000 {
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let target = self.decode_lower_effective_address(space, ins, Some(Size::Word))?;
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match get_size(ins) {
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Some(size) => Ok(Instruction::TST(target, size)),
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None => Ok(Instruction::TAS(target)),
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}
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} else if (ins & 0b111100000000) == 0b100000000000 {
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let subselect = (ins & 0x01C0) >> 6;
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let mode = get_low_mode(ins);
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match (subselect, mode) {
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(0b010, 0b000) => {
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Ok(Instruction::EXT(get_low_reg(ins), Size::Word))
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},
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(0b011, 0b000) => {
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Ok(Instruction::EXT(get_low_reg(ins), Size::Long))
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},
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(0b000, mode) => {
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let target = self.decode_lower_effective_address(space, ins, Some(Size::Byte))?;
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Ok(Instruction::NBCD(target))
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},
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(0b001, 0b000) => {
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Ok(Instruction::SWAP(get_low_reg(ins)))
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},
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(0b001, mode) => {
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let target = self.decode_lower_effective_address(space, ins, None)?;
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Ok(Instruction::PEA(target))
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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} else if (ins & 0b111110000000) == 0b111010000000 {
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// JMP/JSR Instruction
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let target = self.decode_lower_effective_address(space, ins)?;
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let target = self.decode_lower_effective_address(space, ins, None)?;
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if (ins & 0b01000000) == 0 {
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Ok(Instruction::JSR(target))
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} else {
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Ok(Instruction::JMP(target))
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}
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} else if (ins & 0b111111110000) == 0b111001010000 {
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let reg = get_low_reg(ins);
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if (ins & 0b1000) == 0 {
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let data = self.read_instruction_word(space)?;
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Ok(Instruction::LINK(reg, data))
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} else {
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Ok(Instruction::UNLK(reg))
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}
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} else if (ins & 0b111111110000) == 0b111001100000 {
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let reg = get_low_reg(ins);
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let dir = if (ins & 0b1000) == 0 { Direction::FromTarget } else { Direction::ToTarget };
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Ok(Instruction::MOVEUSP(Target::DirectAReg(reg), dir))
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} else {
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panic!("");
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match ins & 0x0FFF {
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0xAFC => Ok(Instruction::ILLEGAL),
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0xE70 => Ok(Instruction::RESET),
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0xE71 => Ok(Instruction::NOP),
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0xE72 => {
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let data = self.read_instruction_word(space)?;
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Ok(Instruction::STOP(data))
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},
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0xE73 => Ok(Instruction::RTE),
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0xE75 => Ok(Instruction::RTS),
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0xE76 => Ok(Instruction::TRAPV),
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0xE77 => Ok(Instruction::RTR),
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0xE7A | 0xE7B => {
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let dir = if ins & 0x01 == 0 { Direction::ToTarget } else { Direction::FromTarget };
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let ins2 = self.read_instruction_word(space)?;
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let target = match ins2 & 0x8000 {
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0 => Target::DirectDReg(((ins2 & 0x7000) >> 12) as u8),
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_ => Target::DirectAReg(((ins2 & 0x7000) >> 12) as u8),
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};
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let creg = match ins2 & 0xFFF {
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0x801 => ControlRegister::VBR,
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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};
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Ok(Instruction::MOVEC(target, creg, dir))
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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}
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},
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OPCG_ADDQ_SUBQ => {
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let size = match get_size(ins) {
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Some(size) => size,
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None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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};
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panic!("");
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let target = self.decode_lower_effective_address(space, ins, Some(size))?;
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let mut data = ((ins & 0x0E00) >> 9) as u32;
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if data == 0 {
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data = 8;
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}
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if (ins & 0x0100) == 0 {
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Ok(Instruction::ADD(Target::Immediate(data), target, size))
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} else {
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Ok(Instruction::SUB(Target::Immediate(data), target, size))
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}
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},
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OPCG_BRANCH => {
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panic!("");
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let mut disp = (ins & 0xFF);
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if disp == 0 {
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disp = self.read_instruction_word(space)?;
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}
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let condition = get_condition(ins);
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match condition {
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Condition::True => Ok(Instruction::BRA(disp)),
|
||||
Condition::False => Ok(Instruction::BSR(disp)),
|
||||
_ => Ok(Instruction::Bcc(condition, disp)),
|
||||
}
|
||||
},
|
||||
OPCG_MOVEQ => {
|
||||
|
||||
panic!("");
|
||||
// TODO make sure the 9th bit is 0
|
||||
let reg = get_high_reg(ins);
|
||||
let data = (ins & 0xFF) as u8;
|
||||
Ok(Instruction::MOVEQ(data, reg))
|
||||
},
|
||||
OPCG_DIV_OR => {
|
||||
let size = get_size(ins);
|
||||
|
||||
panic!("");
|
||||
if size.is_none() {
|
||||
let sign = if (ins & 0x0100) == 0 { Sign::Unsigned } else { Sign::Signed };
|
||||
let data_reg = Target::DirectDReg(get_high_reg(ins));
|
||||
let effective_addr = self.decode_lower_effective_address(space, ins, size)?;
|
||||
Ok(Instruction::DIV(effective_addr, data_reg, Size::Word, sign))
|
||||
} else if (ins & 0b000111110000) == 0b000100000000 {
|
||||
// TODO SBCD
|
||||
panic!("Not Implemented");
|
||||
} else {
|
||||
let data_reg = Target::DirectDReg(get_high_reg(ins));
|
||||
let effective_addr = self.decode_lower_effective_address(space, ins, size)?;
|
||||
let (from, to) = if (ins & 0x0100) == 0 { (effective_addr, data_reg) } else { (data_reg, effective_addr) };
|
||||
Ok(Instruction::OR(from, to, size.unwrap()))
|
||||
}
|
||||
},
|
||||
OPCG_SUB => {
|
||||
|
||||
panic!("");
|
||||
// TODO need to decode the SUBX instruction (would likely be erroneously decoded atm)
|
||||
let reg = get_high_reg(ins);
|
||||
let dir = (ins & 0x0100) >> 8;
|
||||
let size = get_size(ins);
|
||||
match size {
|
||||
Some(size) => {
|
||||
let target = self.decode_lower_effective_address(space, ins, Some(size))?;
|
||||
if dir == 0 {
|
||||
Ok(Instruction::SUB(target, Target::DirectDReg(reg), size))
|
||||
} else {
|
||||
Ok(Instruction::SUB(Target::DirectDReg(reg), target, size))
|
||||
}
|
||||
},
|
||||
None => {
|
||||
let size = if dir == 0 { Size::Word } else { Size::Long };
|
||||
let target = self.decode_lower_effective_address(space, ins, Some(size))?;
|
||||
Ok(Instruction::SUB(target, Target::DirectAReg(reg), size))
|
||||
},
|
||||
}
|
||||
},
|
||||
OPCG_CMP_EOR => {
|
||||
|
||||
panic!("");
|
||||
let reg = get_high_reg(ins);
|
||||
let optype = (ins & 0x0100) >> 8;
|
||||
let size = get_size(ins);
|
||||
match (optype, size) {
|
||||
(0b1, Some(size)) => {
|
||||
// TODO need to decode the CMPM instruction (mode == 0b001) (would likely be erroneously decoded atm)
|
||||
let target = self.decode_lower_effective_address(space, ins, Some(size))?;
|
||||
Ok(Instruction::EOR(Target::DirectDReg(reg), target, size))
|
||||
},
|
||||
(0b0, Some(size)) => {
|
||||
let target = self.decode_lower_effective_address(space, ins, Some(size))?;
|
||||
Ok(Instruction::CMP(Target::DirectDReg(reg), target, size))
|
||||
},
|
||||
(size, None) => {
|
||||
let size = if optype == 0 { Size::Word } else { Size::Long };
|
||||
let target = self.decode_lower_effective_address(space, ins, Some(size))?;
|
||||
Ok(Instruction::CMP(target, Target::DirectAReg(reg), size))
|
||||
},
|
||||
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
||||
}
|
||||
},
|
||||
OPCG_MUL_EXCH => {
|
||||
OPCG_MUL_AND => {
|
||||
let size = get_size(ins);
|
||||
|
||||
panic!("");
|
||||
if size.is_none() {
|
||||
let sign = if (ins & 0x0100) == 0 { Sign::Unsigned } else { Sign::Signed };
|
||||
let data_reg = Target::DirectDReg(get_high_reg(ins));
|
||||
let effective_addr = self.decode_lower_effective_address(space, ins, size)?;
|
||||
Ok(Instruction::MUL(effective_addr, data_reg, Size::Word, sign))
|
||||
} else if (ins & 0b000111110000) == 0b000100000000 {
|
||||
// TODO ABCD or EXG
|
||||
panic!("Not Implemented");
|
||||
} else {
|
||||
let data_reg = Target::DirectDReg(get_high_reg(ins));
|
||||
let effective_addr = self.decode_lower_effective_address(space, ins, size)?;
|
||||
let (from, to) = if (ins & 0x0100) == 0 { (effective_addr, data_reg) } else { (data_reg, effective_addr) };
|
||||
Ok(Instruction::AND(from, to, size.unwrap()))
|
||||
}
|
||||
},
|
||||
OPCG_ADD => {
|
||||
|
||||
panic!("");
|
||||
// TODO need to decode the ADDX instruction (would likely be erroneously decoded atm)
|
||||
let reg = get_high_reg(ins);
|
||||
let dir = (ins & 0x0100) >> 8;
|
||||
let size = get_size(ins);
|
||||
match size {
|
||||
Some(size) => {
|
||||
let target = self.decode_lower_effective_address(space, ins, Some(size))?;
|
||||
if dir == 0 {
|
||||
Ok(Instruction::ADD(target, Target::DirectDReg(reg), size))
|
||||
} else {
|
||||
Ok(Instruction::ADD(Target::DirectDReg(reg), target, size))
|
||||
}
|
||||
},
|
||||
None => {
|
||||
let size = if dir == 0 { Size::Word } else { Size::Long };
|
||||
let target = self.decode_lower_effective_address(space, ins, Some(size))?;
|
||||
Ok(Instruction::ADD(target, Target::DirectAReg(reg), size))
|
||||
},
|
||||
}
|
||||
},
|
||||
OPCG_SHIFT => {
|
||||
let dir = if (ins & 0x0100) == 0 { ShiftDirection::Right } else { ShiftDirection::Left };
|
||||
match get_size(ins) {
|
||||
Some(size) => {
|
||||
let reg = get_low_reg(ins);
|
||||
let rotation = get_high_reg(ins);
|
||||
let count = if (ins & 0x0020) == 0 {
|
||||
Target::Immediate(rotation as u32)
|
||||
} else {
|
||||
Target::DirectDReg(rotation)
|
||||
};
|
||||
|
||||
panic!("");
|
||||
match (ins & 0x0018) >> 3 {
|
||||
0b00 => Ok(Instruction::ASd(count, Target::DirectDReg(reg), size, dir)),
|
||||
0b01 => Ok(Instruction::LSd(count, Target::DirectDReg(reg), size, dir)),
|
||||
0b10 => Ok(Instruction::ROXd(count, Target::DirectDReg(reg), size, dir)),
|
||||
0b11 => Ok(Instruction::ROd(count, Target::DirectDReg(reg), size, dir)),
|
||||
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
||||
}
|
||||
},
|
||||
None => {
|
||||
let target = self.decode_lower_effective_address(space, ins, Some(Size::Word))?;
|
||||
let count = Target::Immediate(1);
|
||||
|
||||
match (ins & 0x0600) >> 9 {
|
||||
0b00 => Ok(Instruction::ASd(count, target, Size::Word, dir)),
|
||||
0b01 => Ok(Instruction::LSd(count, target, Size::Word, dir)),
|
||||
0b10 => Ok(Instruction::ROXd(count, target, Size::Word, dir)),
|
||||
0b11 => Ok(Instruction::ROd(count, target, Size::Word, dir)),
|
||||
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
||||
}
|
||||
},
|
||||
}
|
||||
},
|
||||
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
||||
}
|
||||
}
|
||||
|
||||
fn decode_lower_effective_address(&mut self, space: &mut AddressSpace, ins: u16) -> Result<Target, Error> {
|
||||
fn decode_lower_effective_address(&mut self, space: &mut AddressSpace, ins: u16, size: Option<Size>) -> Result<Target, Error> {
|
||||
let reg = get_low_reg(ins);
|
||||
let mode = get_mode(ins);
|
||||
self.get_mode_as_target(space, mode, reg)
|
||||
let mode = get_low_mode(ins);
|
||||
self.get_mode_as_target(space, mode, reg, size)
|
||||
}
|
||||
|
||||
fn get_mode_as_target(&mut self, space: &mut AddressSpace, mode: u8, reg: u8) -> Result<Target, Error> {
|
||||
fn decode_upper_effective_address(&mut self, space: &mut AddressSpace, ins: u16, size: Option<Size>) -> Result<Target, Error> {
|
||||
let reg = get_high_reg(ins);
|
||||
let mode = get_high_mode(ins);
|
||||
self.get_mode_as_target(space, mode, reg, size)
|
||||
}
|
||||
|
||||
fn decode_brief_extension_word(&self, brief_extension: u16) -> (Target, u16, Size) {
|
||||
let data = brief_extension & 0x00FF;
|
||||
let reg = ((brief_extension & 0x7000) >> 12) as u8;
|
||||
let size = if (brief_extension & 0x0800) == 0 { Size::Word } else { Size::Long };
|
||||
|
||||
let target = if (brief_extension & 0x8000) == 0 {
|
||||
Target::DirectDReg(reg)
|
||||
} else {
|
||||
Target::DirectAReg(reg)
|
||||
};
|
||||
|
||||
(target, data, size)
|
||||
}
|
||||
|
||||
fn get_mode_as_target(&mut self, space: &mut AddressSpace, mode: u8, reg: u8, size: Option<Size>) -> Result<Target, Error> {
|
||||
let value = match mode {
|
||||
0b000 => Target::DirectDReg(reg),
|
||||
0b001 => Target::DirectAReg(reg),
|
||||
0b010 => Target::IndirectAReg(reg),
|
||||
0b011 => Target::IndirectARegInc(reg),
|
||||
0b100 => Target::IndirectARegDec(reg),
|
||||
0b101 => {
|
||||
let d16 = self.read_instruction_word(space)?;
|
||||
Target::IndirectARegOffset(reg, d16)
|
||||
},
|
||||
0b110 => {
|
||||
let brief_extension = self.read_instruction_word(space)?;
|
||||
let (target, data, size) = self.decode_brief_extension_word(brief_extension);
|
||||
Target::IndirectARegXRegOffset(reg, Box::new(target), data, size)
|
||||
},
|
||||
0b111 => {
|
||||
match reg {
|
||||
0b000 => {
|
||||
|
|
@ -334,6 +736,19 @@ panic!("");
|
|||
let d16 = self.read_instruction_word(space)?;
|
||||
Target::IndirectPCOffset(d16)
|
||||
},
|
||||
0b011 => {
|
||||
let brief_extension = self.read_instruction_word(space)?;
|
||||
let (target, data, size) = self.decode_brief_extension_word(brief_extension);
|
||||
Target::IndirectPCXRegOffset(Box::new(target), data, size)
|
||||
},
|
||||
0b100 => {
|
||||
let data = match size {
|
||||
Some(Size::Byte) | Some(Size::Word) => self.read_instruction_word(space)? as u32,
|
||||
Some(Size::Long) => self.read_instruction_long(space)?,
|
||||
None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
||||
};
|
||||
Target::Immediate(data)
|
||||
},
|
||||
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
||||
}
|
||||
},
|
||||
|
|
@ -341,11 +756,12 @@ panic!("");
|
|||
};
|
||||
Ok(value)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn get_high_reg(ins: u16) -> u8 {
|
||||
((ins & 0x0D00) >> 9) as u8
|
||||
((ins & 0x0E00) >> 9) as u8
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
|
|
@ -354,10 +770,49 @@ fn get_low_reg(ins: u16) -> u8 {
|
|||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn get_mode(ins: u16) -> u8 {
|
||||
fn get_high_mode(ins: u16) -> u8 {
|
||||
((ins & 0x01C0) >> 6) as u8
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn get_low_mode(ins: u16) -> u8 {
|
||||
((ins & 0x0038) >> 3) as u8
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn get_size(ins: u16) -> Option<Size> {
|
||||
match (ins & 0x00C0) >> 6 {
|
||||
0b00 => Some(Size::Byte),
|
||||
0b01 => Some(Size::Word),
|
||||
0b10 => Some(Size::Long),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn get_condition(ins: u16) -> Condition {
|
||||
match (ins & 0x0F00) >> 8 {
|
||||
0b0000 => Condition::True,
|
||||
0b0001 => Condition::False,
|
||||
0b0010 => Condition::High,
|
||||
0b0011 => Condition::LowOrSame,
|
||||
0b0100 => Condition::CarryClear,
|
||||
0b0101 => Condition::CarrySet,
|
||||
0b0110 => Condition::NotEqual,
|
||||
0b0111 => Condition::Equal,
|
||||
0b1000 => Condition::OverflowClear,
|
||||
0b1001 => Condition::OverflowSet,
|
||||
0b1010 => Condition::Plus,
|
||||
0b1011 => Condition::Minus,
|
||||
0b1100 => Condition::GreaterThanOrEqual,
|
||||
0b1101 => Condition::LessThan,
|
||||
0b1110 => Condition::GreaterThan,
|
||||
0b1111 => Condition::LessThanOrEqual,
|
||||
|
||||
_ => Condition::True,
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
impl Processor for MC68010 {
|
||||
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ impl AddressSpace {
|
|||
return Ok(&self.segments[i]);
|
||||
}
|
||||
}
|
||||
return Err(Error::new("No segment found"));
|
||||
return Err(Error::new(&format!("No segment found at {:08x}", addr)));
|
||||
}
|
||||
|
||||
pub fn get_segment_mut(&mut self, addr: Address) -> Result<&mut Segment, Error> {
|
||||
|
|
@ -84,7 +84,7 @@ impl AddressSpace {
|
|||
return Ok(&mut self.segments[i]);
|
||||
}
|
||||
}
|
||||
return Err(Error::new("No segment found"));
|
||||
return Err(Error::new(&format!("No segment found at {:08x}", addr)));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue