8 Commits

Author	SHA1	Message	Date
transistor	c4a99245e3	Added option to exclude or only run tests that involve an exception	2022-09-11 18:52:19 -07:00
transistor	03f4e11e3b	Added proper AddressError handling to m68k ... Also a few fixes, such as correcting a decode error in ADDX	2022-09-11 17:42:54 -07:00
transistor	34bdd86772	Added address mask to memory accesses from the tests	2022-09-11 14:51:58 -07:00
transistor	0582625b5e	Fixed some issue with m68k ... Some debug code was enabled that prevented illegal instructions from being handled normally with a processor exception The brief instruction word decoding could cause an illegal instruction if it didn't match the docs, but the actual implementation would not complain in those cases, so I modified it to not perform validation for <=MC68010 Increment and Decrement addressing modes, when using the stack pointer, will always inc/dec by at least 2 bytes, even if it's a byte operation, to keep the stack aligned to the nearest word boundary	2022-09-10 21:09:35 -07:00
transistor	27f71b0f33	Added test results	2022-09-10 20:49:26 -07:00
transistor	c53253c050	Added more options to run select tests to harte test runner	2022-09-10 14:08:01 -07:00
transistor	f3a177489e	Fixed the percentage summary for the harte tests	2022-09-09 23:43:06 -07:00
transistor	c57c8f87b4	Added test running for Tom Harte's ProcessorTests test suite	2022-09-09 23:17:33 -07:00