8 Commits

Author	SHA1	Message	Date
transistor	84d2b5e15b	Added test results	2022-09-14 22:51:48 -07:00
transistor	d074b7fc5e	Test after fixing MULS	2022-09-13 22:18:22 -07:00
transistor	873741846c	Implemented the CHK and NEGX instructions	2022-09-12 22:19:01 -07:00
transistor	9ff528c463	Fixed some AddressError tests ... Adjusted the PC value stored when an Address Error fault occurs to use the size of the access operation. I also flipped the IN bit in the word that's written to the top of the stack on an AddressError, even though that's opposite of what the docs say. It seems to pass the tests. I probably have something else going wrong, but it shouldn't be an important bit either way.	2022-09-12 21:47:36 -07:00
transistor	42bfabb743	Added test results	2022-09-11 21:52:29 -07:00
transistor	03f4e11e3b	Added proper AddressError handling to m68k ... Also a few fixes, such as correcting a decode error in ADDX	2022-09-11 17:42:54 -07:00
transistor	0582625b5e	Fixed some issue with m68k ... Some debug code was enabled that prevented illegal instructions from being handled normally with a processor exception The brief instruction word decoding could cause an illegal instruction if it didn't match the docs, but the actual implementation would not complain in those cases, so I modified it to not perform validation for <=MC68010 Increment and Decrement addressing modes, when using the stack pointer, will always inc/dec by at least 2 bytes, even if it's a byte operation, to keep the stack aligned to the nearest word boundary	2022-09-10 21:09:35 -07:00
transistor	27f71b0f33	Added test results	2022-09-10 20:49:26 -07:00