Commit Graph

11 Commits

Author SHA1 Message Date
transistor
d0037c8125 Fixed tests and clippy warnings 2024-03-16 13:15:34 -07:00
transistor
c20d7afe6e Fixed some tests 2024-03-15 23:01:41 -07:00
transistor
545f339fe2 Separated moa-core dependency into an optional feature flag 2024-03-13 21:49:04 -07:00
transistor
b4a35641e4 Refactored to separate out the BusPort, to eventually replace it 2024-03-03 22:57:27 -08:00
transistor
54ebcce94c Fixed m68k tests after refactor 2024-03-03 13:26:15 -08:00
transistor
cff6a48cc7 Refactoring m68k to use a temporary cycle struct
I'm trying to extract the memory/bus interface, and pass it in at
the start of each cycle instead of having the BusPort permanently
embedded, which will allow migrating to emulator-hal.

The functional way would be argument drilling; passing an extra argument
to each function in the entire execution core.  The problem is that it's
messy, so a solution that is still functional is to implement all of the
execution logic on a newtype that contains a reference to the mutable
state and the owned cycle data, and at the end of the cycle, decompose
the M68kCycleGuard that holds the reference, and keep the cycle data for
debugging purposes.
2024-03-02 23:48:19 -08:00
transistor
9ff431ebc6 Split clocks into femtos crate 2024-02-24 13:02:09 -08:00
transistor
be91118bac Added function to create the CPU BusPorts based on the CPU type 2023-06-10 20:28:40 -07:00
transistor
e3861f33b5 Fixed tests and clippy warnings 2023-06-10 17:39:20 -07:00
transistor
5e228c377e Fixed tests after ClockTime and Frequency changes
And also removed HostData
2023-05-07 20:42:55 -07:00
transistor
099d557a3f Reorganized m68k tests 2023-03-25 21:27:02 -07:00