mirror of
https://github.com/transistorfet/moa.git
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67 lines
1.5 KiB
Rust
67 lines
1.5 KiB
Rust
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use std::slice::Iter;
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use crate::memory::{Address, Addressable};
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const REG_MR1A_MR2A: Address = 0x01;
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const REG_SRA_RD: Address = 0x03;
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const REG_CSRA_WR: Address = 0x03;
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const REG_CRA_WR: Address = 0x05;
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const REG_TBA_WR: Address = 0x07;
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const REG_RBA_RD: Address = 0x07;
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const REG_ACR_WR: Address = 0x09;
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const REG_CTUR_WR: Address = 0x0D;
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const REG_CTLR_WR: Address = 0x0F;
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const REG_START_RD: Address = 0x1D;
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const REG_STOP_RD: Address = 0x1F;
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const REG_IPCR_RD: Address = 0x09;
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const REG_OPCR_WR: Address = 0x1B;
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const REG_INPUT_RD: Address = 0x1B;
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const REG_OUT_SET: Address = 0x1D;
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const REG_OUT_RESET: Address = 0x1F;
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const REG_ISR_RD: Address = 0x0B;
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const REG_IMR_WR: Address = 0x0B;
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const REG_IVR_WR: Address = 0x19;
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const DEV_NAME: &'static str = "mc68681";
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pub struct MC68681 {
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pub status: [u8; 1],
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pub input: [u8; 1],
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}
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impl MC68681 {
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pub fn new() -> Self {
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MC68681 {
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status: [0x0C],
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input: [0],
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}
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}
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}
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impl Addressable for MC68681 {
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fn len(&self) -> usize {
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0x30
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}
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fn read(&self, addr: Address) -> &[u8] {
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match addr {
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REG_SRA_RD => &self.status,
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REG_TBA_RD => &self.input,
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_ => { println!("{}: reading from {:0x}", DEV_NAME, addr); &self.input },
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}
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}
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fn write(&mut self, mut addr: Address, data: &[u8]) {
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match addr {
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REG_TBA_WR => { println!(">>> {}", data[0] as char); },
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_ => { println!("{}: writing {:0x} to {:0x}", DEV_NAME, data[0], addr); },
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}
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}
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}
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