transistor 10e905674b Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags ...

With ADDA, SUBA, and ADDQ/SUBQ when the target is an address register, the condition
flags should not be changed, but the code was changing them, which caused problems.
I've fixed it by making the ADD/SUB executions check for an address target and
will not update flags in that case.  This should only occur when the actual instruction
was an ADDA or ADDQ with an address register target

2021-10-02 21:59:28 -07:00

..

cpus

Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags

2021-10-02 21:59:28 -07:00

devices

Fixed pty code to actually read input

2021-10-01 17:53:55 -07:00

error.rs

Initial start with some structure for instruction decoding

2021-09-28 16:09:38 -07:00

main.rs

Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags

2021-10-02 21:59:28 -07:00

memory.rs

Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags

2021-10-02 21:59:28 -07:00