mirror of
https://github.com/transistorfet/moa.git
synced 2025-08-07 20:25:11 +00:00
342bb8aa3d
* Converted Z80 to use emulator-hal traits * Updated emulator-hal * Added a hacky Signalable trait to replace the Z80 signals * Minor fixes * Fixed timing tests and added no io tests option * Fixed genesis Z80 bus issue * Fixed addressing for BusAccess impl of Z80 * Fixed tests and clippy lints
79 lines
3.2 KiB
Rust
79 lines
3.2 KiB
Rust
use femtos::{Instant, Frequency};
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use emulator_hal::{BusAccess, Step, NoBus};
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use emulator_hal_memory::MemoryBlock;
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use moa_z80::{Z80, Z80Type, Z80Port, Instruction, LoadTarget, Target, Register, RegisterPair, IndexRegister, IndexRegisterHalf};
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fn init_decode_test() -> (Z80<Instant>, MemoryBlock<Instant>) {
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// Insert basic initialization
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let len = 0x10_0000;
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let mut data = Vec::with_capacity(len);
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unsafe {
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data.set_len(len);
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}
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let mut memory = MemoryBlock::from(data);
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let mut io = NoBus::new();
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// Initialize the CPU and make sure it's in the expected state
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let mut cpu = Z80::new(Z80Type::Z80, Frequency::from_mhz(4));
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let mut bus = Z80Port::new(&mut memory, &mut io);
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cpu.reset(Instant::START, &mut bus).unwrap();
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cpu.step(Instant::START, &mut bus).unwrap();
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(cpu, memory)
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}
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fn load_memory(memory: &mut MemoryBlock<Instant>, data: &[u8]) {
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for i in 0..data.len() {
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memory.write_u8(Instant::START, i, data[i]).unwrap();
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}
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}
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fn run_decode_test(data: &[u8]) -> Instruction {
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let (mut cpu, mut memory) = init_decode_test();
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load_memory(&mut memory, data);
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let mut io = NoBus::new();
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let mut bus = Z80Port::new(&mut memory, &mut io);
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cpu.step(Instant::START, &mut bus).unwrap();
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cpu.previous_cycle.decoder.instruction
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}
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#[test]
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fn run_all_decode_tests() {
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let mut failures = vec![];
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for (data, expected_instruction) in DECODE_TESTS {
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let instruction = run_decode_test(data);
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if instruction != *expected_instruction {
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failures.push((data, instruction, expected_instruction));
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}
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}
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let fails = failures.len();
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for (data, instruction, expected_instruction) in failures {
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println!("for {:?}\nexpected:\t{:?}\nreceived:\t{:?}\n", data, instruction, expected_instruction);
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}
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if fails > 0 {
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panic!("{} decode tests failed", fails);
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}
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}
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#[rustfmt::skip]
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const DECODE_TESTS: &'static [(&[u8], Instruction)] = &[
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(&[0x00], Instruction::NOP),
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(&[0x01, 0x01, 0x02], Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::BC), LoadTarget::ImmediateWord(0x0201))),
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(&[0x02], Instruction::LD(LoadTarget::IndirectRegByte(RegisterPair::BC), LoadTarget::DirectRegByte(Register::A))),
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(&[0x03], Instruction::INC16(RegisterPair::BC)),
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(&[0x04], Instruction::INC8(Target::DirectReg(Register::B))),
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(&[0x05], Instruction::DEC8(Target::DirectReg(Register::B))),
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(&[0xDD, 0x09], Instruction::ADD16(RegisterPair::IX, RegisterPair::BC)),
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(&[0xDD, 0x44], Instruction::LD(LoadTarget::DirectRegByte(Register::B), LoadTarget::DirectRegHalfByte(IndexRegisterHalf::IXH))),
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(&[0xDD, 0x66, 0x12], Instruction::LD(LoadTarget::DirectRegByte(Register::H), LoadTarget::IndirectOffsetByte(IndexRegister::IX, 0x12))),
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(&[0xDD, 0x6E, 0x12], Instruction::LD(LoadTarget::DirectRegByte(Register::L), LoadTarget::IndirectOffsetByte(IndexRegister::IX, 0x12))),
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(&[0xDD, 0x84], Instruction::ADDa(Target::DirectRegHalf(IndexRegisterHalf::IXH))),
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(&[0xDD, 0x85], Instruction::ADDa(Target::DirectRegHalf(IndexRegisterHalf::IXL))),
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];
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