mirror of
https://github.com/transistorfet/moa.git
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59 lines
3.0 KiB
Plaintext
59 lines
3.0 KiB
Plaintext
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* currently you need to implement the 1.5ms reset in the genesis controllers
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* should SharedData be HostData, or something else? I don't think the name is very informative
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* can you make the connections between things (like memory adapters), be expressed in a way that's more similar to the electrical design?
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like specifying that address pins 10-7 should be ignored/unconnected, pin 11 will connect to "chip select", etc
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* movem still isn't working (for genesis)
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* fix movem tests
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* modify the frame swapper and frontend to avoid the extra buffer copy
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* I had to remove the mask colour from blit because it doesn't work with the mac... need a new solution
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* add more m68k tests and try to test against a working impl
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* maybe see about a Mac 128k or something
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* should you rename devices.rs traits.rs?
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* how can you do devices that change their address map during operation, like mac which puts rom at 0 and ram at 600000 temporarily
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* i need a better way of handling disperate reads/writes to I/O spaces, rather than having multiple devices or having a massive chunk of address space allocated, continuously
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* should you modify Addressable to also take the absolute address as input? I'm thinking of how the same device could be mapped to multiple addresses in memory instead
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of taking up a whole range of addresses
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* could have a remapper device, which takes a big swath of addresses in and maps them to another set of addresses (for Mac VIA generic to bus-hookup-in-mac adapter)
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* could you use a generic sharable signal thing for sharing data, such as the VIA in mac128 where a single output bit determines the video mode (which would be a separate device)
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So both could share the same Signal, one setting it and the other reading it, but how would you actually configure/build that?
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* you could modify read()/write() in Addressable to return the number of bytes read or written for dynamic bus sizing used by the MC68020+
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* should you simulate bus arbitration?
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Genesis/Mega Drive:
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* fix ym7101 to better handle V/H interrupts (right now it sets and then the next step will clear, but it'd be nice if it could 'edge trigger')
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* YM7101 timing is causing it to be very slow... speeding this up increasing rendering speed a lot, even though the frame shouldn't be drawn that often... not sure what's wrong with the timing
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* make the ym7101 set/reset the v_int occurred flag based on the interrupt controller
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68000:
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* add instruction timing to M68k
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* make tests for each instruction
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* check all instructions in the docs
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* unimplemented: ABCD, ADDX, BFFFO, BFINS, BKPT, CHK, ILLEGAL, MOVEfromCCR,, RTR, RTD, SBCD, SUBX
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* >=MC68020 undecoded & unimplemented: CALLM, CAS, CAS2, CHK2, CMP2, RTM, PACK, TRAPcc, UNPK
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* add support for MMU
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* add support for FPU
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* Coprocessor instructions: cpBcc, cpDBcc, cpGEN, cpScc, cpTRAPcc
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Z80:
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* add instruction timings to Z80
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* how can you have multiple CPUs
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* can you eventually make the system connections all configurable via a config file?
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