mirror of
https://github.com/transistorfet/moa.git
synced 2024-06-03 23:29:29 +00:00
586a16509f
It can encode some basic instructions but not the more complicated addressing modes or special instructions. It can keep track of labels and patch the displacement addresses after assembling the output data, but it doesn't check for duplicates or that a label has been declared before it appears. It also doesn't take into account the origin yet. To run it, there is an m68kas command that will take a file and print the data: ``` cargo run -p moa --bin m68kas <filename> ``` It's not yet tied into the rest of the system, but could be used in the debugger to allow insertion of new code into a running system.
587 lines
23 KiB
Rust
587 lines
23 KiB
Rust
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use std::collections::HashMap;
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use crate::error::Error;
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use crate::parser::{AssemblyLine, AssemblyOperand, AssemblyParser};
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use crate::parser::{expect_args, expect_label, expect_immediate};
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use super::state::M68kType;
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use super::instructions::Size;
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#[repr(usize)]
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#[derive(Copy, Clone)]
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pub enum Disallow {
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None = 0x0000,
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NoDReg = 0x0001,
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NoAReg = 0x0002,
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NoIndirect = 0x0004,
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NoIndirectPre = 0x0008,
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NoIndirectPost = 0x0010,
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NoIndirectOffset = 0x0020,
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NoIndirectIndexReg = 0x0040,
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NoIndirectImmediate = 0x0080,
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NoImmediate = 0x0100,
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NoPCRelative = 0x0200,
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NoPCRelativeIndex = 0x0400,
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NoRegs = 0x0003,
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NoRegsOrImmediate = 0x0103,
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NoRegsImmediateOrPC = 0x0703,
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NoARegImmediateOrPC = 0x0702,
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NoRegsPrePostOrImmediate = 0x011B,
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NoImmediateOrPC = 0x0700,
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}
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impl Disallow {
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pub fn check(&self, lineno: usize, disallow: Disallow) -> Result<(), Error> {
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if (*self as usize) & (disallow as usize) == 0 {
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Ok(())
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} else {
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Err(Error::new(&format!("error at line {}: invalid addressing mode for the instruction", lineno)))
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}
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}
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}
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pub enum RelocationType {
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Displacement,
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Word(String),
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Long(String),
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}
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pub struct Relocation {
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pub rtype: RelocationType,
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pub label: String,
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pub index: usize,
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pub from_origin: usize,
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}
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impl Relocation {
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pub fn new(rtype: RelocationType, label: String, index: usize, from_origin: usize) -> Self {
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Self {
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rtype,
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label,
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index,
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from_origin,
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}
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}
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}
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pub struct M68kAssembler {
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pub cputype: M68kType,
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pub labels: HashMap<String, usize>,
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pub output: Vec<u16>,
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pub relocations: Vec<Relocation>,
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pub current_origin: usize,
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}
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impl M68kAssembler {
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pub fn new(cputype: M68kType) -> Self {
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Self {
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cputype,
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labels: HashMap::new(),
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output: vec![],
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relocations: vec![],
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current_origin: 0,
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}
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}
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pub fn assemble(&mut self, text: &str) -> Result<Vec<u8>, Error> {
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self.assemble_in_place(text)?;
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Ok(self.output.iter().fold(vec![], |mut acc, item| {
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acc.push((*item >> 8) as u8);
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acc.push(*item as u8);
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acc
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}))
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}
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pub fn assemble_words(&mut self, text: &str) -> Result<Vec<u16>, Error> {
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self.assemble_in_place(text)?;
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Ok(self.output.clone())
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}
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pub fn assemble_in_place(&mut self, text: &str) -> Result<(), Error> {
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let lines = self.parse(text)?;
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for (lineno, line) in lines {
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self.convert(lineno, &line)?;
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}
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self.apply_relocations()?;
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Ok(())
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}
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fn parse(&mut self, text: &str) -> Result<Vec<(usize, AssemblyLine)>, Error> {
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let mut output = vec![];
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let iter = text.split_terminator("\n");
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for (lineno, line_text) in iter.enumerate() {
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let mut parser = AssemblyParser::new(lineno, line_text);
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let parsed_line = parser.parse_line()?;
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if let Some(line) = parsed_line {
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output.push((lineno, line));
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}
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}
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Ok(output)
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}
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fn apply_relocations(&mut self) -> Result<(), Error> {
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for reloc in self.relocations.iter() {
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match reloc.rtype {
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RelocationType::Displacement => {
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// TODO this doesn't yet take into accound the origin
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let location = *self.labels.get(&reloc.label).ok_or_else(|| Error::new(&format!("error during relocation, label undefined {:?}", reloc.label)))?;
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self.output[reloc.index] |= ((self.output[reloc.index] as i8 * 2 + 2) - (location as i8 * 2)) as u16 & 0x00ff;
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},
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_ => panic!("relocation type unimplemented"),
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}
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}
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Ok(())
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}
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fn convert(&mut self, lineno: usize, line: &AssemblyLine) -> Result<(), Error> {
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match line {
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AssemblyLine::Directive(name, list) => {
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println!("skipping directive {} ({:?})", name, list);
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},
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AssemblyLine::Label(label) => {
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println!("label {}", label);
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self.labels.insert(label.clone(), self.output.len() - 1);
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},
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AssemblyLine::Instruction(name, list) => {
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self.convert_instruction(lineno, &name, &list)?;
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},
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}
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Ok(())
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}
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fn convert_instruction(&mut self, lineno: usize, mneumonic: &str, args: &[AssemblyOperand]) -> Result<(), Error> {
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match mneumonic {
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"bra" => {
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let label = expect_label(lineno, args)?;
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self.output.push(0x6000);
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self.relocations.push(Relocation::new(RelocationType::Displacement, label, self.output.len() - 1, self.current_origin));
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},
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"bsr" => {
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let label = expect_label(lineno, args)?;
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self.output.push(0x6100);
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self.relocations.push(Relocation::new(RelocationType::Displacement, label, self.output.len() - 1, self.current_origin));
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},
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"illegal" => {
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self.output.push(0x4AFC);
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},
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"lea" => {
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expect_args(lineno, args, 2)?;
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let reg = expect_address_register(lineno, &args[0])?;
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let (effective_address, additional_words) = convert_target(lineno, &args[1], Size::Long, Disallow::NoRegsPrePostOrImmediate)?;
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self.output.push(0x41C0 | (reg << 9) | effective_address);
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self.output.extend(additional_words);
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},
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"nop" => {
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self.output.push(0x4E71);
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},
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"rts" => {
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self.output.push(0x4E75);
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},
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"rte" => {
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self.output.push(0x4E73);
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},
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"rtr" => {
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self.output.push(0x4E77);
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},
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"stop" => {
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let immediate = expect_immediate(lineno, &args[0])?;
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self.output.push(0x4E72);
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self.output.extend(convert_immediate(lineno, immediate, Size::Word)?);
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},
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"trapv" => {
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self.output.push(0x4E76);
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},
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_ => {
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self.convert_sized_instruction(lineno, mneumonic, args)?;
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},
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}
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Ok(())
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}
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fn convert_sized_instruction(&mut self, lineno: usize, mneumonic: &str, args: &[AssemblyOperand]) -> Result<(), Error> {
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let operation_size = get_size_from_mneumonic(mneumonic).ok_or_else(|| Error::new(&format!("error at line {}: expected a size specifier (b/w/l)", lineno)));
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match &mneumonic[..mneumonic.len() - 1] {
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"addi" | "addai" => {
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self.convert_common_immediate_instruction(lineno, 0x0600, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"add" | "adda" => {
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self.convert_common_dreg_instruction(lineno, 0xD000, args, operation_size?, Disallow::None)?;
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},
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"andi" => {
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if !self.check_convert_flags_instruction(lineno, 0x23C, 0x27C, args)? {
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self.convert_common_immediate_instruction(lineno, 0x0200, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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}
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},
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"and" => {
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self.convert_common_dreg_instruction(lineno, 0xC000, args, operation_size?, Disallow::None)?;
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},
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"asr" | "asl" => {
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self.convert_common_shift_instruction(lineno, mneumonic, 0xE000, args, operation_size?)?;
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},
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"clr" => {
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self.convert_common_single_operand_instruction(lineno, 0x4200, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"cmpi" => {
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self.convert_common_immediate_instruction(lineno, 0x0C00, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"cmp" => {
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self.convert_common_dreg_instruction(lineno, 0xB000, args, operation_size?, Disallow::None)?;
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},
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"eori" => {
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if !self.check_convert_flags_instruction(lineno, 0x0A3C, 0x0A7C, args)? {
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self.convert_common_immediate_instruction(lineno, 0x0A00, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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}
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},
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"eor" => {
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self.convert_common_dreg_instruction(lineno, 0xB000, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"lsr" | "lsl" => {
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self.convert_common_shift_instruction(lineno, mneumonic, 0xE008, args, operation_size?)?;
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},
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"move" | "movea" => {
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let operation_size = operation_size?;
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expect_args(lineno, args, 2)?;
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let (effective_address_left, additional_words_left) = convert_target(lineno, &args[0], operation_size, Disallow::None)?;
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let (effective_address_right, additional_words_right) = convert_target(lineno, &args[1], operation_size, Disallow::None)?;
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let effective_address_left = (effective_address_left >> 3) | (effective_address_left << 3);
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self.output.push(0x0000 | encode_size_for_move(operation_size) | effective_address_left | effective_address_right);
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self.output.extend(additional_words_left);
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self.output.extend(additional_words_right);
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},
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"neg" => {
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self.convert_common_single_operand_instruction(lineno, 0x4400, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"negx" => {
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self.convert_common_single_operand_instruction(lineno, 0x4000, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"not" => {
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self.convert_common_single_operand_instruction(lineno, 0x4600, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"ori" => {
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if !self.check_convert_flags_instruction(lineno, 0x003C, 0x007C, args)? {
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self.convert_common_immediate_instruction(lineno, 0x0000, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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}
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},
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"or" => {
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self.convert_common_dreg_instruction(lineno, 0x8000, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"ror" | "rol" => {
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self.convert_common_shift_instruction(lineno, mneumonic, 0xE018, args, operation_size?)?;
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},
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"roxr" | "roxl" => {
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self.convert_common_shift_instruction(lineno, mneumonic, 0xE010, args, operation_size?)?;
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},
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"subi" | "subai" => {
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self.convert_common_immediate_instruction(lineno, 0x0400, args, operation_size?, Disallow::NoARegImmediateOrPC)?;
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},
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"sub" | "suba" => {
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self.convert_common_dreg_instruction(lineno, 0x9000, args, operation_size?, Disallow::None)?;
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},
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// TODO complete remaining instructions
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_ => return Err(Error::new(&format!("unrecognized instruction at line {}: {:?}", lineno, mneumonic))),
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}
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Ok(())
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}
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fn convert_common_immediate_instruction(&mut self, lineno: usize, opcode: u16, args: &[AssemblyOperand], operation_size: Size, disallow: Disallow) -> Result<(), Error> {
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expect_args(lineno, args, 2)?;
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let immediate = expect_immediate(lineno, &args[0])?;
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let (effective_address, additional_words) = convert_target(lineno, &args[1], operation_size, disallow)?;
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self.output.push(opcode | encode_size(operation_size) | effective_address);
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self.output.extend(convert_immediate(lineno, immediate, operation_size)?);
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self.output.extend(additional_words);
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Ok(())
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}
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fn convert_common_dreg_instruction(&mut self, lineno: usize, opcode: u16, args: &[AssemblyOperand], operation_size: Size, disallow: Disallow) -> Result<(), Error> {
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expect_args(lineno, args, 2)?;
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let (direction, reg, operand) = convert_reg_and_other(lineno, args, Disallow::NoAReg)?;
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let (effective_address, additional_words) = convert_target(lineno, operand, operation_size, disallow)?;
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self.output.push(opcode | encode_size(operation_size) | direction | (reg << 9) | effective_address);
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self.output.extend(additional_words);
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Ok(())
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}
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fn convert_common_single_operand_instruction(&mut self, lineno: usize, opcode: u16, args: &[AssemblyOperand], operation_size: Size, disallow: Disallow) -> Result<(), Error> {
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expect_args(lineno, args, 1)?;
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let (effective_address, additional_words) = convert_target(lineno, &args[0], operation_size, disallow)?;
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self.output.push(opcode | encode_size(operation_size) | effective_address);
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self.output.extend(additional_words);
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Ok(())
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}
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fn check_convert_flags_instruction(&mut self, lineno: usize, opcode_ccr: u16, opcode_sr: u16, args: &[AssemblyOperand]) -> Result<bool, Error> {
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if let AssemblyOperand::Register(name) = &args[1] {
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let opcode = match name.as_str() {
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"ccr" => Some(opcode_ccr),
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"sr" => Some(opcode_sr),
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_ => None,
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};
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if let Some(opcode) = opcode {
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expect_args(lineno, args, 2)?;
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let immediate = expect_immediate(lineno, &args[0])?;
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self.output.push(opcode);
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self.output.extend(convert_immediate(lineno, immediate, Size::Word)?);
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return Ok(true);
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}
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}
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Ok(false)
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}
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fn convert_common_shift_instruction(&mut self, lineno: usize, mneumonic: &str, opcode: u16, args: &[AssemblyOperand], operation_size: Size) -> Result<(), Error> {
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let dirstr = &mneumonic[mneumonic.len() - 2..mneumonic.len() - 1];
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let direction = if dirstr == "r" {
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0
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} else if dirstr == "l" {
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1 << 8
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} else {
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return Err(Error::new(&format!("error at line {}: expected direction of (l)eft or (r)ight, but found {:?}", lineno, dirstr)));
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};
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match &args {
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&[AssemblyOperand::Immediate(_), AssemblyOperand::Register(_)] => {
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let mut immediate = expect_immediate(lineno, &args[0])?;
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if immediate < 1 || immediate > 8 {
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return Err(Error::new(&format!("error at line {}: immediate value must be between 1 and 8, found {:?}", lineno, args)));
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} else if immediate == 8 {
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immediate = 0;
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}
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let reg = expect_data_register(lineno, &args[1])?;
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self.output.push(opcode | ((immediate as u16) << 9) | direction | encode_size(operation_size) | (0b0 << 5) | reg);
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},
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&[AssemblyOperand::Register(_), AssemblyOperand::Register(_)] => {
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let bit_reg = expect_data_register(lineno, &args[0])?;
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let reg = expect_data_register(lineno, &args[1])?;
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self.output.push(opcode | ((bit_reg as u16) << 9) | direction | encode_size(operation_size) | (0b1 << 5) | reg);
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},
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//&[_] => {
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// let (effective_address, additional_words) = convert_target(lineno, &args[0], Size::Word, Disallow::NoRegsImmediateOrPC)?;
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// self.output.push(opcode | effective_address);
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// self.output.extend(additional_words);
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//},
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_ => return Err(Error::new(&format!("error at line {}: unexpected addressing mode, found {:?}", lineno, args))),
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}
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Ok(())
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}
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}
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fn convert_target(lineno: usize, operand: &AssemblyOperand, size: Size, disallow: Disallow) -> Result<(u16, Vec<u16>), Error> {
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match operand {
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AssemblyOperand::Register(name) => {
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convert_register(lineno, name, disallow)
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},
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AssemblyOperand::Immediate(value) => {
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disallow.check(lineno, Disallow::NoImmediate)?;
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Ok((0b111100, convert_immediate(lineno, *value, size)?))
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},
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AssemblyOperand::Indirect(args) => {
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convert_indirect(lineno, args, disallow)
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},
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AssemblyOperand::IndirectPost(args, operator) => {
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disallow.check(lineno, Disallow::NoIndirectPost)?;
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if args.len() == 1 && operator == "+" {
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if let AssemblyOperand::Register(name) = &args[0] {
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if name.starts_with("a") {
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let reg = expect_reg_num(lineno, name)?;
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return Ok(((0b011 << 3) | reg, vec![]));
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}
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}
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}
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Err(Error::new(&format!("error at line {}: post-increment operator can only be used with a single address register", lineno)))
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},
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AssemblyOperand::IndirectPre(operator, args) => {
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disallow.check(lineno, Disallow::NoIndirectPre)?;
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if args.len() == 1 && operator == "-" {
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if let AssemblyOperand::Register(name) = &args[0] {
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if name.starts_with("a") {
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let reg = expect_reg_num(lineno, name)?;
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return Ok(((0b100 << 3) | reg, vec![]));
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}
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}
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}
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Err(Error::new(&format!("error at line {}: pre-decrement operator can only be used with a single address register", lineno)))
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},
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// TODO complete remaining types
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_ => Err(Error::new(&format!("not implemented: {:?}", operand))),
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}
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}
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fn convert_register(lineno: usize, name: &str, disallow: Disallow) -> Result<(u16, Vec<u16>), Error> {
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match name {
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name if name.starts_with("d") => {
|
|
disallow.check(lineno, Disallow::NoDReg)?;
|
|
let reg = expect_reg_num(lineno, name)?;
|
|
Ok(((0b000 << 3) | reg, vec![]))
|
|
},
|
|
name if name.starts_with("a") => {
|
|
disallow.check(lineno, Disallow::NoAReg)?;
|
|
let reg = expect_reg_num(lineno, name)?;
|
|
Ok(((0b001 << 3) | reg, vec![]))
|
|
},
|
|
"sp" => {
|
|
disallow.check(lineno, Disallow::NoAReg)?;
|
|
Ok(((0b001 << 3) | 7, vec![]))
|
|
},
|
|
_ => Err(Error::new(&format!("error at line {}: invalid register {:?}", lineno, name))),
|
|
}
|
|
}
|
|
|
|
fn convert_indirect(lineno: usize, args: &[AssemblyOperand], disallow: Disallow) -> Result<(u16, Vec<u16>), Error> {
|
|
match &args {
|
|
&[AssemblyOperand::Register(name)] => {
|
|
disallow.check(lineno, Disallow::NoIndirect)?;
|
|
let reg = expect_address_reg_num(lineno, name)?;
|
|
Ok(((0b010 << 3) | reg, vec![]))
|
|
},
|
|
&[AssemblyOperand::Immediate(address)] => {
|
|
disallow.check(lineno, Disallow::NoIndirectImmediate)?;
|
|
if *address < u16::MAX as usize {
|
|
Ok((0b111000, convert_immediate(lineno, *address, Size::Word)?))
|
|
} else {
|
|
Ok((0b111001, convert_immediate(lineno, *address, Size::Long)?))
|
|
}
|
|
},
|
|
&[AssemblyOperand::Immediate(offset), AssemblyOperand::Register(name)] => {
|
|
if name == "pc" {
|
|
disallow.check(lineno, Disallow::NoPCRelative)?;
|
|
Ok((0b111010, convert_immediate(lineno, *offset, Size::Word)?))
|
|
} else {
|
|
disallow.check(lineno, Disallow::NoIndirectOffset)?;
|
|
let reg = expect_address_reg_num(lineno, name)?;
|
|
Ok(((0b101 << 3) | reg, convert_immediate(lineno, *offset, Size::Word)?))
|
|
}
|
|
},
|
|
// TODO add the index register mode
|
|
_ => {
|
|
Err(Error::new(&format!("error at line {}: expected valid indirect addressing mode, but found {:?}", lineno, args)))
|
|
}
|
|
}
|
|
}
|
|
|
|
fn convert_reg_and_other<'a>(lineno: usize, args: &'a [AssemblyOperand], disallow: Disallow) -> Result<(u16, u16, &'a AssemblyOperand), Error> {
|
|
match &args {
|
|
&[AssemblyOperand::Register(reg), effective_address] => {
|
|
Ok(((0b1 << 8), expect_reg_num(lineno, ®)?, effective_address))
|
|
},
|
|
&[effective_address, AssemblyOperand::Register(reg)] => {
|
|
Ok(((0b0 << 8), expect_reg_num(lineno, ®)?, effective_address))
|
|
},
|
|
_ => {
|
|
Err(Error::new(&format!("error at line {}: expected register and effective address, but found {:?}", lineno, args)))
|
|
}
|
|
}
|
|
}
|
|
|
|
fn convert_immediate(lineno: usize, value: usize, size: Size) -> Result<Vec<u16>, Error> {
|
|
match size {
|
|
Size::Byte => {
|
|
if value < u8::MAX as usize {
|
|
Ok(vec![value as u16])
|
|
} else {
|
|
Err(Error::new(&format!("error at line {}: immediate number is out of range; must be less than {}, but number is {:?}", lineno, u8::MAX, value)))
|
|
}
|
|
},
|
|
Size::Word => {
|
|
if value < u16::MAX as usize {
|
|
Ok(vec![value as u16])
|
|
} else {
|
|
Err(Error::new(&format!("error at line {}: immediate number is out of range; must be less than {}, but number is {:?}", lineno, u16::MAX, value)))
|
|
}
|
|
},
|
|
Size::Long => Ok(vec![(value >> 16) as u16, value as u16]),
|
|
}
|
|
}
|
|
|
|
fn expect_data_register(lineno: usize, operand: &AssemblyOperand) -> Result<u16, Error> {
|
|
if let AssemblyOperand::Register(name) = operand {
|
|
if name.starts_with("d") {
|
|
return expect_reg_num(lineno, name);
|
|
}
|
|
}
|
|
Err(Error::new(&format!("error at line {}: expected a data register, but found {:?}", lineno, operand)))
|
|
}
|
|
|
|
fn expect_address_register(lineno: usize, operand: &AssemblyOperand) -> Result<u16, Error> {
|
|
if let AssemblyOperand::Register(name) = operand {
|
|
if name.starts_with("d") {
|
|
return expect_reg_num(lineno, name);
|
|
}
|
|
}
|
|
Err(Error::new(&format!("error at line {}: expected an address register, but found {:?}", lineno, operand)))
|
|
}
|
|
|
|
fn expect_address_reg_num(lineno: usize, name: &str) -> Result<u16, Error> {
|
|
if name.starts_with("a") {
|
|
return expect_reg_num(lineno, name);
|
|
}
|
|
Err(Error::new(&format!("error at line {}: expected an address register, but found {:?}", lineno, name)))
|
|
}
|
|
|
|
fn expect_reg_num(lineno: usize, name: &str) -> Result<u16, Error> {
|
|
if let Ok(number) = str::parse::<u16>(&name[1..]) {
|
|
if number <= 7 {
|
|
return Ok(number);
|
|
}
|
|
}
|
|
Err(Error::new(&format!("error at line {}: no such register {:?}", lineno, name)))
|
|
}
|
|
|
|
|
|
fn get_size_from_mneumonic(s: &str) -> Option<Size> {
|
|
let size_ch = s.chars().last()?;
|
|
match size_ch {
|
|
'b' => Some(Size::Byte),
|
|
'w' => Some(Size::Word),
|
|
'l' => Some(Size::Long),
|
|
_ => None
|
|
}
|
|
}
|
|
|
|
fn encode_size(size: Size) -> u16 {
|
|
match size {
|
|
Size::Byte => 0b00 << 6,
|
|
Size::Word => 0b01 << 6,
|
|
Size::Long => 0b10 << 6,
|
|
}
|
|
}
|
|
|
|
fn encode_size_for_move(size: Size) -> u16 {
|
|
match size {
|
|
Size::Byte => 0b01 << 12,
|
|
Size::Word => 0b11 << 12,
|
|
Size::Long => 0b10 << 12,
|
|
}
|
|
}
|
|
|
|
fn encode_size_bit(size: Size) -> Result<u16, Error> {
|
|
match size {
|
|
Size::Word => Ok(0b01 << 6),
|
|
Size::Long => Ok(0b10 << 6),
|
|
_ => Err(Error::new(&format!("invalid size for this operation: {:?}", size)))
|
|
}
|
|
}
|
|
|