356 lines
17 KiB
Rust
356 lines
17 KiB
Rust
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use crate::M68kType;
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use crate::instructions::{Size, Sign, Direction, Target, Instruction};
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#[derive(Clone, Debug, PartialEq, Eq)]
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pub struct M68kInstructionTiming {
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pub cputype: M68kType,
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pub bus_size: Size,
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pub accesses: u8,
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pub internal: u8,
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pub on_branch: u8,
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pub per_rep: u8,
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}
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impl M68kInstructionTiming {
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pub fn new(cputype: M68kType, bus_width: u8) -> Self {
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let bus_size = if bus_width <= 16 { Size::Word } else { Size::Long };
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Self {
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cputype,
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bus_size,
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accesses: 0,
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internal: 0,
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on_branch: 0,
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per_rep: 0,
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}
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}
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pub fn reset(&mut self) {
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self.accesses = 0;
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self.internal = 0;
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self.on_branch = 0;
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self.per_rep = 0;
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}
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#[inline(always)]
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pub fn add_access(&mut self, size: Size) -> &mut Self {
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self.accesses += self.access_size(size);
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self
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}
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#[inline(always)]
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pub fn add_internal(&mut self, clocks: u8) -> &mut Self {
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self.internal += clocks;
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self
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}
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#[inline(always)]
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pub fn sub_internal(&mut self, clocks: u8) -> &mut Self {
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self.internal = self.internal.saturating_sub(clocks);
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self
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}
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#[inline(always)]
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pub fn add_if_long(&mut self, size: Size, clocks: u8) -> &mut Self {
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self.internal += if size == Size::Long { clocks } else { 0 };
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self
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}
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#[inline(always)]
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pub fn add_reg_v_mem(&mut self, target: &Target, reg: u8, mem: u8) -> &mut Self {
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self.internal += match target {
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Target::DirectDReg(_) |
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Target::DirectAReg(_) => reg,
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_ => mem,
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};
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self
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}
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#[inline(always)]
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pub fn add_word_v_long(&mut self, size: Size, word: u8, long: u8) -> &mut Self {
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self.internal += if size != Size::Long { word } else { long };
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self
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}
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#[inline(always)]
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pub fn add_standard_set(&mut self, size: Size, target: &Target, areg: (u8, u8), dreg: (u8, u8), mem: (u8, u8)) -> &mut Self {
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match target {
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Target::DirectDReg(_) => self.add_word_v_long(size, dreg.0, dreg.1),
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Target::DirectAReg(_) => self.add_word_v_long(size, areg.0, dreg.1),
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_ => self.add_word_v_long(size, mem.0, mem.1),
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}
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}
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#[inline(always)]
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pub fn add_immediate_set(&mut self, size: Size, target: &Target, reg: (u8, u8), mem: (u8, u8)) -> &mut Self {
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match target {
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Target::DirectDReg(_) | Target::DirectAReg(_) => self.add_word_v_long(size, reg.0, reg.1),
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_ => self.add_word_v_long(size, mem.0, mem.1)
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}
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}
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#[inline(always)]
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pub fn add_indirect_set(&mut self, target: &Target, areg: u8, aoff: u8, indoff: u8, indw: u8, indl: u8) -> &mut Self {
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match target {
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Target::IndirectAReg(_) => self.add_internal(areg),
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Target::IndirectRegOffset(_, None, _) => self.add_internal(aoff),
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Target::IndirectRegOffset(_, Some(_), _) => self.add_internal(indoff),
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Target::IndirectMemory(_, Size::Long) => self.add_internal(indl),
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Target::IndirectMemory(_, _) => self.add_internal(indw),
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_ => panic!("This timing set can't be used with {:?} targetting", target),
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}
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}
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#[inline(always)]
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pub fn add_reg_mem_set(&mut self, size: Size, target: &Target, reg: (u8, u8), mem: (u8, u8)) -> &mut Self {
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match target {
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Target::DirectDReg(_) | Target::DirectAReg(_) => self.add_word_v_long(size, reg.0, reg.1),
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_ => self.add_word_v_long(size, mem.0, mem.1)
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}
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}
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#[inline(always)]
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pub fn add_on_branch(&mut self, clocks: u8) -> &mut Self {
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self.on_branch += clocks;
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self
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}
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#[inline(always)]
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pub fn add_per_rep(&mut self, clocks: u8) -> &mut Self {
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self.per_rep += clocks;
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self
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}
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pub fn add_target(&mut self, size: Size, target: &Target) -> &mut Self {
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match target {
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Target::Immediate(_) => self.add_access(size),
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Target::DirectDReg(_) => self,
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Target::DirectAReg(_) => self,
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Target::IndirectAReg(_) => self.add_access(size),
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Target::IndirectARegInc(_) => self.add_access(size),
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Target::IndirectARegDec(_) => self.add_access(size).add_internal(2),
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Target::IndirectRegOffset(_, index_reg, _) => {
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match index_reg {
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None => self.add_access(size).add_internal(4),
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Some(_) => self.add_access(size).add_internal(6),
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}
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},
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Target::IndirectMemoryPreindexed(_, index_reg, _, _) |
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Target::IndirectMemoryPostindexed(_, index_reg, _, _) => {
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// TODO this is very wrong, but the 68020 timings are complicated
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match index_reg {
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None => self.add_access(size).add_internal(4),
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Some(_) => self.add_access(size).add_internal(6),
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}
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},
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Target::IndirectMemory(_, addr_size) => self.add_access(*addr_size).add_access(size),
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}
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}
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pub fn add_two_targets(&mut self, size: Size, src: &Target, dest: &Target) -> &mut Self {
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match (src, dest) {
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(Target::IndirectARegDec(_), Target::IndirectARegDec(_)) => self.add_target(size, src).add_target(size, dest).sub_internal(2),
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_ => self.add_target(size, src).add_target(size, dest),
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}
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}
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pub fn add_movem(&mut self, size: Size, target: &Target, dir: Direction, n: u8) -> &mut Self {
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if dir == Direction::FromTarget {
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match target {
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Target::IndirectAReg(_) => self.add_word_v_long(size, 12 + 4 * n, 12 + 8 * n),
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Target::IndirectARegInc(_) => self.add_word_v_long(size, 12 + 4 * n, 12 + 8 * n),
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Target::IndirectRegOffset(_, None, _) => self.add_word_v_long(size, 16 + 4 * n, 16 + 8 * n),
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Target::IndirectRegOffset(_, Some(_), _) => self.add_word_v_long(size, 18 + 4 * n, 18 + 8 * n),
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Target::IndirectMemory(_, Size::Long) => self.add_word_v_long(size, 20 + 4 * n, 20 + 8 * n),
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Target::IndirectMemory(_, _) => self.add_word_v_long(size, 16 + 4 * n, 16 + 8 * n),
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_ => panic!("This timing set can't be used with {:?} targetting", target),
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}
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} else {
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match target {
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Target::IndirectAReg(_) => self.add_word_v_long(size, 8 + 4 * n, 8 + 8 * n),
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Target::IndirectARegDec(_) => self.add_word_v_long(size, 8 + 4 * n, 8 + 8 * n),
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Target::IndirectRegOffset(_, None, _) => self.add_word_v_long(size, 12 + 4 * n, 12 + 8 * n),
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Target::IndirectRegOffset(_, Some(_), _) => self.add_word_v_long(size, 14 + 4 * n, 14 + 8 * n),
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Target::IndirectMemory(_, Size::Long) => self.add_word_v_long(size, 16 + 4 * n, 16 + 8 * n),
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Target::IndirectMemory(_, _) => self.add_word_v_long(size, 12 + 4 * n, 12 + 8 * n),
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_ => panic!("This timing set can't be used with {:?} targetting", target),
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}
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}
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}
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pub fn add_instruction(&mut self, instruction: &Instruction) -> &mut Self {
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match self.cputype {
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M68kType::MC68000 | M68kType::MC68010 => self.add_instruction_68000(instruction),
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_ => self.add_instruction_68020(instruction),
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}
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}
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pub fn add_instruction_68000(&mut self, instruction: &Instruction) -> &mut Self {
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match instruction {
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Instruction::ABCD(_, dest) => self.add_reg_v_mem(dest, 6, 18),
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Instruction::ADD(Target::Immediate(x), dest, size) if *x <= 8 => self.add_immediate_set(*size, dest, (4, 8), (8, 12)).add_target(*size, dest),// ADDQ
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Instruction::ADD(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest), // ADDI
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Instruction::ADD(src, dest, size) => self.add_standard_set(*size, dest, (8, 6), (4, 6), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::ADDA(target, _, size) => self.add_word_v_long(*size, 8, 6).add_target(*size, target),
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Instruction::ADDX(_, dest, size) => self.add_reg_mem_set(*size, dest, (4, 8), (18, 30)),
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Instruction::AND(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 14), (12, 20)).add_target(*size, dest),
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Instruction::AND(src, dest, size) => self.add_standard_set(*size, dest, (0, 0), (4, 6), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::ANDtoCCR(_) => self.add_internal(20),
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Instruction::ANDtoSR(_) => self.add_internal(20),
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Instruction::ASd(_, target, size, _) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::Bcc(_, _) => self.add_internal(8).add_on_branch(2),
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Instruction::BRA(_) => self.add_internal(10),
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Instruction::BSR(_) => self.add_internal(18),
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Instruction::BCHG(bit, target, size) => match bit {
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Target::Immediate(_) => self.add_reg_v_mem(target, 12, 12),
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_ => self.add_reg_v_mem(target, 8, 8),
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}.add_target(*size, target),
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Instruction::BCLR(bit, target, size) => match bit {
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Target::Immediate(_) => self.add_reg_v_mem(target, 14, 12),
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_ => self.add_reg_v_mem(target, 10, 8),
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}.add_target(*size, target),
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Instruction::BSET(bit, target, size) => match bit {
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Target::Immediate(_) => self.add_reg_v_mem(target, 12, 12),
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_ => self.add_reg_v_mem(target, 8, 8),
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}.add_target(*size, target),
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Instruction::BTST(bit, target, size) => match bit {
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Target::Immediate(_) => self.add_reg_v_mem(target, 10, 8),
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_ => self.add_reg_v_mem(target, 6, 4),
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}.add_target(*size, target),
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Instruction::CHK(_, _, _) => self.add_internal(10),
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Instruction::CLR(target, size) => self.add_reg_v_mem(target, 4, 8).add_word_v_long(*size, 0, 2).add_target(*size, target),
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Instruction::CMP(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 14), (8, 12)).add_target(*size, dest),
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Instruction::CMP(src, dest, size) => self.add_standard_set(*size, dest, (6, 6), (4, 6), (0, 0)).add_two_targets(*size, src, dest),
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Instruction::CMPA(target, _, size) => self.add_word_v_long(*size, 6, 6).add_target(*size, target),
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Instruction::DBcc(_, _, _) => self.add_internal(10).add_on_branch(4),
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Instruction::DIVW(src, _, sign) => match sign {
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Sign::Unsigned => self.add_internal(140).add_target(Size::Long, src),
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Sign::Signed => self.add_internal(158).add_target(Size::Long, src),
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},
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Instruction::EOR(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest),
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Instruction::EOR(src, dest, size) => self.add_standard_set(*size, dest, (0, 0), (4, 8), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::EORtoCCR(_) => self.add_internal(20),
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Instruction::EORtoSR(_) => self.add_internal(20),
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Instruction::EXG(_, _) => self.add_internal(6),
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Instruction::EXT(_, _, _) => self.add_internal(4),
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Instruction::ILLEGAL => self.add_internal(4),
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Instruction::JMP(target) => self.add_indirect_set(target, 8, 10, 14, 10, 12),
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Instruction::JSR(target) => self.add_indirect_set(target, 16, 18, 22, 18, 20),
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Instruction::LEA(target, _) => self.add_indirect_set(target, 4, 8, 12, 8, 12),
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Instruction::LINK(_, _) => self.add_internal(16),
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Instruction::LSd(_, target, size, _) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::MOVE(src, dest, size) => self.add_internal(4).add_two_targets(*size, src, dest),
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Instruction::MOVEA(target, _, size) => self.add_internal(4).add_target(*size, target),
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Instruction::MOVEfromSR(target) => self.add_reg_v_mem(target, 6, 8).add_target(Size::Word, target),
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Instruction::MOVEtoSR(target) => self.add_internal(12).add_target(Size::Word, target),
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Instruction::MOVEfromCCR(target) => self.add_internal(12).add_target(Size::Word, target),
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Instruction::MOVEtoCCR(target) => self.add_internal(12).add_target(Size::Word, target),
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Instruction::MOVEC(target, _, _) => self.add_reg_v_mem(target, 10, 12),
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Instruction::MOVEM(target, size, dir, mask) => self.add_movem(*size, target, *dir, mask.count_ones() as u8),
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Instruction::MOVEP(_, _, _, size, _) => self.add_word_v_long(*size, 16, 24),
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Instruction::MOVEQ(_, _) => self.add_internal(4),
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Instruction::MOVEUSP(_, _) => self.add_internal(4),
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Instruction::MULW(src, _, _) => self.add_internal(70).add_target(Size::Word, src),
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Instruction::NBCD(target) => self.add_reg_v_mem(target, 6, 8),
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Instruction::NEG(target, size) => self.add_reg_mem_set(*size, target, (4, 6), (8, 12)).add_target(*size, target),
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Instruction::NEGX(target, size) => self.add_reg_mem_set(*size, target, (4, 6), (8, 12)).add_target(*size, target),
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Instruction::NOP => self.add_internal(4),
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Instruction::NOT(target, size) => self.add_reg_mem_set(*size, target, (4, 6), (8, 12)).add_target(*size, target),
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Instruction::OR(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest),
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Instruction::OR(src, dest, size) => self.add_standard_set(*size, dest, (0, 0), (4, 6), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::ORtoCCR(_) => self.add_internal(20),
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Instruction::ORtoSR(_) => self.add_internal(20),
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Instruction::PEA(target) => self.add_indirect_set(target, 12, 16, 20, 16, 20),
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Instruction::RESET => self.add_internal(132),
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Instruction::ROd(_, target, size, _) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::ROXd(_, target, size, _) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::RTE => self.add_internal(20),
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Instruction::RTR => self.add_internal(20),
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Instruction::RTS => self.add_internal(16),
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//Instruction::RTD(offset) => ,
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Instruction::SBCD(_, dest) => self.add_reg_v_mem(dest, 6, 18),
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Instruction::Scc(_, target) => self.add_reg_v_mem(target, 4, 8).add_on_branch(2).add_target(Size::Byte, target),
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Instruction::STOP(_) => self.add_internal(4),
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Instruction::SUB(Target::Immediate(x), Target::DirectAReg(_), Size::Byte)
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| Instruction::SUB(Target::Immediate(x), Target::DirectAReg(_), Size::Word) if *x <= 8 => self.add_internal(8), // SUBQ with an address reg as dest
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Instruction::SUB(Target::Immediate(x), dest, size) if *x <= 8 => self.add_immediate_set(*size, dest, (4, 8), (8, 12)).add_target(*size, dest), // SUBQ
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Instruction::SUB(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest), // SUBI
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Instruction::SUB(src, dest, size) => self.add_standard_set(*size, dest, (0, 0), (4, 6), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::SUBA(target, _, size) => self.add_word_v_long(*size, 8, 6).add_target(*size, target),
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Instruction::SUBX(_, dest, size) => self.add_reg_mem_set(*size, dest, (4, 8), (18, 30)),
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Instruction::SWAP(_) => self.add_internal(4),
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Instruction::TAS(target) => self.add_reg_v_mem(target, 4, 14).add_target(Size::Byte, target),
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Instruction::TST(target, size) => self.add_internal(4).add_target(*size, target),
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Instruction::TRAP(_) => self.add_internal(34),
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Instruction::TRAPV => self.add_internal(34),
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Instruction::UNLK(_) => self.add_internal(12),
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Instruction::UnimplementedA(_) => self.add_internal(34),
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Instruction::UnimplementedF(_) => self.add_internal(34),
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_ => {
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//panic!("Unexpected instruction for cpu type {:?}: {:?}", self.cputype, instruction);
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self.add_internal(4)
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},
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}
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}
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pub fn add_instruction_68020(&mut self, _instruction: &Instruction) -> &mut Self {
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//match instruction {
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// // TODO implement
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// _ => self.add_internal(4),
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//}
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self.add_internal(4)
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}
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pub fn calculate_clocks(&self, branched: bool, reps: u16) -> u16 {
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//println!("{:?}", self);
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(self.accesses as u16 * 4)
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+ self.internal as u16
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+ (if branched { self.on_branch as u16 } else { 0 })
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+ self.per_rep as u16 * reps
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}
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#[inline(always)]
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pub fn access_size(&self, size: Size) -> u8 {
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if self.bus_size == Size::Word && size == Size::Long {
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2
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} else {
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1
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}
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}
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}
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