158 lines
4.1 KiB
Rust
158 lines
4.1 KiB
Rust
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use moa_core::{Address, BusPort, Signal};
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use crate::decode::Z80Decoder;
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use crate::debugger::Z80Debugger;
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#[allow(dead_code)]
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#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord)]
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pub enum Z80Type {
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Z80,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Status {
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Init,
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Running,
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Halted,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum InterruptMode {
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Mode0,
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Mode01,
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Mode1,
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Mode2,
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}
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#[repr(u8)]
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#[allow(dead_code)]
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Flags {
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Carry = 0x01,
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AddSubtract = 0x02,
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Parity = 0x04,
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F3 = 0x08,
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HalfCarry = 0x10,
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F5 = 0x20,
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Zero = 0x40,
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Sign = 0x80,
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}
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#[repr(u8)]
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Register {
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B = 0,
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C = 1,
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D = 2,
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E = 3,
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H = 4,
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L = 5,
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A = 6,
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F = 7,
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}
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#[derive(Clone, Debug, PartialEq, Eq)]
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pub struct Z80State {
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pub status: Status,
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pub interrupts_enabled: bool,
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pub interrupt_mode: InterruptMode,
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pub pc: u16,
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pub sp: u16,
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pub ix: u16,
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pub iy: u16,
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pub reg: [u8; 8],
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pub shadow_reg: [u8; 8],
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pub i: u8,
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pub r: u8,
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}
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impl Default for Z80State {
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fn default() -> Self {
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Self {
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status: Status::Init,
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interrupts_enabled: false,
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interrupt_mode: InterruptMode::Mode0,
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pc: 0,
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sp: 0,
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ix: 0,
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iy: 0,
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reg: [0; 8],
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shadow_reg: [0; 8],
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i: 0,
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r: 0,
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}
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}
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}
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impl Z80State {
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pub fn get_register(&mut self, reg: Register) -> u8 {
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self.reg[reg as usize]
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}
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pub fn set_register(&mut self, reg: Register, value: u8) {
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self.reg[reg as usize] = value;
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}
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}
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pub struct Z80 {
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pub cputype: Z80Type,
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pub frequency: u32,
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pub state: Z80State,
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pub decoder: Z80Decoder,
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pub debugger: Z80Debugger,
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pub port: BusPort,
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pub reset: Signal<bool>,
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pub bus_request: Signal<bool>,
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}
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impl Z80 {
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pub fn new(cputype: Z80Type, frequency: u32, port: BusPort) -> Self {
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Self {
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cputype,
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frequency,
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state: Z80State::default(),
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decoder: Z80Decoder::default(),
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debugger: Z80Debugger::default(),
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port,
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reset: Signal::new(false),
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bus_request: Signal::new(false),
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}
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}
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#[allow(dead_code)]
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pub fn clear_state(&mut self) {
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self.state = Z80State::default();
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self.decoder = Z80Decoder::default();
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self.debugger = Z80Debugger::default();
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}
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pub fn dump_state(&mut self) {
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println!("Status: {:?}", self.state.status);
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println!("PC: {:#06x}", self.state.pc);
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println!("SP: {:#06x}", self.state.sp);
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println!("IX: {:#06x}", self.state.ix);
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println!("IY: {:#06x}", self.state.iy);
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println!("A: {:#04x} F: {:#04x} A': {:#04x} F': {:#04x}", self.state.reg[Register::A as usize], self.state.reg[Register::F as usize], self.state.shadow_reg[Register::A as usize], self.state.shadow_reg[Register::F as usize]);
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println!("B: {:#04x} C: {:#04x} B': {:#04x} C': {:#04x}", self.state.reg[Register::B as usize], self.state.reg[Register::C as usize], self.state.shadow_reg[Register::B as usize], self.state.shadow_reg[Register::C as usize]);
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println!("D: {:#04x} E: {:#04x} D': {:#04x} E': {:#04x}", self.state.reg[Register::D as usize], self.state.reg[Register::E as usize], self.state.shadow_reg[Register::D as usize], self.state.shadow_reg[Register::E as usize]);
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println!("H: {:#04x} L: {:#04x} H': {:#04x} L': {:#04x}", self.state.reg[Register::H as usize], self.state.reg[Register::L as usize], self.state.shadow_reg[Register::H as usize], self.state.shadow_reg[Register::L as usize]);
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println!("Current Instruction: {} {:?}", self.decoder.format_instruction_bytes(&mut self.port), self.decoder.instruction);
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println!();
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self.port.dump_memory(self.state.sp as Address, 0x40);
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println!();
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}
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}
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