119 lines
3.6 KiB
Rust
119 lines
3.6 KiB
Rust
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use moa_core::{Error, System, ClockElapsed, Address, Addressable, Steppable, Transmutable, Signal, ObservableSignal, Observable, debug, warn};
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const REG_OUTPUT_B: Address = 0x00;
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const REG_OUTPUT_A: Address = 0x01;
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const REG_DDR_B: Address = 0x02;
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const REG_DDR_A: Address = 0x03;
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const REG_PERIPH_CTRL: Address = 0x0C;
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const REG_INT_FLAGS: Address = 0x0D;
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const REG_INT_ENABLE: Address = 0x0E;
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const REG_OUTPUT_A_NHS: Address = 0x0F;
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const DEV_NAME: &str = "mos6522";
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pub struct Port {
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pub data: u8,
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pub ddr: u8,
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}
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impl Default for Port {
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fn default() -> Self {
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Self {
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data: 0xff,
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ddr: 0,
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}
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}
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}
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pub struct Mos6522 {
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pub port_a: ObservableSignal<Port>,
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pub port_b: ObservableSignal<Port>,
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pub peripheral_ctrl: u8,
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pub interrupt: Signal<bool>,
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pub interrupt_flags: u8,
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pub interrupt_enable: u8,
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}
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impl Default for Mos6522 {
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fn default() -> Self {
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Self {
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port_a: ObservableSignal::new(Port::default()),
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port_b: ObservableSignal::new(Port::default()),
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peripheral_ctrl: 0,
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interrupt: Signal::new(false),
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interrupt_flags: 0,
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interrupt_enable: 0,
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}
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}
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}
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impl Addressable for Mos6522 {
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fn len(&self) -> usize {
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0x10
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}
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fn read(&mut self, addr: Address, data: &mut [u8]) -> Result<(), Error> {
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match addr {
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REG_OUTPUT_B => { data[0] = self.port_b.borrow_mut().data; },
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REG_OUTPUT_A => { data[0] = self.port_a.borrow_mut().data; },
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REG_DDR_B => { data[0] = self.port_b.borrow_mut().ddr; },
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REG_DDR_A => { data[0] = self.port_a.borrow_mut().ddr; },
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REG_INT_FLAGS => { data[0] = self.interrupt_flags; },
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REG_INT_ENABLE => { data[0] = self.interrupt_enable | 0x80; },
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_ => {
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warn!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
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},
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}
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debug!("{}: read from register {:x} of {:?}", DEV_NAME, addr, data);
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Ok(())
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}
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fn write(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
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debug!("{}: write to register {:x} with {:x}", DEV_NAME, addr, data[0]);
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match addr {
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REG_OUTPUT_B => { self.port_b.borrow_mut().data = data[0]; self.port_b.notify(); },
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REG_OUTPUT_A => { self.port_a.borrow_mut().data = data[0]; self.port_a.notify(); },
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REG_DDR_B => { self.port_b.borrow_mut().ddr = data[0]; self.port_b.notify(); },
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REG_DDR_A => { self.port_a.borrow_mut().ddr = data[0]; self.port_a.notify(); },
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REG_PERIPH_CTRL => { println!("SET TO {:?}", data[0]); self.peripheral_ctrl = data[0]; },
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REG_INT_FLAGS => { self.interrupt_flags &= !data[0] & 0x7F; },
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REG_INT_ENABLE => {
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if (data[0] & 0x80) == 0 {
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self.interrupt_flags &= !data[0];
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} else {
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self.interrupt_flags |= data[0];
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}
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},
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REG_OUTPUT_A_NHS => { self.port_a.borrow_mut().data = data[0]; self.port_a.notify(); },
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_ => {
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warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
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},
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}
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Ok(())
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}
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}
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impl Steppable for Mos6522 {
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fn step(&mut self, _system: &System) -> Result<ClockElapsed, Error> {
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Ok(16_600_000)
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}
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}
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impl Transmutable for Mos6522 {
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fn as_addressable(&mut self) -> Option<&mut dyn Addressable> {
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Some(self)
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}
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fn as_steppable(&mut self) -> Option<&mut dyn Steppable> {
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Some(self)
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}
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}
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