448 lines
11 KiB
Rust
448 lines
11 KiB
Rust
use core::cmp;
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use core::fmt::Write;
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use femtos::Instant;
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use emulator_hal::bus::BusAccess;
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use crate::state::{M68k, M68kError, CpuInfo, Exceptions};
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use crate::instructions::Size;
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#[repr(u8)]
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#[allow(dead_code)]
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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#[rustfmt::skip]
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pub enum FunctionCode {
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Reserved0 = 0,
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UserData = 1,
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UserProgram = 2,
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Reserved3 = 3,
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Reserved4 = 4,
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SupervisorData = 5,
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SupervisorProgram = 6,
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CpuSpace = 7,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum MemType {
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Program,
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Data,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum MemAccess {
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Read,
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Write,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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// TODO change to MemoryState or RequestState or AccessState or maybe even BusState
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pub struct MemoryRequest {
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pub i_n_bit: bool,
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pub access: MemAccess,
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pub code: FunctionCode,
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pub size: Size,
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pub address: u32,
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pub clock: Instant,
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}
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impl FunctionCode {
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pub fn program(is_supervisor: bool) -> Self {
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if is_supervisor {
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FunctionCode::SupervisorProgram
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} else {
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FunctionCode::UserProgram
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}
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}
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pub fn data(is_supervisor: bool) -> Self {
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if is_supervisor {
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FunctionCode::SupervisorData
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} else {
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FunctionCode::UserData
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}
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}
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}
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impl Default for MemoryRequest {
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fn default() -> Self {
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Self {
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i_n_bit: false,
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access: MemAccess::Read,
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code: FunctionCode::Reserved0,
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size: Size::Word,
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address: 0,
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clock: Instant::START,
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}
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}
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}
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impl MemoryRequest {
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pub(crate) fn instruction<BusError>(&mut self, is_supervisor: bool, addr: u32) -> Result<u32, M68kError<BusError>> {
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self.i_n_bit = false;
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self.code = FunctionCode::program(is_supervisor);
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self.access = MemAccess::Read;
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self.address = addr;
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validate_address(addr)
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}
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#[inline]
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pub fn get_type_code(&self) -> u16 {
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let ins = match self.i_n_bit {
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false => 0x0000,
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true => 0x0008,
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};
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let rw = match self.access {
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MemAccess::Write => 0x0000,
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MemAccess::Read => 0x0010,
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};
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ins | rw | (self.code as u16)
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}
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}
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//pub type M68kAddress = (FunctionCode, u32);
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pub type M68kAddress = u32;
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pub type M68kAddressSpace = (FunctionCode, u32);
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#[derive(Clone, Debug)]
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pub struct InstructionRequest {
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pub request: MemoryRequest,
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pub current_clock: Instant,
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}
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#[derive(Clone, Debug)]
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pub struct M68kBusPort {
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pub request: MemoryRequest,
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pub data_bytewidth: usize,
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pub address_mask: u32,
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pub cycle_start_clock: Instant,
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pub current_clock: Instant,
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}
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impl M68k {
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// TODO should some of the ones from execute.rs move here
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}
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impl Default for M68kBusPort {
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fn default() -> Self {
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Self {
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request: Default::default(),
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data_bytewidth: 32 / 8,
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address_mask: 0xFFFF_FFFF,
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cycle_start_clock: Instant::START,
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current_clock: Instant::START,
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}
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}
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}
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impl M68kBusPort {
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pub fn from_info(info: &CpuInfo, clock: Instant) -> Self {
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Self {
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request: Default::default(),
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data_bytewidth: info.data_width as usize / 8,
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address_mask: 1_u32.checked_shl(info.address_width as u32).unwrap_or(0).wrapping_sub(1),
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cycle_start_clock: clock,
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current_clock: clock,
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}
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}
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fn read<Bus, BusError>(
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&mut self,
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bus: &mut Bus,
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clock: Instant,
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addr: M68kAddress,
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data: &mut [u8],
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) -> Result<(), M68kError<BusError>>
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where
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Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
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{
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let addr = addr & self.address_mask;
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for i in (0..data.len()).step_by(self.data_bytewidth) {
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let addr_index = (addr + i as M68kAddress) & self.address_mask;
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let end = cmp::min(i + self.data_bytewidth, data.len());
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bus.read(clock, addr_index, &mut data[i..end])
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.map_err(|err| M68kError::BusError(err))?;
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}
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Ok(())
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}
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fn write<Bus, BusError>(
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&mut self,
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bus: &mut Bus,
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clock: Instant,
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addr: M68kAddress,
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data: &[u8],
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) -> Result<(), M68kError<BusError>>
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where
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Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
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{
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let addr = addr & self.address_mask;
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for i in (0..data.len()).step_by(self.data_bytewidth) {
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let addr_index = (addr + i as M68kAddress) & self.address_mask;
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let end = cmp::min(i + self.data_bytewidth, data.len());
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bus.write(clock, addr_index, &data[i..end])
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.map_err(|err| M68kError::BusError(err))?;
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}
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Ok(())
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}
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fn read_sized<Bus, BusError>(&mut self, bus: &mut Bus, addr: M68kAddress, size: Size) -> Result<u32, M68kError<BusError>>
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where
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Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
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{
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let mut data = [0; 4];
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match size {
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Size::Byte => self.read(bus, self.current_clock, addr, &mut data[3..4]),
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Size::Word => self.read(bus, self.current_clock, addr, &mut data[2..4]),
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Size::Long => self.read(bus, self.current_clock, addr, &mut data[0..4]),
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}
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.map(|_| u32::from_be_bytes(data))
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}
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fn write_sized<Bus, BusError>(
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&mut self,
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bus: &mut Bus,
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addr: M68kAddress,
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size: Size,
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value: u32,
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) -> Result<(), M68kError<BusError>>
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where
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Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
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{
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let data = value.to_be_bytes();
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match size {
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Size::Byte => self.write(bus, self.current_clock, addr, &data[3..4]),
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Size::Word => self.write(bus, self.current_clock, addr, &data[2..4]),
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Size::Long => self.write(bus, self.current_clock, addr, &data[0..4]),
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}
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}
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pub(crate) fn read_data_sized<Bus, BusError>(
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&mut self,
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bus: &mut Bus,
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is_supervisor: bool,
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addr: M68kAddress,
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size: Size,
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) -> Result<u32, M68kError<BusError>>
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where
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Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
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{
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self.start_request(is_supervisor, addr, size, MemAccess::Read, MemType::Data, false)?;
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self.read_sized(bus, addr, size)
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}
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pub(crate) fn write_data_sized<Bus, BusError>(
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&mut self,
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bus: &mut Bus,
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is_supervisor: bool,
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addr: M68kAddress,
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size: Size,
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value: u32,
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) -> Result<(), M68kError<BusError>>
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where
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Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
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{
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self.start_request(is_supervisor, addr, size, MemAccess::Write, MemType::Data, false)?;
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self.write_sized(bus, addr, size, value)
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}
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pub(crate) fn read_instruction_word<Bus, BusError>(
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&mut self,
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bus: &mut Bus,
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is_supervisor: bool,
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addr: u32,
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) -> Result<u16, M68kError<BusError>>
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where
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Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
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{
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self.request.instruction(is_supervisor, addr)?;
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Ok(self.read_sized(bus, addr, Size::Word)? as u16)
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}
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pub(crate) fn read_instruction_long<Bus, BusError>(
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&mut self,
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bus: &mut Bus,
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is_supervisor: bool,
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addr: u32,
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) -> Result<u32, M68kError<BusError>>
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where
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Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
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{
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self.request.instruction(is_supervisor, addr)?;
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self.read_sized(bus, addr, Size::Long)
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}
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pub(crate) fn start_request<BusError>(
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&mut self,
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is_supervisor: bool,
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addr: u32,
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size: Size,
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access: MemAccess,
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mtype: MemType,
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i_n_bit: bool,
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) -> Result<u32, M68kError<BusError>> {
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self.request.i_n_bit = i_n_bit;
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self.request.code = match mtype {
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MemType::Program => FunctionCode::program(is_supervisor),
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MemType::Data => FunctionCode::data(is_supervisor),
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};
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self.request.access = access;
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self.request.address = addr;
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if size == Size::Byte {
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Ok(addr)
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} else {
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validate_address(addr)
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}
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}
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}
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fn validate_address<BusError>(addr: u32) -> Result<u32, M68kError<BusError>> {
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if addr & 0x1 == 0 {
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Ok(addr)
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} else {
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Err(M68kError::Exception(Exceptions::AddressError))
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}
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}
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pub fn dump_memory<Bus, Address, Instant>(bus: &mut Bus, clock: Instant, addr: Address, count: Address)
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where
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Bus: BusAccess<Address, Instant>,
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Address: From<u32> + Into<u32> + Copy,
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Instant: Copy,
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{
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let mut addr = addr.into();
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let mut count = count.into();
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while count > 0 {
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let mut line = format!("{:#010x}: ", addr);
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let to = if count < 16 { count / 2 } else { 8 };
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for _ in 0..to {
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let word = bus.read_beu16(clock, Address::from(addr));
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if word.is_err() {
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println!("{}", line);
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return;
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}
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write!(line, "{:#06x} ", word.unwrap()).unwrap();
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addr += 2;
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count -= 2;
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}
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println!("{}", line);
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}
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}
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/*
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pub(crate) struct TargetAccess {
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must_read: bool,
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must_write: bool,
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size: Size,
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target: Target,
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}
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impl TargetAccess {
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pub(crate) fn read_only(size: Size) -> Self {
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}
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pub(crate) fn read_update(size: Size) -> Self {
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}
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pub(crate) fn updated_only(size: Size) -> Self {
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}
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pub(crate) fn get(&mut self, cpu: &M68k) -> Result<u32, M68kError> {
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}
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pub(crate) fn set(&mut self, cpu: &M68k, value: u32) -> Result<(), M68kError> {
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}
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pub(crate) fn complete(&self) -> Result<Self, M68kError> {
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}
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}
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impl Target {
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pub(crate) fn read_once(self, size: Size) -> ReadOnceAccess {
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ReadOnceAccess {
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size,
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target: self,
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accessed: false,
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}
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}
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pub(crate) fn read_update(self, size: Size) -> ReadUpdateAccess {
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ReadUpdateAccess {
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size,
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target: self,
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}
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}
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pub(crate) fn write_once(self, size: Size) -> WriteOnceAccess {
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WriteOnceAccess {
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size,
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target: self,
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}
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}
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}
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pub(crate) struct ReadOnceAccess {
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size: Size,
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target: Target,
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accessed: bool,
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}
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impl ReadOnceAccess {
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pub(crate) fn get(&mut self, cpu: &M68k) -> Result<u32, M68kError> {
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}
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pub(crate) fn complete(&self) -> Result<Self, M68kError> {
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}
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}
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pub(crate) struct ReadUpdateAccess {
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size: Size,
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target: Target,
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}
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impl ReadUpdateAccess {
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pub(crate) fn get(&mut self, cpu: &M68k) -> Result<u32, M68kError> {
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}
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pub(crate) fn set(&mut self, cpu: &M68k, value: u32) -> Result<(), M68kError> {
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}
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pub(crate) fn complete(&self) -> Result<Self, M68kError> {
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}
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}
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pub(crate) struct WriteOnceAccess {
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size: Size,
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target: Target,
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}
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impl WriteOnceAccess {
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pub(crate) fn set(&mut self, cpu: &M68k, value: u32) -> Result<(), M68kError> {
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}
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pub(crate) fn complete(&self) -> Result<Self, M68kError> {
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}
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}
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*/
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