208 lines
3.6 KiB
Rust
208 lines
3.6 KiB
Rust
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Direction {
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ToAcc,
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FromAcc,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Size {
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Byte,
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Word,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Condition {
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NotZero,
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Zero,
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NotCarry,
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Carry,
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ParityOdd,
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ParityEven,
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Positive,
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Negative,
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}
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#[repr(u8)]
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Register {
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B = 0,
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C = 1,
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D = 2,
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E = 3,
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H = 4,
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L = 5,
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A = 6,
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F = 7,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum RegisterPair {
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BC,
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DE,
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HL,
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AF,
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SP,
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IX,
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IY,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum IndexRegister {
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IX,
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IY,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum IndexRegisterHalf {
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IXH,
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IXL,
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IYH,
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IYL,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum SpecialRegister {
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I,
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R,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum InterruptMode {
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Mode0,
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Mode1,
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Mode2,
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Unknown(u8),
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Target {
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DirectReg(Register),
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DirectRegHalf(IndexRegisterHalf),
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IndirectReg(RegisterPair),
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IndirectOffset(IndexRegister, i8),
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Immediate(u8),
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum LoadTarget {
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DirectRegByte(Register),
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DirectRegHalfByte(IndexRegisterHalf),
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DirectRegWord(RegisterPair),
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IndirectRegByte(RegisterPair),
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IndirectRegWord(RegisterPair),
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IndirectOffsetByte(IndexRegister, i8),
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DirectAltRegByte(Register),
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IndirectByte(u16),
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IndirectWord(u16),
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ImmediateByte(u8),
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ImmediateWord(u16),
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}
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pub type UndocumentedCopy = Option<Target>;
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#[derive(Clone, Debug, PartialEq, Eq)]
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pub enum Instruction {
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ADCa(Target),
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ADC16(RegisterPair, RegisterPair),
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ADDa(Target),
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ADD16(RegisterPair, RegisterPair),
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AND(Target),
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BIT(u8, Target),
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CALL(u16),
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CALLcc(Condition, u16),
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CCF,
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CP(Target),
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CPD,
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CPDR,
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CPI,
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CPIR,
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CPL,
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DAA,
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DEC16(RegisterPair),
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DEC8(Target),
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DI,
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DJNZ(i8),
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EI,
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EXX,
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EXafaf,
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EXhlde,
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EXsp(RegisterPair),
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HALT,
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IM(InterruptMode),
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INC16(RegisterPair),
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INC8(Target),
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IND,
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INDR,
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INI,
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INIR,
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INic(Register),
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INicz,
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INx(u8),
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JP(u16),
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JPIndirect(RegisterPair),
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JPcc(Condition, u16),
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JR(i8),
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JRcc(Condition, i8),
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LD(LoadTarget, LoadTarget),
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LDsr(SpecialRegister, Direction),
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LDD,
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LDDR,
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LDI,
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LDIR,
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NEG,
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NOP,
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OR(Target),
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OTDR,
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OTIR,
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OUTD,
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OUTI,
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OUTic(Register),
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OUTicz,
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OUTx(u8),
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POP(RegisterPair),
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PUSH(RegisterPair),
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RES(u8, Target, UndocumentedCopy),
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RET,
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RETI,
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RETN,
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RETcc(Condition),
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RL(Target, UndocumentedCopy),
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RLA,
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RLC(Target, UndocumentedCopy),
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RLCA,
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RLD,
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RR(Target, UndocumentedCopy),
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RRA,
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RRC(Target, UndocumentedCopy),
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RRCA,
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RRD,
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RST(u8),
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SBCa(Target),
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SBC16(RegisterPair, RegisterPair),
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SCF,
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SET(u8, Target, UndocumentedCopy),
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SLA(Target, UndocumentedCopy),
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SLL(Target, UndocumentedCopy),
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SRA(Target, UndocumentedCopy),
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SRL(Target, UndocumentedCopy),
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SUB(Target),
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XOR(Target),
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}
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impl From<u8> for InterruptMode {
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fn from(im: u8) -> Self {
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match im {
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0 => InterruptMode::Mode0,
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1 => InterruptMode::Mode1,
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2 => InterruptMode::Mode2,
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_ => InterruptMode::Unknown(im),
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}
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}
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}
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impl RegisterPair {
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pub(crate) fn is_index_reg(&self) -> bool {
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matches!(self, RegisterPair::IX | RegisterPair::IY)
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}
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}
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