467 lines
15 KiB
Rust
467 lines
15 KiB
Rust
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const DEFAULT_RAD_TESTS: &str = "tests/jsmoo/misc/tests/GeneratedTests/z80/v1/";
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use std::rc::Rc;
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use std::cell::RefCell;
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use std::io::prelude::*;
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use std::fmt::{Debug, UpperHex};
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use std::path::PathBuf;
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use std::time::SystemTime;
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use std::fs::{self, File};
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use clap::Parser;
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use flate2::read::GzDecoder;
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use serde_derive::Deserialize;
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use moa_core::{System, Error, MemoryBlock, Bus, BusPort, Frequency, Address, Addressable, Steppable, Device};
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use moa_z80::{Z80, Z80Type};
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use moa_z80::instructions::InterruptMode;
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use moa_z80::state::Flags;
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use moa_z80::state::Status;
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#[derive(Parser)]
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struct Args {
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/// Filter the tests by gzip file name
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filter: Option<String>,
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/// Only run the one test with the given number
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#[clap(short, long)]
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only: Option<String>,
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/// Dump the CPU state when a test fails
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#[clap(short, long)]
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debug: bool,
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/// Only print a summary for each test file
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#[clap(short, long)]
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quiet: bool,
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/// Check the Half Carry, F3, and F5 flags for accuracy
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#[clap(short = 'f', long)]
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check_extra_flags: bool,
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/// Check undocumented instructions
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#[clap(short = 'u', long)]
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check_undocumented: bool,
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/// Check instruction timings
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#[clap(short = 't', long)]
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check_timings: bool,
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/// Directory to the test suite to run
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#[clap(long, default_value = DEFAULT_RAD_TESTS)]
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testsuite: String,
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}
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fn main() {
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let args = Args::parse();
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run_all_tests(&args);
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}
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#[derive(Debug, Deserialize)]
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struct TestState {
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pc: u16,
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sp: u16,
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a: u8,
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b: u8,
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c: u8,
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d: u8,
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e: u8,
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f: u8,
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h: u8,
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l: u8,
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i: u8,
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r: u8,
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//ei: u8,
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//wz: u8,
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ix: u16,
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iy: u16,
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af_: u16,
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bc_: u16,
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de_: u16,
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hl_: u16,
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im: u8,
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//p: u8,
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//q: u8,
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iff1: u8,
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iff2: u8,
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ram: Vec<(u16, u8)>,
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}
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#[derive(Debug, Deserialize)]
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struct TestCycle(u16, Option<u8>, String);
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#[derive(Debug, Deserialize)]
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struct TestPort {
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addr: u16,
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value: u8,
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atype: String,
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}
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#[derive(Debug, Deserialize)]
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struct TestCase {
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name: String,
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#[serde(rename(deserialize = "initial"))]
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initial_state: TestState,
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#[serde(rename(deserialize = "final"))]
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final_state: TestState,
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#[serde(default)]
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cycles: Vec<TestCycle>,
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#[serde(default)]
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ports: Vec<TestPort>,
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}
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impl TestState {
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pub fn dump(&self) {
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println!(" a: {:02x} a': {:02x}", self.a, self.af_ >> 8);
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println!(" b: {:02x} b': {:02x}", self.b, self.bc_ & 0xff);
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println!(" c: {:02x} c': {:02x}", self.c, self.bc_ >> 8);
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println!(" d: {:02x} d': {:02x}", self.d, self.de_ & 0xff);
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println!(" e: {:02x} e': {:02x}", self.e, self.de_ >> 8);
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println!(" f: {:02x} f': {:02x}", self.f, self.af_ & 0xff);
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println!(" h: {:02x} h': {:02x}", self.h, self.hl_ >> 8);
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println!(" l: {:02x} l': {:02x}", self.l, self.hl_ & 0xff);
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println!("pc: {:04x} sp: {:04x}", self.pc, self.sp);
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println!("ix: {:04x} iy: {:04x}", self.ix, self.iy);
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println!(" i: {:02x} r: {:02x}", self.i, self.r);
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println!("im: {:02x} iff1: {:02x} iff2: {:02x}", self.im, self.iff1, self.iff2);
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println!("ram: ");
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for (addr, byte) in self.ram.iter() {
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println!("{:04x} {:02x} ", *addr, *byte);
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}
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}
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}
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impl TestCase {
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pub fn dump(&self) {
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println!("{}", self.name);
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println!("initial:");
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self.initial_state.dump();
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println!("final:");
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self.final_state.dump();
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println!("ports: ");
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for port in self.ports.iter() {
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println!("{:04x} {:02x} {}", port.addr, port.value, port.atype);
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}
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}
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}
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fn init_execute_test(cputype: Z80Type, state: &TestState, ports: &[TestPort]) -> Result<(Z80, System, Rc<RefCell<Bus>>), Error> {
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let mut system = System::default();
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// Insert basic initialization
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let mem = MemoryBlock::new(vec![0; 0x1_0000]);
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system.add_addressable_device(0x00000000, Device::new(mem)).unwrap();
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// Set up IOREQ as memory space
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let io_ram = Device::new(MemoryBlock::new(vec![0; 0x10000]));
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let io_bus = Rc::new(RefCell::new(Bus::default()));
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io_bus.borrow_mut().set_ignore_unmapped(true);
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io_bus.borrow_mut().insert(0x0000, io_ram.clone());
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let port = BusPort::new(0, 16, 8, system.bus.clone());
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let ioport = BusPort::new(0, 16, 8, io_bus.clone());
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let mut cpu = Z80::new(cputype, Frequency::from_mhz(10), port, Some(ioport));
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cpu.state.status = Status::Running;
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load_state(&mut cpu, &mut system, io_bus.clone(), state, ports)?;
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Ok((cpu, system, io_bus))
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}
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fn assert_value<T>(actual: T, expected: T, message: &str) -> Result<(), Error>
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where
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T: PartialEq + Debug + UpperHex
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{
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if actual == expected {
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Ok(())
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} else {
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Err(Error::assertion(&format!("{:#X} != {:#X}, {}", actual, expected, message)))
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}
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}
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fn load_state(cpu: &mut Z80, system: &mut System, io_bus: Rc<RefCell<Bus>>, initial: &TestState, ports: &[TestPort]) -> Result<(), Error> {
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cpu.state.reg[0] = initial.b;
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cpu.state.reg[1] = initial.c;
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cpu.state.reg[2] = initial.d;
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cpu.state.reg[3] = initial.e;
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cpu.state.reg[4] = initial.h;
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cpu.state.reg[5] = initial.l;
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cpu.state.reg[6] = initial.a;
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cpu.state.reg[7] = initial.f;
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cpu.state.shadow_reg[0] = (initial.bc_ >> 8) as u8;
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cpu.state.shadow_reg[1] = (initial.bc_ & 0xff) as u8;
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cpu.state.shadow_reg[2] = (initial.de_ >> 8) as u8;
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cpu.state.shadow_reg[3] = (initial.de_ & 0xff) as u8;
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cpu.state.shadow_reg[4] = (initial.hl_ >> 8) as u8;
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cpu.state.shadow_reg[5] = (initial.hl_ & 0xff) as u8;
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cpu.state.shadow_reg[6] = (initial.af_ >> 8) as u8;
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cpu.state.shadow_reg[7] = (initial.af_ & 0xff) as u8;
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cpu.state.ix = initial.ix;
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cpu.state.iy = initial.iy;
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cpu.state.sp = initial.sp;
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cpu.state.pc = initial.pc;
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cpu.state.i = initial.i;
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cpu.state.r = initial.r;
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cpu.state.im = initial.im.into();
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cpu.state.iff1 = initial.iff1 != 0;
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cpu.state.iff2 = initial.iff2 != 0;
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// Load data bytes into memory
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for (addr, byte) in initial.ram.iter() {
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system.get_bus().write_u8(system.clock, *addr as u64, *byte)?;
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}
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// Load data bytes into io space
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for port in ports.iter() {
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io_bus.borrow_mut().write_u8(system.clock, port.addr as u64, port.value)?;
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}
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Ok(())
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}
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const IGNORE_FLAG_MASK: u8 = Flags::F3 as u8 | Flags::F5 as u8;
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fn assert_state(cpu: &Z80, system: &System, io_bus: Rc<RefCell<Bus>>, expected: &TestState, check_extra_flags: bool, ports: &[TestPort]) -> Result<(), Error> {
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assert_value(cpu.state.reg[0], expected.b, "b")?;
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assert_value(cpu.state.reg[1], expected.c, "c")?;
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assert_value(cpu.state.reg[2], expected.d, "d")?;
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assert_value(cpu.state.reg[3], expected.e, "e")?;
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assert_value(cpu.state.reg[4], expected.h, "h")?;
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assert_value(cpu.state.reg[5], expected.l, "l")?;
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assert_value(cpu.state.reg[6], expected.a, "a")?;
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if check_extra_flags {
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assert_value(cpu.state.reg[7], expected.f, "f")?;
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} else {
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assert_value(cpu.state.reg[7] & !IGNORE_FLAG_MASK, expected.f & !IGNORE_FLAG_MASK, "f")?;
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}
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assert_value(cpu.state.shadow_reg[0], (expected.bc_ >> 8) as u8, "b'")?;
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assert_value(cpu.state.shadow_reg[1], (expected.bc_ & 0xff) as u8, "c'")?;
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assert_value(cpu.state.shadow_reg[2], (expected.de_ >> 8) as u8, "d'")?;
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assert_value(cpu.state.shadow_reg[3], (expected.de_ & 0xff) as u8, "e'")?;
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assert_value(cpu.state.shadow_reg[4], (expected.hl_ >> 8) as u8, "h'")?;
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assert_value(cpu.state.shadow_reg[5], (expected.hl_ & 0xff) as u8, "l'")?;
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assert_value(cpu.state.shadow_reg[6], (expected.af_ >> 8) as u8, "a'")?;
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assert_value(cpu.state.shadow_reg[7], (expected.af_ & 0xff) as u8, "f'")?;
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assert_value(cpu.state.ix, expected.ix, "ix")?;
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assert_value(cpu.state.iy, expected.iy, "iy")?;
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assert_value(cpu.state.sp, expected.sp, "sp")?;
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assert_value(cpu.state.pc, expected.pc, "pc")?;
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assert_value(cpu.state.i, expected.i, "i")?;
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// TODO this isn't emulated yet, so it will cause all the tests to fail
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//assert_value(cpu.state.r, expected.r, "r")?;
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let expected_im: InterruptMode = expected.im.into();
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if cpu.state.im != expected_im {
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return Err(Error::assertion(&format!("{:?} != {:?}, im", cpu.state.im, expected_im)));
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}
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assert_value(cpu.state.iff1 as u8, expected.iff1, "iff1")?;
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assert_value(cpu.state.iff2 as u8, expected.iff2, "iff2")?;
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let addr_mask = cpu.port.address_mask();
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// Load data bytes into memory
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for (addr, byte) in expected.ram.iter() {
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let actual = system.get_bus().read_u8(system.clock, *addr as Address & addr_mask)?;
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assert_value(actual, *byte, &format!("ram at {:x}", addr))?;
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}
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// Load data bytes into io space
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for port in ports.iter() {
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if port.atype == "w" {
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let actual = io_bus.borrow_mut().read_u8(system.clock, port.addr as u64)?;
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assert_value(actual, port.value, &format!("port value at {:x}", port.addr))?;
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}
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}
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Ok(())
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}
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fn step_cpu_and_assert(cpu: &mut Z80, system: &System, io_bus: Rc<RefCell<Bus>>, case: &TestCase, args: &Args) -> Result<(), Error> {
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let clock_elapsed = cpu.step(&system)?;
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assert_state(&cpu, &system, io_bus, &case.final_state, args.check_extra_flags, &case.ports)?;
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if args.check_timings {
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let cycles = clock_elapsed / cpu.frequency.period_duration();
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if cycles != case.cycles.len() as Address {
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return Err(Error::assertion(&format!("expected instruction to take {} cycles, but took {}", case.cycles.len(), cycles)));
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}
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}
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Ok(())
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}
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fn run_test(case: &TestCase, args: &Args) -> Result<(), Error> {
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let (mut cpu, system, io_bus) = init_execute_test(Z80Type::Z80, &case.initial_state, &case.ports).unwrap();
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let mut initial_cpu = cpu.clone();
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let result = step_cpu_and_assert(&mut cpu, &system, io_bus, case, args);
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match result {
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Ok(()) => Ok(()),
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Err(err) => {
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if !args.quiet {
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if args.debug {
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case.dump();
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println!("");
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initial_cpu.dump_state(system.clock);
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cpu.dump_state(system.clock);
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}
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println!("FAILED: {:?}", err);
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}
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Err(err)
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},
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}
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}
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fn test_json_file(path: PathBuf, args: &Args) -> (usize, usize, String) {
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let extension = path.extension().unwrap();
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let cases: Vec<TestCase> = if extension == "gz" {
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let file = File::open(&path).unwrap();
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let mut decoder = GzDecoder::new(file);
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let mut data = String::new();
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decoder.read_to_string(&mut data).unwrap();
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serde_json::from_str(&data).unwrap()
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} else {
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let data = fs::read(&path).unwrap();
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serde_json::from_slice(&data).unwrap()
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};
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let mut passed = 0;
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let mut failed = 0;
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for mut case in cases {
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if let Some(only) = args.only.as_ref() {
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if !case.name.ends_with(only) {
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continue;
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}
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}
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// Sort the ram memory for debugging help
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if args.debug {
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case.initial_state.ram.sort_by_key(|(addr, _)| *addr);
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case.final_state.ram.sort_by_key(|(addr, _)| *addr);
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}
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if !args.quiet {
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println!("Running test {}", case.name);
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}
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let result = run_test(&case, args);
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if let Err(err) = result {
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failed += 1;
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if !args.quiet {
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println!("FAILED: {:?}", err);
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}
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} else {
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passed += 1
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}
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}
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let name = path.file_name().unwrap().to_str().unwrap();
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let message = if failed == 0 {
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format!("{} completed, all passed!", name)
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} else {
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format!("{} completed: {} passed, {} FAILED", name, passed, failed)
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};
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(passed, failed, message)
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}
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fn run_all_tests(args: &Args) {
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let mut passed = 0;
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let mut failed = 0;
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let mut messages = vec![];
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let mut tests: Vec<PathBuf> = fs::read_dir(&args.testsuite)
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.unwrap()
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.map(|dirent| dirent.unwrap().path())
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.collect();
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tests.sort();
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let start = SystemTime::now();
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for path in tests {
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// Only test gzip files (the repo has .md files as well)
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let extension = path.extension().unwrap();
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if extension != "json" && extension != "gz" {
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continue;
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}
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let name = path.file_name().unwrap().to_str().unwrap();
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// If specified, only test files that start with a given string
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if let Some(filter) = &args.filter {
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if !name.starts_with(filter) {
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continue;
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}
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}
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if !args.check_undocumented && is_undocumented_instruction(name) {
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continue;
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}
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// Run every test in the file
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let (test_passed, test_failed, message) = test_json_file(path, args);
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// In quiet mode, print each summary as it's received to give a progress update
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if args.quiet {
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println!("{}", message);
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}
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passed += test_passed;
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failed += test_failed;
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messages.push(message);
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}
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let elapsed_secs = start.elapsed().unwrap().as_secs();
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// Print the stored summary if not in quite mode
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if !args.quiet {
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for message in messages {
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println!("{}", message);
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}
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}
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println!("");
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println!("passed: {}, failed: {}, total {:.0}%", passed, failed, ((passed as f32) / (passed as f32 + failed as f32)) * 100.0);
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println!("completed in {}m {}s", elapsed_secs / 60, elapsed_secs % 60);
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}
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fn is_undocumented_instruction(name: &str) -> bool {
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let mut opcodes: Vec<u8> = name
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.splitn(3, &[' ', '.'])
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.filter_map(|s| u8::from_str_radix(s, 16).ok())
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.collect();
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opcodes.extend(vec![0; 3 - opcodes.len()]);
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match (opcodes[0], opcodes[1]) {
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(0xCB, op) => {
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op >= 0x30 && op <= 0x37
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},
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(0xDD, 0xCB) |
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(0xFD, 0xCB) => {
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!(opcodes[2] & 0x07 == 0x06 && opcodes[2] != 0x36)
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},
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(0xDD, op) |
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(0xFD, op) => {
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let upper = op & 0xF0;
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let lower = op & 0x0F;
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!(lower == 0x06 && upper >= 0x30 && upper <= 0xB0 && upper != 0x70) &&
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!(lower == 0x0E && upper >= 0x40 && upper <= 0xB0) &&
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!(op >= 0x70 && op <= 0x77 && op != 0x76) &&
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!(op >= 0x21 && op <= 0x23 && op >= 0x34 && op <= 0x36 && op >= 0x29 && op <= 0x2B) &&
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!(lower == 0x09 && upper <= 0x30) &&
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!(op == 0xE1 || op == 0xE3 || op == 0xE5 || op == 0xE9 || op == 0xF9)
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},
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(0xED, op) => {
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// NOTE this assumes the tests don't have the missing instructions, or the Z180 instructions
|
|
// so it only checks for the undocumented ones
|
|
op == 0x63 || op == 0x6B || op == 0x70 || op == 0x71
|
|
},
|
|
_ => false
|
|
}
|
|
}
|
|
|