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31 lines
1.4 KiB
Plaintext
31 lines
1.4 KiB
Plaintext
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* each device that can make a bus request should have a BusPort which is used to access the bus. Not sure how it'll be created or passed to the device, since
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the offset should be set by the builder or system, and the mask and data size should be sent by the CPU (although I suppose some systems could hook it up differently)
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* what about even vs odd accesses? If you access a byte, should the bus port possible turn it into a word access, and return only the byte portion?
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this would be more accurate for the 68000 which doesn't have an A0 address pin
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* there is clearly an issue with the ROM writing 4 bytes to the data port when the autoincrement is only 2. This might be an issue with the fact that the CPU
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is making full long word requests even though the 68000 shouldn't be able to (a long word would be 2 word accesses)
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* make devices nameable, using a hashmap to store them
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* can you eventually make the system connections all configurable via a config file?
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* make tests for each instruction
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* unimplemented: ABCD, ADDX, BFFFO, BFINS, BKPT, CHK, EXG, ILLEGAL, MOVEfromCCR, MOVEP, RTR, RTD, SBCD, SUBX
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* >=MC68020 undecoded & unimplemented: CALLM, CAS, CAS2, CHK2, CMP2, RTM, PACK, TRAPcc, UNPK
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* add support for MMU
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* add support for FPU
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* Coprocessor instructions: cpBcc, cpDBcc, cpGEN, cpScc, cpTRAPcc
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* how can you have multple CPUs
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* should you simulate bus arbitration?
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* check all instructions in the docs
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