mirror of
https://github.com/transistorfet/moa.git
synced 2024-09-27 01:54:50 +00:00
400 lines
13 KiB
Rust
400 lines
13 KiB
Rust
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use std::num::NonZeroU8;
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use std::collections::VecDeque;
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use moa_core::{debug, warn};
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use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable};
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use moa_core::host::{Host, Audio};
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use moa_core::host::audio::{SineWave};
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const DEV_NAME: &'static str = "ym2612";
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const CHANNELS: usize = 8;
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#[derive(Copy, Clone, Debug)]
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pub enum OperatorAlgorithm {
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A0,
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A1,
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A2,
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A3,
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A4,
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A5,
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A6,
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A7,
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}
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#[derive(Clone)]
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pub struct Operator {
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pub wave: SineWave,
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pub frequency: f32,
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pub multiplier: f32,
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}
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impl Operator {
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pub fn new(sample_rate: usize) -> Self {
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Self {
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wave: SineWave::new(400.0, sample_rate),
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frequency: 400.0,
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multiplier: 1.0,
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}
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}
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pub fn set_frequency(&mut self, frequency: f32) {
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self.frequency = frequency;
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}
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pub fn reset(&mut self) {
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self.wave.reset();
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}
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pub fn set_multiplier(&mut self, _frequency: f32, multiplier: f32) {
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self.multiplier = multiplier;
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}
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pub fn get_sample(&mut self, modulator: f32) -> f32 {
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// TODO this would need to take into account the volume and envelope
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self.wave.set_frequency((self.frequency * self.multiplier) + modulator);
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self.wave.next().unwrap()
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}
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}
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#[derive(Clone)]
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pub struct Channel {
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pub operators: Vec<Operator>,
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pub on: u8,
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pub base_frequency: f32,
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pub algorithm: OperatorAlgorithm,
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}
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impl Channel {
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pub fn new(sample_rate: usize) -> Self {
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Self {
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operators: vec![Operator::new(sample_rate); 4],
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on: 0,
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base_frequency: 0.0,
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algorithm: OperatorAlgorithm::A0,
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}
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}
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pub fn set_frequency(&mut self, frequency: f32) {
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self.base_frequency = frequency;
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for operator in self.operators.iter_mut() {
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operator.set_frequency(frequency);
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}
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}
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pub fn reset(&mut self) {
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for operator in self.operators.iter_mut() {
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operator.reset();
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}
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}
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pub fn get_sample(&mut self) -> f32 {
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match self.algorithm {
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OperatorAlgorithm::A0 => {
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let modulator0 = self.operators[0].get_sample(0.0);
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let modulator1 = self.operators[1].get_sample(modulator0);
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let modulator2 = self.operators[2].get_sample(modulator1);
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self.operators[3].get_sample(modulator2)
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},
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OperatorAlgorithm::A1 => {
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let sample1 = self.operators[0].get_sample(0.0) + self.operators[1].get_sample(0.0);
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let sample2 = self.operators[2].get_sample(sample1);
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let sample3 = self.operators[3].get_sample(sample2);
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sample3
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},
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OperatorAlgorithm::A2 => {
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let sample1 = self.operators[1].get_sample(0.0);
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let sample2 = self.operators[2].get_sample(sample1);
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let sample3 = self.operators[0].get_sample(0.0) + sample2;
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let sample4 = self.operators[3].get_sample(sample3);
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sample4
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},
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OperatorAlgorithm::A3 => {
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let sample1 = self.operators[0].get_sample(0.0);
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let sample2 = self.operators[1].get_sample(sample1);
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let sample3 = self.operators[2].get_sample(0.0);
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let sample4 = self.operators[3].get_sample(sample2 + sample3);
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sample4
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},
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OperatorAlgorithm::A4 => {
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let sample1 = self.operators[0].get_sample(0.0);
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let sample2 = self.operators[1].get_sample(sample1);
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let sample3 = self.operators[2].get_sample(0.0);
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let sample4 = self.operators[3].get_sample(sample3);
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sample2 + sample4
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},
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OperatorAlgorithm::A5 => {
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let sample1 = self.operators[0].get_sample(0.0);
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let sample2 = self.operators[1].get_sample(sample1) + self.operators[2].get_sample(sample1) + self.operators[3].get_sample(sample1);
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sample2
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},
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OperatorAlgorithm::A6 => {
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let sample1 = self.operators[0].get_sample(0.0);
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let sample2 = self.operators[1].get_sample(sample1);
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sample2 + self.operators[2].get_sample(0.0) + self.operators[3].get_sample(0.0)
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},
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OperatorAlgorithm::A7 => {
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let sample = self.operators[0].get_sample(0.0)
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+ self.operators[1].get_sample(0.0)
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+ self.operators[2].get_sample(0.0)
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+ self.operators[3].get_sample(0.0);
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sample
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},
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}
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}
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}
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pub struct Ym2612 {
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pub source: Box<dyn Audio>,
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pub selected_reg_0: Option<NonZeroU8>,
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pub selected_reg_1: Option<NonZeroU8>,
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pub channels: Vec<Channel>,
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pub channel_frequencies: [(u8, u16); CHANNELS],
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pub dac_enabled: bool,
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pub dac: VecDeque<u8>,
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pub timer_a_enable: bool,
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pub timer_a: u16,
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pub timer_a_current: u16,
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pub timer_a_overflow: bool,
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pub timer_b_enable: bool,
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pub timer_b: u8,
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pub timer_b_current: u8,
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pub timer_b_overflow: bool,
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}
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impl Ym2612 {
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pub fn create<H: Host>(host: &mut H) -> Result<Self, Error> {
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let source = host.create_audio_source()?;
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let sample_rate = source.samples_per_second();
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Ok(Self {
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source,
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selected_reg_0: None,
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selected_reg_1: None,
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channels: vec![Channel::new(sample_rate); 8],
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channel_frequencies: [(0, 0); CHANNELS],
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dac_enabled: false,
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dac: VecDeque::with_capacity(100),
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timer_a_enable: false,
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timer_a: 0,
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timer_a_current: 0,
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timer_a_overflow: false,
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timer_b_enable: false,
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timer_b: 0,
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timer_b_current: 0,
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timer_b_overflow: false,
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})
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}
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pub fn set_register(&mut self, bank: usize, reg: usize, data: u8) {
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warn!("{}: set reg {}{:x} to {:x}", DEV_NAME, bank, reg, data);
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match reg {
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0x24 => {
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self.timer_a = (self.timer_a & 0x3) | ((data as u16) << 2);
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},
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0x25 => {
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self.timer_a = (self.timer_a & 0xFFFC) | ((data as u16) & 0x03);
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},
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0x26 => {
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self.timer_b = data;
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},
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0x27 => {
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//if (data >> 5) & 0x1 {
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// self.timer_b
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},
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0x28 => {
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let ch = (data as usize) & 0x07;
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self.channels[ch].on = data >> 4;
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self.channels[ch].reset();
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println!("Note: {}: {:x}", ch, self.channels[ch].on);
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},
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0x2a => {
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if self.dac_enabled {
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for _ in 0..3 {
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self.dac.push_back(data);
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}
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}
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},
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0x2b => {
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self.dac_enabled = data & 0x80 != 0;
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},
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reg if (reg & 0xF0) == 0x30 => {
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let (ch, op) = get_ch_op(bank, reg);
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let multiplier = if data == 0 { 0.5 } else { (data & 0x0F) as f32 };
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let frequency = self.channels[ch].base_frequency;
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debug!("{}: channel {} operator {} set to multiplier {}", DEV_NAME, ch + 1, op + 1, multiplier);
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self.channels[ch].operators[op].set_multiplier(frequency, multiplier)
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},
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reg if reg >= 0xA0 && reg <= 0xA2 => {
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let ch = (reg & 0x07) + (bank * 3);
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self.channel_frequencies[ch].1 = (self.channel_frequencies[ch].1 & 0xFF00) | data as u16;
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let frequency = fnumber_to_frequency(self.channel_frequencies[ch]);
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debug!("{}: channel {} set to frequency {}", DEV_NAME, ch + 1, frequency);
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self.channels[ch].set_frequency(frequency);
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},
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reg if reg >= 0xA4 && reg <= 0xA6 => {
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let ch = (reg & 0x07) - 4 + (bank * 3);
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self.channel_frequencies[ch].1 = (self.channel_frequencies[ch].1 & 0xFF) | ((data as u16) & 0x07) << 8;
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self.channel_frequencies[ch].0 = (data & 0x38) >> 3;
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},
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reg if reg >= 0xB0 && reg <= 0xB2 => {
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let ch = (reg & 0x07) + (bank * 3);
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self.channels[ch].algorithm = match data & 0x07 {
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0 => OperatorAlgorithm::A0,
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1 => OperatorAlgorithm::A1,
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2 => OperatorAlgorithm::A2,
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3 => OperatorAlgorithm::A3,
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4 => OperatorAlgorithm::A4,
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5 => OperatorAlgorithm::A5,
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6 => OperatorAlgorithm::A6,
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7 => OperatorAlgorithm::A7,
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_ => OperatorAlgorithm::A0,
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};
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},
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_ => {
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warn!("{}: !!! unhandled write to register {:0x} with {:0x}", DEV_NAME, reg, data);
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},
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}
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}
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}
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#[inline(always)]
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pub fn fnumber_to_frequency(fnumber: (u8, u16)) -> f32 {
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(fnumber.1 as f32 * 0.0264) * (2 as u32).pow(fnumber.0 as u32) as f32
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}
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#[inline(always)]
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pub fn get_ch_op(bank: usize, reg: usize) -> (usize, usize) {
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let ch = (reg & 0x03) + (bank * 3);
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let op = (reg & 0xC0) >> 2;
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(ch, op)
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}
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impl Steppable for Ym2612 {
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fn step(&mut self, system: &System) -> Result<ClockElapsed, Error> {
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// TODO since you expect this step function to be called every 1ms of simulated time
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// you could assume that you should produce (sample_rate / 1000) samples
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//if self.sine.frequency < 2000.0 {
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// self.sine.frequency += 1.0;
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//}
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//let rate = self.source.samples_per_second();
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//self.source.write_samples(rate / 1000, &mut self.sine);
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//println!("{}", self.sine.frequency);
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//if self.on {
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// let rate = self.source.samples_per_second();
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// self.source.write_samples(rate / 1000, &mut self.sine);
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//}
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let rate = self.source.samples_per_second();
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let available = self.source.space_available();
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let samples = if available < rate / 1000 { available } else { rate / 1000 };
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//if self.source.space_available() >= samples {
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let mut buffer = vec![0.0; samples];
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for i in 0..samples {
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let mut sample = 0.0;
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for ch in 0..6 {
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if self.channels[ch].on != 0 {
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sample += self.channels[ch].get_sample();
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}
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}
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if self.dac_enabled {
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if let Some(data) = self.dac.pop_front() {
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sample += ((data as f32 - 128.0) / 255.0) * 2.0;
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}
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} else if self.channels[6].on != 0 {
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sample += self.channels[6].get_sample();
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}
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buffer[i] = sample.clamp(-1.0, 1.0);
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}
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//println!("synthesized: {:?}", buffer);
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self.source.write_samples(system.clock, &buffer);
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//}
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Ok(1_000_000) // Every 1ms of simulated time
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}
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}
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impl Addressable for Ym2612 {
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fn len(&self) -> usize {
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0x04
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}
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fn read(&mut self, addr: Address, data: &mut [u8]) -> Result<(), Error> {
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match addr {
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0 | 1 | 2 | 3 => {
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// Read the status byte (busy/overflow)
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data[0] = 0 | ((self.timer_a_overflow as u8) << 1) | (self.timer_b_overflow as u8);
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}
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_ => {
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warn!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
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},
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}
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debug!("{}: read from register {:x} of {:?}", DEV_NAME, addr, data);
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Ok(())
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}
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fn write(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
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debug!("{}: write to register {:x} with {:x}", DEV_NAME, addr, data[0]);
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match addr {
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0 => {
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self.selected_reg_0 = NonZeroU8::new(data[0]);
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},
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1 => {
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if let Some(reg) = self.selected_reg_0 {
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self.set_register(0, reg.get() as usize, data[0]);
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}
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},
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2 => {
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self.selected_reg_1 = NonZeroU8::new(data[0]);
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},
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3 => {
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if let Some(reg) = self.selected_reg_1 {
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self.set_register(1, reg.get() as usize, data[0]);
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}
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},
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_ => {
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warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
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},
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}
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Ok(())
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}
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}
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impl Transmutable for Ym2612 {
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fn as_addressable(&mut self) -> Option<&mut dyn Addressable> {
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Some(self)
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}
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fn as_steppable(&mut self) -> Option<&mut dyn Steppable> {
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Some(self)
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}
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}
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