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93c080eae6
Previously the m68k wasn't masking interrupts with an equal priorty. I also modified how they work, such that the cpus will check the controller rather than wait for the notification call
40 lines
1.6 KiB
Plaintext
40 lines
1.6 KiB
Plaintext
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* i need a better way of handling disperate reads/writes to I/O spaces, rather than having multiple devices or having a massive chunk of address space allocated, continuously
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* should you modify Addressable to also take the absolute address as input? I'm thinking of how the same device could be mapped to multiple addresses in memory instead
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of taking up a whole range of addresses
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* implement a Z80
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* maybe see about a Mac 128k or something
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* add instruction timing to M68k
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* YM7101 timing is causing it to be very slow... speeding this up increasing rendering speed a lot, even though the frame shouldn't be drawn that often... not sure what's wrong with the timing
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* make the ym7101 set/reset the v_int occurred flag based on the interrupt controller
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* each device that can make a bus request should have a BusPort which is used to access the bus
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* separate the debugger out of m68k
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* make devices nameable, using a hashmap to store them
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* you could modify read()/write() in Addressable to return the number of bytes read or written for dynamic bus sizing used by the MC68020+
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* should you simulate bus arbitration?
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* make tests for each instruction
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* check all instructions in the docs
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* unimplemented: ABCD, ADDX, BFFFO, BFINS, BKPT, CHK, EXG, ILLEGAL, MOVEfromCCR, MOVEP, RTR, RTD, SBCD, SUBX
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* >=MC68020 undecoded & unimplemented: CALLM, CAS, CAS2, CHK2, CMP2, RTM, PACK, TRAPcc, UNPK
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* add support for MMU
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* add support for FPU
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* Coprocessor instructions: cpBcc, cpDBcc, cpGEN, cpScc, cpTRAPcc
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* how can you have multple CPUs
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* can you eventually make the system connections all configurable via a config file?
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