mirror of
https://github.com/transistorfet/moa.git
synced 2024-05-29 04:41:29 +00:00
883 lines
36 KiB
Rust
883 lines
36 KiB
Rust
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use std::fmt;
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use crate::error::Error;
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use crate::system::System;
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use crate::memory::Address;
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use crate::devices::AddressableDeviceRefMut;
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use super::state::{M68kType, ERR_ILLEGAL_INSTRUCTION};
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const OPCG_BIT_OPS: u8 = 0x0;
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const OPCG_MOVE_BYTE: u8 = 0x1;
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const OPCG_MOVE_LONG: u8 = 0x2;
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const OPCG_MOVE_WORD: u8 = 0x3;
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const OPCG_MISC: u8 = 0x04;
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const OPCG_ADDQ_SUBQ: u8 = 0x5;
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const OPCG_BRANCH: u8 = 0x6;
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const OPCG_MOVEQ: u8 = 0x7;
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const OPCG_DIV_OR: u8 = 0x8;
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const OPCG_SUB: u8 = 0x9;
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const OPCG_RESERVED1: u8 = 0xA;
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const OPCG_CMP_EOR: u8 = 0xB;
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const OPCG_MUL_AND: u8 = 0xC;
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const OPCG_ADD: u8 = 0xD;
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const OPCG_SHIFT: u8 = 0xE;
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const OPCG_RESERVED2: u8 = 0xF;
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Sign {
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Signed,
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Unsigned,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Direction {
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FromTarget,
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ToTarget,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum ShiftDirection {
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Right,
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Left,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum RegisterType {
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Data,
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Address,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum ControlRegister {
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VBR,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Size {
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Byte,
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Word,
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Long,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Condition {
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True,
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False,
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High,
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LowOrSame,
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CarryClear,
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CarrySet,
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NotEqual,
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Equal,
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OverflowClear,
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OverflowSet,
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Plus,
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Minus,
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GreaterThanOrEqual,
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LessThan,
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GreaterThan,
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LessThanOrEqual,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Target {
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Immediate(u32),
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DirectDReg(u8),
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DirectAReg(u8),
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IndirectAReg(u8),
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IndirectARegInc(u8),
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IndirectARegDec(u8),
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IndirectARegOffset(u8, i32),
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IndirectARegXRegOffset(u8, RegisterType, u8, i32, Size),
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IndirectMemory(u32),
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IndirectPCOffset(i32),
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IndirectPCXRegOffset(RegisterType, u8, i32, Size),
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}
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#[derive(Clone, Debug, PartialEq)]
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pub enum Instruction {
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//ABCD
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ADD(Target, Target, Size),
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AND(Target, Target, Size),
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ANDtoCCR(u8),
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ANDtoSR(u16),
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ASd(Target, Target, Size, ShiftDirection),
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Bcc(Condition, i32),
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BRA(i32),
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BSR(i32),
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BCHG(Target, Target, Size),
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BCLR(Target, Target, Size),
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BSET(Target, Target, Size),
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BTST(Target, Target, Size),
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BKPT(u8),
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CHK(Target, u8, Size),
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CLR(Target, Size),
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CMP(Target, Target, Size),
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CMPA(Target, u8, Size),
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DBcc(Condition, u8, i16),
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DIV(Target, Target, Size, Sign),
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EOR(Target, Target, Size),
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EORtoCCR(u8),
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EORtoSR(u16),
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EXG(Target, Target),
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EXT(u8, Size),
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ILLEGAL,
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JMP(Target),
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JSR(Target),
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LEA(Target, u8),
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LINK(u8, i16),
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LSd(Target, Target, Size, ShiftDirection),
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MOVE(Target, Target, Size),
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MOVEA(Target, u8, Size),
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MOVEfromSR(Target),
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MOVEtoSR(Target),
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MOVEfromCCR(Target),
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MOVEtoCCR(Target),
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MOVEC(Target, ControlRegister, Direction),
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MOVEM(Target, Size, Direction, u16),
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MOVEP(u8, Target, Size, Direction),
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MOVEQ(u8, u8),
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MOVEUSP(Target, Direction),
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MUL(Target, Target, Size, Sign),
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NBCD(Target),
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NEG(Target, Size),
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NEGX(Target, Size),
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NOP,
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NOT(Target, Size),
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OR(Target, Target, Size),
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ORtoCCR(u8),
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ORtoSR(u16),
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PEA(Target),
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RESET,
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ROd(Target, Target, Size, ShiftDirection),
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ROXd(Target, Target, Size, ShiftDirection),
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RTE,
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RTR,
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RTS,
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RTD(i16),
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//SBCD
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Scc(Condition, Target),
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STOP(u16),
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SUB(Target, Target, Size),
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SWAP(u8),
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TAS(Target),
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TST(Target, Size),
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TRAP(u8),
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TRAPV,
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UNLK(u8),
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}
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pub struct M68kDecoder {
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pub cputype: M68kType,
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pub base: u32,
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pub start: u32,
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pub end: u32,
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pub instruction: Instruction,
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}
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impl M68kDecoder {
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pub fn new(cputype: M68kType, base: u32, start: u32) -> M68kDecoder {
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M68kDecoder {
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cputype,
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base: base,
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start: start,
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end: start,
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instruction: Instruction::NOP,
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}
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}
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#[inline(always)]
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pub fn init(&mut self, base: u32, start: u32) {
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self.base = base;
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self.start = start;
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self.end = start;
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}
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pub fn decode_at(&mut self, system: &System, start: u32) -> Result<(), Error> {
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let (memory, relative_addr) = system.get_bus().get_device_at(start as Address, 12)?;
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self.init(start - relative_addr as u32, start);
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self.instruction = self.decode_one(&mut memory.borrow_mut())?;
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Ok(())
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}
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pub fn decode_one(&mut self, system: &mut AddressableDeviceRefMut<'_>) -> Result<Instruction, Error> {
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let ins = self.read_instruction_word(system)?;
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match ((ins & 0xF000) >> 12) as u8 {
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OPCG_BIT_OPS => {
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let optype = (ins & 0x0F00) >> 8;
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if (ins & 0x3F) == 0b111100 {
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match (ins & 0x00C0) >> 6 {
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0b00 => {
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let data = self.read_instruction_word(system)?;
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match optype {
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0b0000 => Ok(Instruction::ORtoCCR(data as u8)),
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0b0001 => Ok(Instruction::ANDtoCCR(data as u8)),
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0b1010 => Ok(Instruction::EORtoCCR(data as u8)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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},
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0b01 => {
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let data = self.read_instruction_word(system)?;
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match optype {
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0b0000 => Ok(Instruction::ORtoSR(data)),
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0b0010 => Ok(Instruction::ANDtoSR(data)),
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0b1010 => Ok(Instruction::EORtoSR(data)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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} else if (ins & 0x138) == 0x108 {
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let dreg = get_high_reg(ins);
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let areg = get_low_reg(ins);
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let dir = if (ins & 0x0800) == 0 { Direction::FromTarget } else { Direction::ToTarget };
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let size = if (ins & 0x0040) == 0 { Size::Word } else { Size::Long };
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let offset = sign_extend_to_long(self.read_instruction_word(system)? as u32, Size::Word);
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Ok(Instruction::MOVEP(dreg, Target::IndirectARegOffset(areg, offset), size, dir))
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} else if (ins & 0x0100) == 0x0100 || (ins & 0x0F00) == 0x0800 {
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let bitnum = if (ins & 0x0100) == 0x0100 {
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Target::DirectDReg(get_high_reg(ins))
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} else {
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Target::Immediate(self.read_instruction_word(system)? as u32)
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};
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let target = self.decode_lower_effective_address(system, ins, Some(Size::Byte))?;
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let size = match target {
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Target::DirectAReg(_) | Target::DirectDReg(_) => Size::Long,
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_ => Size::Byte,
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};
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match (ins & 0x00C0) >> 6 {
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0b00 => Ok(Instruction::BTST(bitnum, target, size)),
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0b01 => Ok(Instruction::BCHG(bitnum, target, size)),
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0b10 => Ok(Instruction::BCLR(bitnum, target, size)),
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0b11 => Ok(Instruction::BSET(bitnum, target, size)),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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} else {
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let size = get_size(ins);
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let data = match size {
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Some(Size::Byte) => (self.read_instruction_word(system)? as u32 & 0xFF),
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Some(Size::Word) => self.read_instruction_word(system)? as u32,
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Some(Size::Long) => self.read_instruction_long(system)?,
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None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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};
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let target = self.decode_lower_effective_address(system, ins, size)?;
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match optype {
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0b0000 => Ok(Instruction::OR(Target::Immediate(data), target, size.unwrap())),
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0b0010 => Ok(Instruction::AND(Target::Immediate(data), target, size.unwrap())),
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0b0100 => Ok(Instruction::SUB(Target::Immediate(data), target, size.unwrap())),
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0b0110 => Ok(Instruction::ADD(Target::Immediate(data), target, size.unwrap())),
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0b1010 => Ok(Instruction::EOR(Target::Immediate(data), target, size.unwrap())),
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0b1100 => Ok(Instruction::CMP(Target::Immediate(data), target, size.unwrap())),
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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}
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},
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OPCG_MOVE_BYTE => {
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let src = self.decode_lower_effective_address(system, ins, Some(Size::Byte))?;
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let dest = self.decode_upper_effective_address(system, ins, Some(Size::Byte))?;
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Ok(Instruction::MOVE(src, dest, Size::Byte))
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},
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OPCG_MOVE_LONG => {
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let src = self.decode_lower_effective_address(system, ins, Some(Size::Long))?;
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let dest = self.decode_upper_effective_address(system, ins, Some(Size::Long))?;
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if let Target::DirectAReg(reg) = dest {
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Ok(Instruction::MOVEA(src, reg, Size::Long))
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} else {
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Ok(Instruction::MOVE(src, dest, Size::Long))
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}
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},
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OPCG_MOVE_WORD => {
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let src = self.decode_lower_effective_address(system, ins, Some(Size::Word))?;
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let dest = self.decode_upper_effective_address(system, ins, Some(Size::Word))?;
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if let Target::DirectAReg(reg) = dest {
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Ok(Instruction::MOVEA(src, reg, Size::Word))
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} else {
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Ok(Instruction::MOVE(src, dest, Size::Word))
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}
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},
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OPCG_MISC => {
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let ins_0f00 = ins & 0xF00;
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let ins_00f0 = ins & 0x0F0;
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if (ins & 0x180) == 0x180 {
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if (ins & 0x040) == 0 {
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let size = match get_size(ins) {
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Some(Size::Word) => Size::Word,
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Some(Size::Long) if self.cputype >= M68kType::MC68020 => Size::Long,
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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};
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let reg = get_high_reg(ins);
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let target = self.decode_lower_effective_address(system, ins, Some(size))?;
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Ok(Instruction::CHK(target, reg, size))
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} else {
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let src = self.decode_lower_effective_address(system, ins, None)?;
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let dest = get_high_reg(ins);
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Ok(Instruction::LEA(src, dest))
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}
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} else if (ins & 0xB80) == 0x880 && (ins & 0x038) != 0 {
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let mode = get_low_mode(ins);
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let size = if (ins & 0x0040) == 0 { Size::Word } else { Size::Long };
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let data = self.read_instruction_word(system)?;
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let target = self.decode_lower_effective_address(system, ins, None)?;
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let dir = if (ins & 0x0400) == 0 { Direction::ToTarget } else { Direction::FromTarget };
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Ok(Instruction::MOVEM(target, size, dir, data))
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} else if (ins & 0x800) == 0 {
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let target = self.decode_lower_effective_address(system, ins, Some(Size::Word))?;
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match (ins & 0x0700) >> 8 {
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0b000 => {
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match get_size(ins) {
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Some(size) => Ok(Instruction::NEGX(target, size)),
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None => Ok(Instruction::MOVEfromSR(target)),
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}
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},
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0b010 => {
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match get_size(ins) {
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Some(size) => Ok(Instruction::CLR(target, size)),
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None if self.cputype >= M68kType::MC68010 => Ok(Instruction::MOVEfromCCR(target)),
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None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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},
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0b100 => {
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match get_size(ins) {
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Some(size) => Ok(Instruction::NEG(target, size)),
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None => Ok(Instruction::MOVEtoCCR(target)),
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}
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},
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0b110 => {
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match get_size(ins) {
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Some(size) => Ok(Instruction::NOT(target, size)),
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None => Ok(Instruction::MOVEtoSR(target)),
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}
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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} else if ins_0f00 == 0x800 {
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let subselect = (ins & 0x01C0) >> 6;
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let mode = get_low_mode(ins);
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match (subselect, mode) {
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(0b000, _) => {
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let target = self.decode_lower_effective_address(system, ins, Some(Size::Byte))?;
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Ok(Instruction::NBCD(target))
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},
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(0b001, 0b000) => {
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Ok(Instruction::SWAP(get_low_reg(ins)))
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},
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(0b001, 0b001) => {
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Ok(Instruction::BKPT(get_low_reg(ins)))
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},
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(0b001, _) => {
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let target = self.decode_lower_effective_address(system, ins, None)?;
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Ok(Instruction::PEA(target))
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},
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(0b010, 0b000) |
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(0b011, 0b000) => {
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let size = if (ins & 0x0040) == 0 { Size::Word } else { Size::Long };
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Ok(Instruction::EXT(get_low_reg(ins), size))
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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} else if ins_0f00 == 0xA00 {
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if (ins & 0x0FF) == 0xFC {
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Ok(Instruction::ILLEGAL)
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} else {
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let target = self.decode_lower_effective_address(system, ins, Some(Size::Word))?;
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match get_size(ins) {
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Some(size) => Ok(Instruction::TST(target, size)),
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None => Ok(Instruction::TAS(target)),
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}
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}
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} else if ins_0f00 == 0xE00 {
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if (ins & 0x80) == 0x80 {
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let target = self.decode_lower_effective_address(system, ins, None)?;
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if (ins & 0b01000000) == 0 {
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Ok(Instruction::JSR(target))
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} else {
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Ok(Instruction::JMP(target))
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}
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} else if ins_00f0 == 0x40 {
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Ok(Instruction::TRAP((ins & 0x000F) as u8))
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} else if ins_00f0 == 0x50 {
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let reg = get_low_reg(ins);
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if (ins & 0b1000) == 0 {
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let data = self.read_instruction_word(system)?;
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Ok(Instruction::LINK(reg, data as i16))
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} else {
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Ok(Instruction::UNLK(reg))
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}
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} else if ins_00f0 == 0x60 {
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let reg = get_low_reg(ins);
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let dir = if (ins & 0b1000) == 0 { Direction::FromTarget } else { Direction::ToTarget };
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Ok(Instruction::MOVEUSP(Target::DirectAReg(reg), dir))
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} else {
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match ins & 0x00FF {
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0x70 => Ok(Instruction::RESET),
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0x71 => Ok(Instruction::NOP),
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0x72 => {
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let data = self.read_instruction_word(system)?;
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Ok(Instruction::STOP(data))
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},
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0x73 => Ok(Instruction::RTE),
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0x74 if self.cputype >= M68kType::MC68010 => {
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let offset = self.read_instruction_word(system)? as i16;
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Ok(Instruction::RTD(offset))
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},
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0x75 => Ok(Instruction::RTS),
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0x76 => Ok(Instruction::TRAPV),
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0x77 => Ok(Instruction::RTR),
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0x7A | 0x7B if self.cputype >= M68kType::MC68010 => {
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let dir = if ins & 0x01 == 0 { Direction::ToTarget } else { Direction::FromTarget };
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let ins2 = self.read_instruction_word(system)?;
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let target = match ins2 & 0x8000 {
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0 => Target::DirectDReg(((ins2 & 0x7000) >> 12) as u8),
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_ => Target::DirectAReg(((ins2 & 0x7000) >> 12) as u8),
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};
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let creg = match ins2 & 0xFFF {
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0x801 => ControlRegister::VBR,
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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};
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Ok(Instruction::MOVEC(target, creg, dir))
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},
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_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
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}
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}
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} else {
|
|
return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION));
|
|
}
|
|
},
|
|
OPCG_ADDQ_SUBQ => {
|
|
match get_size(ins) {
|
|
Some(size) => {
|
|
let target = self.decode_lower_effective_address(system, ins, Some(size))?;
|
|
let mut data = ((ins & 0x0E00) >> 9) as u32;
|
|
if data == 0 {
|
|
data = 8;
|
|
}
|
|
|
|
if (ins & 0x0100) == 0 {
|
|
Ok(Instruction::ADD(Target::Immediate(data), target, size))
|
|
} else {
|
|
Ok(Instruction::SUB(Target::Immediate(data), target, size))
|
|
}
|
|
},
|
|
None => {
|
|
let mode = get_low_mode(ins);
|
|
let condition = get_condition(ins);
|
|
|
|
if mode == 0b001 {
|
|
let reg = get_low_reg(ins);
|
|
let disp = self.read_instruction_word(system)? as i16;
|
|
Ok(Instruction::DBcc(condition, reg, disp))
|
|
} else {
|
|
let target = self.decode_lower_effective_address(system, ins, Some(Size::Byte))?;
|
|
Ok(Instruction::Scc(condition, target))
|
|
}
|
|
},
|
|
}
|
|
},
|
|
OPCG_BRANCH => {
|
|
let mut disp = ((ins & 0xFF) as i8) as i32;
|
|
if disp == 0 {
|
|
disp = (self.read_instruction_word(system)? as i16) as i32;
|
|
} else if disp == 0xff && self.cputype >= M68kType::MC68020 {
|
|
disp = self.read_instruction_long(system)? as i32;
|
|
}
|
|
let condition = get_condition(ins);
|
|
match condition {
|
|
Condition::True => Ok(Instruction::BRA(disp)),
|
|
Condition::False => Ok(Instruction::BSR(disp)),
|
|
_ => Ok(Instruction::Bcc(condition, disp)),
|
|
}
|
|
},
|
|
OPCG_MOVEQ => {
|
|
if (ins & 0x0100) != 0 {
|
|
return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION));
|
|
}
|
|
let reg = get_high_reg(ins);
|
|
let data = (ins & 0xFF) as u8;
|
|
Ok(Instruction::MOVEQ(data, reg))
|
|
},
|
|
OPCG_DIV_OR => {
|
|
let size = get_size(ins);
|
|
|
|
if size.is_none() {
|
|
let sign = if (ins & 0x0100) == 0 { Sign::Unsigned } else { Sign::Signed };
|
|
let data_reg = Target::DirectDReg(get_high_reg(ins));
|
|
let effective_addr = self.decode_lower_effective_address(system, ins, size)?;
|
|
Ok(Instruction::DIV(effective_addr, data_reg, Size::Word, sign))
|
|
} else if (ins & 0b000111110000) == 0b000100000000 {
|
|
// TODO SBCD
|
|
panic!("Not Implemented");
|
|
} else {
|
|
let data_reg = Target::DirectDReg(get_high_reg(ins));
|
|
let effective_addr = self.decode_lower_effective_address(system, ins, size)?;
|
|
let (from, to) = if (ins & 0x0100) == 0 { (effective_addr, data_reg) } else { (data_reg, effective_addr) };
|
|
Ok(Instruction::OR(from, to, size.unwrap()))
|
|
}
|
|
},
|
|
OPCG_SUB => {
|
|
let reg = get_high_reg(ins);
|
|
let dir = (ins & 0x0100) >> 8;
|
|
let size = get_size(ins);
|
|
match size {
|
|
Some(size) => {
|
|
if (ins & 0b100110000) == 0b100000000 {
|
|
// TODO implement SUBX
|
|
panic!("Not Implemented");
|
|
} else {
|
|
let target = self.decode_lower_effective_address(system, ins, Some(size))?;
|
|
if dir == 0 {
|
|
Ok(Instruction::SUB(target, Target::DirectDReg(reg), size))
|
|
} else {
|
|
Ok(Instruction::SUB(Target::DirectDReg(reg), target, size))
|
|
}
|
|
}
|
|
},
|
|
None => {
|
|
let size = if dir == 0 { Size::Word } else { Size::Long };
|
|
let target = self.decode_lower_effective_address(system, ins, Some(size))?;
|
|
Ok(Instruction::SUB(target, Target::DirectAReg(reg), size))
|
|
},
|
|
}
|
|
},
|
|
OPCG_CMP_EOR => {
|
|
let reg = get_high_reg(ins);
|
|
let optype = (ins & 0x0100) >> 8;
|
|
let size = get_size(ins);
|
|
match (optype, size) {
|
|
(0b1, Some(size)) => {
|
|
if get_low_mode(ins) == 0b001 {
|
|
Ok(Instruction::CMP(Target::IndirectARegInc(get_low_reg(ins)), Target::IndirectARegInc(reg), size))
|
|
} else {
|
|
let target = self.decode_lower_effective_address(system, ins, Some(size))?;
|
|
Ok(Instruction::EOR(Target::DirectDReg(reg), target, size))
|
|
}
|
|
},
|
|
(0b0, Some(size)) => {
|
|
let target = self.decode_lower_effective_address(system, ins, Some(size))?;
|
|
Ok(Instruction::CMP(target, Target::DirectDReg(reg), size))
|
|
},
|
|
(_, None) => {
|
|
let size = if optype == 0 { Size::Word } else { Size::Long };
|
|
let target = self.decode_lower_effective_address(system, ins, Some(size))?;
|
|
Ok(Instruction::CMPA(target, reg, size))
|
|
},
|
|
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
|
}
|
|
},
|
|
OPCG_MUL_AND => {
|
|
let size = get_size(ins);
|
|
|
|
if (ins & 0b000111110000) == 0b000100000000 {
|
|
// TODO ABCD
|
|
panic!("Not Implemented");
|
|
} else if (ins & 0b000100110000) == 0b000100000000 {
|
|
let regx = get_high_reg(ins);
|
|
let regy = get_low_reg(ins);
|
|
match (ins & 0x00F8) >> 3 {
|
|
0b01000 => Ok(Instruction::EXG(Target::DirectDReg(regx), Target::DirectDReg(regy))),
|
|
0b01001 => Ok(Instruction::EXG(Target::DirectAReg(regx), Target::DirectAReg(regy))),
|
|
0b10001 => Ok(Instruction::EXG(Target::DirectDReg(regx), Target::DirectAReg(regy))),
|
|
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
|
}
|
|
} else if size.is_none() {
|
|
let sign = if (ins & 0x0100) == 0 { Sign::Unsigned } else { Sign::Signed };
|
|
let data_reg = Target::DirectDReg(get_high_reg(ins));
|
|
let effective_addr = self.decode_lower_effective_address(system, ins, Some(Size::Word))?;
|
|
Ok(Instruction::MUL(effective_addr, data_reg, Size::Word, sign))
|
|
} else {
|
|
let data_reg = Target::DirectDReg(get_high_reg(ins));
|
|
let effective_addr = self.decode_lower_effective_address(system, ins, size)?;
|
|
let (from, to) = if (ins & 0x0100) == 0 { (effective_addr, data_reg) } else { (data_reg, effective_addr) };
|
|
Ok(Instruction::AND(from, to, size.unwrap()))
|
|
}
|
|
},
|
|
OPCG_ADD => {
|
|
let reg = get_high_reg(ins);
|
|
let dir = (ins & 0x0100) >> 8;
|
|
let size = get_size(ins);
|
|
match size {
|
|
Some(size) => {
|
|
if (ins & 0b100110000) == 0b100000000 {
|
|
// TODO implement ADDX
|
|
panic!("Not Implemented");
|
|
} else {
|
|
let target = self.decode_lower_effective_address(system, ins, Some(size))?;
|
|
if dir == 0 {
|
|
Ok(Instruction::ADD(target, Target::DirectDReg(reg), size))
|
|
} else {
|
|
Ok(Instruction::ADD(Target::DirectDReg(reg), target, size))
|
|
}
|
|
}
|
|
},
|
|
None => {
|
|
let size = if dir == 0 { Size::Word } else { Size::Long };
|
|
let target = self.decode_lower_effective_address(system, ins, Some(size))?;
|
|
Ok(Instruction::ADD(target, Target::DirectAReg(reg), size))
|
|
},
|
|
}
|
|
},
|
|
OPCG_SHIFT => {
|
|
let dir = if (ins & 0x0100) == 0 { ShiftDirection::Right } else { ShiftDirection::Left };
|
|
match get_size(ins) {
|
|
Some(size) => {
|
|
let reg = get_low_reg(ins);
|
|
let rotation = get_high_reg(ins);
|
|
let count = if (ins & 0x0020) == 0 {
|
|
Target::Immediate(if rotation != 0 { rotation as u32 } else { 8 })
|
|
} else {
|
|
Target::DirectDReg(rotation)
|
|
};
|
|
|
|
match (ins & 0x0018) >> 3 {
|
|
0b00 => Ok(Instruction::ASd(count, Target::DirectDReg(reg), size, dir)),
|
|
0b01 => Ok(Instruction::LSd(count, Target::DirectDReg(reg), size, dir)),
|
|
0b10 => Ok(Instruction::ROXd(count, Target::DirectDReg(reg), size, dir)),
|
|
0b11 => Ok(Instruction::ROd(count, Target::DirectDReg(reg), size, dir)),
|
|
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
|
}
|
|
},
|
|
None => {
|
|
let target = self.decode_lower_effective_address(system, ins, Some(Size::Word))?;
|
|
let count = Target::Immediate(1);
|
|
|
|
match (ins & 0x0600) >> 9 {
|
|
0b00 => Ok(Instruction::ASd(count, target, Size::Word, dir)),
|
|
0b01 => Ok(Instruction::LSd(count, target, Size::Word, dir)),
|
|
0b10 => Ok(Instruction::ROXd(count, target, Size::Word, dir)),
|
|
0b11 => Ok(Instruction::ROd(count, target, Size::Word, dir)),
|
|
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
|
}
|
|
},
|
|
}
|
|
},
|
|
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
|
}
|
|
}
|
|
|
|
fn read_instruction_word(&mut self, device: &mut AddressableDeviceRefMut<'_>) -> Result<u16, Error> {
|
|
let word = device.read_beu16((self.end - self.base) as Address)?;
|
|
//debug!("{:#010x} {:#06x?}", self.end, word);
|
|
self.end += 2;
|
|
Ok(word)
|
|
}
|
|
|
|
fn read_instruction_long(&mut self, device: &mut AddressableDeviceRefMut<'_>) -> Result<u32, Error> {
|
|
let word = device.read_beu32((self.end - self.base) as Address)?;
|
|
//debug!("{:#010x} {:#010x}", self.end, word);
|
|
self.end += 4;
|
|
Ok(word)
|
|
}
|
|
|
|
fn decode_lower_effective_address(&mut self, system: &mut AddressableDeviceRefMut<'_>, ins: u16, size: Option<Size>) -> Result<Target, Error> {
|
|
let reg = get_low_reg(ins);
|
|
let mode = get_low_mode(ins);
|
|
self.get_mode_as_target(system, mode, reg, size)
|
|
}
|
|
|
|
fn decode_upper_effective_address(&mut self, system: &mut AddressableDeviceRefMut<'_>, ins: u16, size: Option<Size>) -> Result<Target, Error> {
|
|
let reg = get_high_reg(ins);
|
|
let mode = get_high_mode(ins);
|
|
self.get_mode_as_target(system, mode, reg, size)
|
|
}
|
|
|
|
fn decode_extension_word(&mut self, system: &mut AddressableDeviceRefMut<'_>, areg: Option<u8>) -> Result<Target, Error> {
|
|
let brief_extension = self.read_instruction_word(system)?;
|
|
let rtype = if (brief_extension & 0x8000) == 0 { RegisterType::Data } else { RegisterType::Address };
|
|
let xreg = ((brief_extension & 0x7000) >> 12) as u8;
|
|
let size = if (brief_extension & 0x0800) == 0 { Size::Word } else { Size::Long };
|
|
let use_full = (brief_extension & 0x0100) == 1;
|
|
let scale = (brief_extension & 0x0600) >> 9 as u8;
|
|
|
|
if !use_full {
|
|
let displacement = sign_extend_to_long((brief_extension & 0x00FF) as u32, Size::Byte);
|
|
match areg {
|
|
Some(areg) => Ok(Target::IndirectARegXRegOffset(areg, rtype, xreg, displacement, size)),
|
|
None => Ok(Target::IndirectPCXRegOffset(rtype, xreg, displacement, size)),
|
|
}
|
|
} else if self.cputype >= M68kType::MC68020 {
|
|
let use_base = (brief_extension & 0x0080) == 0;
|
|
let use_index = (brief_extension & 0x0040) == 0;
|
|
|
|
panic!("Not Implemented");
|
|
} else {
|
|
Err(Error::processor(ERR_ILLEGAL_INSTRUCTION))
|
|
}
|
|
}
|
|
|
|
pub fn get_mode_as_target(&mut self, system: &mut AddressableDeviceRefMut<'_>, mode: u8, reg: u8, size: Option<Size>) -> Result<Target, Error> {
|
|
let value = match mode {
|
|
0b000 => Target::DirectDReg(reg),
|
|
0b001 => Target::DirectAReg(reg),
|
|
0b010 => Target::IndirectAReg(reg),
|
|
0b011 => Target::IndirectARegInc(reg),
|
|
0b100 => Target::IndirectARegDec(reg),
|
|
0b101 => {
|
|
let data = sign_extend_to_long(self.read_instruction_word(system)? as u32, Size::Word);
|
|
Target::IndirectARegOffset(reg, data)
|
|
},
|
|
0b110 => {
|
|
self.decode_extension_word(system, Some(reg))?
|
|
},
|
|
0b111 => {
|
|
match reg {
|
|
0b000 => {
|
|
let value = sign_extend_to_long(self.read_instruction_word(system)? as u32, Size::Word) as u32;
|
|
Target::IndirectMemory(value)
|
|
},
|
|
0b001 => {
|
|
let value = self.read_instruction_long(system)?;
|
|
Target::IndirectMemory(value)
|
|
},
|
|
0b010 => {
|
|
let data = sign_extend_to_long(self.read_instruction_word(system)? as u32, Size::Word);
|
|
Target::IndirectPCOffset(data)
|
|
},
|
|
0b011 => {
|
|
self.decode_extension_word(system, None)?
|
|
},
|
|
0b100 => {
|
|
let data = match size {
|
|
Some(Size::Byte) | Some(Size::Word) => self.read_instruction_word(system)? as u32,
|
|
Some(Size::Long) => self.read_instruction_long(system)?,
|
|
None => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
|
};
|
|
Target::Immediate(data)
|
|
},
|
|
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
|
}
|
|
},
|
|
_ => return Err(Error::processor(ERR_ILLEGAL_INSTRUCTION)),
|
|
};
|
|
Ok(value)
|
|
}
|
|
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn get_high_reg(ins: u16) -> u8 {
|
|
((ins & 0x0E00) >> 9) as u8
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn get_low_reg(ins: u16) -> u8 {
|
|
(ins & 0x0007) as u8
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn get_high_mode(ins: u16) -> u8 {
|
|
((ins & 0x01C0) >> 6) as u8
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn get_low_mode(ins: u16) -> u8 {
|
|
((ins & 0x0038) >> 3) as u8
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn get_size(ins: u16) -> Option<Size> {
|
|
match (ins & 0x00C0) >> 6 {
|
|
0b00 => Some(Size::Byte),
|
|
0b01 => Some(Size::Word),
|
|
0b10 => Some(Size::Long),
|
|
_ => None,
|
|
}
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn get_condition(ins: u16) -> Condition {
|
|
match (ins & 0x0F00) >> 8 {
|
|
0b0000 => Condition::True,
|
|
0b0001 => Condition::False,
|
|
0b0010 => Condition::High,
|
|
0b0011 => Condition::LowOrSame,
|
|
0b0100 => Condition::CarryClear,
|
|
0b0101 => Condition::CarrySet,
|
|
0b0110 => Condition::NotEqual,
|
|
0b0111 => Condition::Equal,
|
|
0b1000 => Condition::OverflowClear,
|
|
0b1001 => Condition::OverflowSet,
|
|
0b1010 => Condition::Plus,
|
|
0b1011 => Condition::Minus,
|
|
0b1100 => Condition::GreaterThanOrEqual,
|
|
0b1101 => Condition::LessThan,
|
|
0b1110 => Condition::GreaterThan,
|
|
0b1111 => Condition::LessThanOrEqual,
|
|
|
|
_ => Condition::True,
|
|
}
|
|
}
|
|
|
|
|
|
impl Size {
|
|
pub fn in_bytes(&self) -> u32 {
|
|
match self {
|
|
Size::Byte => 1,
|
|
Size::Word => 2,
|
|
Size::Long => 4,
|
|
}
|
|
}
|
|
|
|
pub fn in_bits(&self) -> u32 {
|
|
match self {
|
|
Size::Byte => 8,
|
|
Size::Word => 16,
|
|
Size::Long => 32,
|
|
}
|
|
}
|
|
}
|
|
|
|
pub fn sign_extend_to_long(value: u32, from: Size) -> i32 {
|
|
match from {
|
|
Size::Byte => ((value as u8) as i8) as i32,
|
|
Size::Word => ((value as u16) as i16) as i32,
|
|
Size::Long => value as i32,
|
|
}
|
|
}
|
|
|
|
impl fmt::Display for Target {
|
|
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
|
match self {
|
|
Target::Immediate(value) => write!(f, "#{:08x}", value),
|
|
Target::DirectDReg(reg) => write!(f, "%d{}", reg),
|
|
Target::DirectAReg(reg) => write!(f, "%a{}", reg),
|
|
Target::IndirectAReg(reg) => write!(f, "(%a{})", reg),
|
|
Target::IndirectARegInc(reg) => write!(f, "(%a{})+", reg),
|
|
Target::IndirectARegDec(reg) => write!(f, "-(%a{})", reg),
|
|
Target::IndirectARegOffset(reg, offset) => write!(f, "(%a{} + #{})", reg, offset),
|
|
Target::IndirectARegXRegOffset(reg, rtype, xreg, offset, _) => write!(f, "(%a{} + %{}{} + #{})", reg, if *rtype == RegisterType::Data { 'd' } else { 'a' }, xreg, offset),
|
|
Target::IndirectMemory(value) => write!(f, "(#{:08x})", value),
|
|
Target::IndirectPCOffset(offset) => write!(f, "(%pc + #{})", offset),
|
|
Target::IndirectPCXRegOffset(rtype, xreg, offset, _) => write!(f, "(%pc + %{}{} + #{})", if *rtype == RegisterType::Data { 'd' } else { 'a' }, xreg, offset),
|
|
}
|
|
}
|
|
}
|
|
|