mirror of
https://github.com/transistorfet/moa.git
synced 2024-11-26 07:49:17 +00:00
73 lines
2.9 KiB
Rust
73 lines
2.9 KiB
Rust
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use moa_core::{System, MemoryBlock, BusPort, Frequency, Address, Addressable, wrap_transmutable};
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use moa_z80::{Z80, Z80Type};
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use moa_z80::state::Register;
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use moa_z80::decode::{Instruction, LoadTarget, Target, RegisterPair, IndexRegister, IndexRegisterHalf};
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fn init_decode_test() -> (Z80, System) {
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let mut system = System::default();
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// Insert basic initialization
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let data = vec![0; 0x10000];
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let mem = MemoryBlock::new(data);
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system.add_addressable_device(0x0000, wrap_transmutable(mem)).unwrap();
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// Initialize the CPU and make sure it's in the expected state
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let mut cpu = Z80::new(Z80Type::Z80, Frequency::from_mhz(4), BusPort::new(0, 16, 8, system.bus.clone()));
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cpu.init().unwrap();
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(cpu, system)
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}
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fn load_memory(system: &System, data: &[u8]) {
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for i in 0..data.len() {
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system.get_bus().write_u8(system.clock, i as Address, data[i]).unwrap();
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}
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}
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fn run_decode_test(data: &[u8]) -> Instruction {
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let (mut cpu, system) = init_decode_test();
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load_memory(&system, data);
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cpu.decode_next().unwrap();
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cpu.decoder.instruction
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}
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#[test]
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fn run_all_decode_tests() {
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let mut failures = vec![];
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for (data, expected_instruction) in DECODE_TESTS {
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let instruction = run_decode_test(data);
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if instruction != *expected_instruction {
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failures.push((data, instruction, expected_instruction));
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}
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}
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let fails = failures.len();
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for (data, instruction, expected_instruction) in failures {
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println!("for {:?}\nexpected:\t{:?}\nreceived:\t{:?}\n", data, instruction, expected_instruction);
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}
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if fails > 0 {
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panic!("{} decode tests failed", fails);
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}
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}
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const DECODE_TESTS: &'static [(&[u8], Instruction)] = &[
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(&[0x00], Instruction::NOP),
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(&[0x01, 0x01, 0x02], Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::BC), LoadTarget::ImmediateWord(0x0201))),
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(&[0x02], Instruction::LD(LoadTarget::IndirectRegByte(RegisterPair::BC), LoadTarget::DirectRegByte(Register::A))),
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(&[0x03], Instruction::INC16(RegisterPair::BC)),
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(&[0x04], Instruction::INC8(Target::DirectReg(Register::B))),
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(&[0x05], Instruction::DEC8(Target::DirectReg(Register::B))),
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(&[0xDD, 0x09], Instruction::ADD16(RegisterPair::IX, RegisterPair::BC)),
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(&[0xDD, 0x44], Instruction::LD(LoadTarget::DirectRegByte(Register::B), LoadTarget::DirectRegHalfByte(IndexRegisterHalf::IXH))),
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(&[0xDD, 0x66, 0x12], Instruction::LD(LoadTarget::DirectRegByte(Register::H), LoadTarget::IndirectOffsetByte(IndexRegister::IX, 0x12))),
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(&[0xDD, 0x6E, 0x12], Instruction::LD(LoadTarget::DirectRegByte(Register::L), LoadTarget::IndirectOffsetByte(IndexRegister::IX, 0x12))),
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(&[0xDD, 0x84], Instruction::ADDa(Target::DirectRegHalf(IndexRegisterHalf::IXH))),
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(&[0xDD, 0x85], Instruction::ADDa(Target::DirectRegHalf(IndexRegisterHalf::IXL))),
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];
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