330 lines
7.9 KiB
Rust
330 lines
7.9 KiB
Rust
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use femtos::Instant;
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use emulator_hal::bus::{BusType, BusAccess};
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use moa_core::{Address, Addressable, BusPort};
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use crate::state::{M68k, M68kError, Exceptions};
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use crate::instructions::Size;
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#[repr(u8)]
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#[allow(dead_code)]
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum FunctionCode {
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Reserved0 = 0,
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UserData = 1,
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UserProgram = 2,
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Reserved3 = 3,
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Reserved4 = 4,
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SupervisorData = 5,
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SupervisorProgram = 6,
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CpuSpace = 7,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum MemType {
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Program,
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Data,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum MemAccess {
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Read,
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Write,
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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// TODO change to MemoryState or RequestState or AccessState or maybe even BusState
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pub struct MemoryRequest {
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pub i_n_bit: bool,
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pub access: MemAccess,
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pub code: FunctionCode,
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pub size: Size,
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pub address: u32,
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pub clock: Instant,
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}
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impl FunctionCode {
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pub fn program(is_supervisor: bool) -> Self {
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if is_supervisor {
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FunctionCode::SupervisorProgram
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} else {
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FunctionCode::UserProgram
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}
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}
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pub fn data(is_supervisor: bool) -> Self {
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if is_supervisor {
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FunctionCode::SupervisorData
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} else {
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FunctionCode::UserData
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}
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}
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}
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impl Default for MemoryRequest {
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fn default() -> Self {
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Self {
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i_n_bit: false,
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access: MemAccess::Read,
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code: FunctionCode::Reserved0,
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size: Size::Word,
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address: 0,
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clock: Instant::START,
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}
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}
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}
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impl MemoryRequest {
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pub(crate) fn instruction(&mut self, is_supervisor: bool, addr: u32) -> Result<u32, M68kError> {
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self.i_n_bit = false;
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self.code = FunctionCode::program(is_supervisor);
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self.access = MemAccess::Read;
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self.address = addr;
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validate_address(addr)
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}
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#[inline]
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pub fn get_type_code(&self) -> u16 {
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let ins = match self.i_n_bit {
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false => 0x0000,
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true => 0x0008,
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};
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let rw = match self.access {
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MemAccess::Write => 0x0000,
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MemAccess::Read => 0x0010,
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};
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ins | rw | (self.code as u16)
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}
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}
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#[derive(Clone, Debug)]
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pub struct InstructionRequest {
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pub request: MemoryRequest,
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pub current_clock: Instant,
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}
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#[derive(Clone, Debug)]
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pub struct M68kBusPort {
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//pub port: BusPort,
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pub request: MemoryRequest,
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pub cycle_start_clock: Instant,
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pub current_clock: Instant,
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}
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impl M68k {
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// TODO should some of the ones from execute.rs move here
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}
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impl Default for M68kBusPort {
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fn default(/* port: BusPort */) -> Self {
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Self {
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//port,
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request: Default::default(),
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cycle_start_clock: Instant::START,
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current_clock: Instant::START,
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}
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}
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}
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impl M68kBusPort {
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pub fn new(clock: Instant) -> Self {
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Self {
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request: Default::default(),
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cycle_start_clock: clock,
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current_clock: clock,
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}
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}
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pub(crate) fn read_data_sized(&mut self, port: &mut BusPort, is_supervisor: bool, addr: Address, size: Size) -> Result<u32, M68kError> {
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self.start_request(is_supervisor, addr as u32, size, MemAccess::Read, MemType::Data, false)?;
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Ok(match size {
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Size::Byte => port.read_u8(self.current_clock, addr).map(|value| value as u32),
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Size::Word => port.read_beu16(self.current_clock, addr).map(|value| value as u32),
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Size::Long => port.read_beu32(self.current_clock, addr),
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}?)
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}
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pub(crate) fn write_data_sized(&mut self, port: &mut BusPort, is_supervisor: bool, addr: Address, value: u32, size: Size) -> Result<(), M68kError> {
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self.start_request(is_supervisor, addr as u32, size, MemAccess::Write, MemType::Data, false)?;
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Ok(match size {
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Size::Byte => port.write_u8(self.current_clock, addr, value as u8),
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Size::Word => port.write_beu16(self.current_clock, addr, value as u16),
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Size::Long => port.write_beu32(self.current_clock, addr, value),
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}?)
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}
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pub(crate) fn read_instruction_word(&mut self, port: &mut BusPort, is_supervisor: bool, addr: u32) -> Result<u16, M68kError> {
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self.request.instruction(is_supervisor, addr)?;
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Ok(port.read_beu16(self.current_clock, addr as Address)?)
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}
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pub(crate) fn read_instruction_long(&mut self, port: &mut BusPort, is_supervisor: bool, addr: u32) -> Result<u32, M68kError> {
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self.request.instruction(is_supervisor, addr)?;
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Ok(port.read_beu32(self.current_clock, addr as Address)?)
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}
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pub(crate) fn start_request(&mut self, is_supervisor: bool, addr: u32, size: Size, access: MemAccess, mtype: MemType, i_n_bit: bool) -> Result<u32, M68kError> {
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self.request.i_n_bit = i_n_bit;
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self.request.code = match mtype {
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MemType::Program => FunctionCode::program(is_supervisor),
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MemType::Data => FunctionCode::data(is_supervisor),
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};
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self.request.access = access;
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self.request.address = addr;
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if size == Size::Byte {
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Ok(addr)
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} else {
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validate_address(addr)
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}
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}
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pub(crate) fn dump_memory(&mut self, port: &mut BusPort, addr: u32, length: usize) {
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port.dump_memory(self.current_clock, addr as Address, length as u64);
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}
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}
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fn validate_address(addr: u32) -> Result<u32, M68kError> {
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if addr & 0x1 == 0 {
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Ok(addr)
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} else {
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Err(M68kError::Exception(Exceptions::AddressError))
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}
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}
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/*
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impl BusType for M68kBusPort {
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type Instant = Instant;
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type Error = Error;
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}
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impl BusAccess<u32> for M68kBusPort {
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fn read(&mut self, now: Self::Instant, addr: Address, data: &mut [u8]) -> Result<usize, Self::Error> {
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self.
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}
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fn write(&mut self, now: Self::Instant, addr: Address, data: &[u8]) -> Result<usize, Self::Error> {
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}
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}
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*/
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/*
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pub(crate) struct TargetAccess {
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must_read: bool,
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must_write: bool,
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size: Size,
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target: Target,
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}
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impl TargetAccess {
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pub(crate) fn read_only(size: Size) -> Self {
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}
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pub(crate) fn read_update(size: Size) -> Self {
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}
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pub(crate) fn updated_only(size: Size) -> Self {
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}
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pub(crate) fn get(&mut self, cpu: &M68k) -> Result<u32, M68kError> {
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}
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pub(crate) fn set(&mut self, cpu: &M68k, value: u32) -> Result<(), M68kError> {
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}
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pub(crate) fn complete(&self) -> Result<Self, M68kError> {
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}
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}
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impl Target {
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pub(crate) fn read_once(self, size: Size) -> ReadOnceAccess {
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ReadOnceAccess {
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size,
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target: self,
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accessed: false,
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}
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}
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pub(crate) fn read_update(self, size: Size) -> ReadUpdateAccess {
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ReadUpdateAccess {
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size,
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target: self,
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}
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}
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pub(crate) fn write_once(self, size: Size) -> WriteOnceAccess {
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WriteOnceAccess {
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size,
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target: self,
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}
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}
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}
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pub(crate) struct ReadOnceAccess {
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size: Size,
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target: Target,
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accessed: bool,
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}
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impl ReadOnceAccess {
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pub(crate) fn get(&mut self, cpu: &M68k) -> Result<u32, M68kError> {
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}
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pub(crate) fn complete(&self) -> Result<Self, M68kError> {
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}
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}
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pub(crate) struct ReadUpdateAccess {
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size: Size,
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target: Target,
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}
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impl ReadUpdateAccess {
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pub(crate) fn get(&mut self, cpu: &M68k) -> Result<u32, M68kError> {
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}
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pub(crate) fn set(&mut self, cpu: &M68k, value: u32) -> Result<(), M68kError> {
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}
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pub(crate) fn complete(&self) -> Result<Self, M68kError> {
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}
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}
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pub(crate) struct WriteOnceAccess {
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size: Size,
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target: Target,
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}
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impl WriteOnceAccess {
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pub(crate) fn set(&mut self, cpu: &M68k, value: u32) -> Result<(), M68kError> {
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}
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pub(crate) fn complete(&self) -> Result<Self, M68kError> {
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}
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}
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*/
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