378 lines
13 KiB
Rust
378 lines
13 KiB
Rust
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#[cfg(test)]
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mod decode_unit_tests {
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use femtos::Instant;
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use emulator_hal::bus::BusAccess;
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use emulator_hal_memory::MemoryBlock;
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use crate::M68kType;
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use crate::instructions::{Target, Size, XRegister, BaseRegister, IndexRegister};
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use crate::decode::{M68kDecoder, InstructionDecoding};
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use crate::memory::M68kBusPort;
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const INIT_ADDR: u32 = 0x00000000;
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fn run_decode_test<F>(cputype: M68kType, mut test_func: F)
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where
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F: FnMut(&mut InstructionDecoding<'_, MemoryBlock<u32, Instant>>),
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{
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let mut memory = MemoryBlock::from(vec![0; 0x0000100]);
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let mut decoder = M68kDecoder::new(cputype, true, 0);
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let mut decoding = InstructionDecoding {
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bus: &mut memory,
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memory: &mut M68kBusPort::default(),
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decoder: &mut decoder,
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};
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test_func(&mut decoding);
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}
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//
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// Addressing Mode Target Tests
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//
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#[test]
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fn target_direct_d() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Word;
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let target = decoder.get_mode_as_target(0b000, 0b001, Some(size)).unwrap();
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assert_eq!(target, Target::DirectDReg(1));
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});
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}
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#[test]
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fn target_direct_a() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Word;
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let target = decoder.get_mode_as_target(0b001, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::DirectAReg(2));
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});
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}
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#[test]
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fn target_indirect_a() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Long;
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let expected = 0x12345678;
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decoder.bus.write_beu32(Instant::START, INIT_ADDR, expected).unwrap();
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let target = decoder.get_mode_as_target(0b010, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectAReg(2));
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});
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}
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#[test]
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fn target_indirect_a_inc() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Long;
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let expected = 0x12345678;
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decoder.bus.write_beu32(Instant::START, INIT_ADDR, expected).unwrap();
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let target = decoder.get_mode_as_target(0b011, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectARegInc(2));
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});
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}
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#[test]
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fn target_indirect_a_dec() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Long;
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let expected = 0x12345678;
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decoder.bus.write_beu32(Instant::START, INIT_ADDR, expected).unwrap();
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let target = decoder.get_mode_as_target(0b100, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectARegDec(2));
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});
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}
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#[test]
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fn target_indirect_a_reg_offset() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Long;
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let offset = -8;
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, (offset as i16) as u16).unwrap();
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let target = decoder.get_mode_as_target(0b101, 0b100, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(4), None, offset));
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});
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}
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#[test]
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fn target_indirect_a_reg_brief_extension_word() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Long;
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let offset = -8;
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let brief_extension = 0x3800 | (((offset as i8) as u8) as u16);
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, brief_extension).unwrap();
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decoder.bus.write_beu16(Instant::START, INIT_ADDR + 2, (offset as i16) as u16).unwrap();
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let target = decoder.get_mode_as_target(0b110, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), Some(IndexRegister { xreg: XRegister::DReg(3), scale: 0, size: size }), offset));
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});
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}
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#[test]
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fn target_indirect_a_reg_full_extension_word() {
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run_decode_test(M68kType::MC68020, |decoder| {
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let size = Size::Word;
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let offset = -1843235 as i32;
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let brief_extension = 0xF330;
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, brief_extension).unwrap();
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decoder.bus.write_beu32(Instant::START, INIT_ADDR + 2, offset as u32).unwrap();
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let target = decoder.get_mode_as_target(0b110, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset));
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});
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}
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#[test]
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fn target_indirect_a_reg_full_extension_word_no_base() {
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run_decode_test(M68kType::MC68020, |decoder| {
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let size = Size::Word;
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let offset = -1843235 as i32;
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let brief_extension = 0xF3B0;
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, brief_extension).unwrap();
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decoder.bus.write_beu32(Instant::START, INIT_ADDR + 2, offset as u32).unwrap();
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let target = decoder.get_mode_as_target(0b110, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset));
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});
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}
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#[test]
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fn target_indirect_a_reg_full_extension_word_no_index() {
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run_decode_test(M68kType::MC68020, |decoder| {
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let size = Size::Word;
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let offset = -1843235 as i32;
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let brief_extension = 0xF370;
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, brief_extension).unwrap();
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decoder.bus.write_beu32(Instant::START, INIT_ADDR + 2, offset as u32).unwrap();
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let target = decoder.get_mode_as_target(0b110, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), None, offset));
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});
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}
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#[test]
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fn target_indirect_pc_offset() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Long;
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let offset = -8;
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, (offset as i16) as u16).unwrap();
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let target = decoder.get_mode_as_target(0b111, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, None, offset));
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});
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}
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#[test]
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fn target_indirect_pc_brief_extension_word() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Word;
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let offset = -8;
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let brief_extension = 0x3000 | (((offset as i8) as u8) as u16);
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, brief_extension).unwrap();
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decoder.bus.write_beu16(Instant::START, INIT_ADDR + 2, (offset as i16) as u16).unwrap();
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let target = decoder.get_mode_as_target(0b111, 0b011, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(3), scale: 0, size: size }), offset));
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});
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}
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#[test]
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fn target_indirect_pc_full_extension_word() {
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run_decode_test(M68kType::MC68020, |decoder| {
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let size = Size::Word;
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let offset = -1843235 as i32;
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let brief_extension = 0xF330;
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, brief_extension).unwrap();
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decoder.bus.write_beu32(Instant::START, INIT_ADDR + 2, offset as u32).unwrap();
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let target = decoder.get_mode_as_target(0b111, 0b011, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset));
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});
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}
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#[test]
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fn target_indirect_immediate_word() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Word;
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let expected = 0x1234;
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, expected as u16).unwrap();
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let target = decoder.get_mode_as_target(0b111, 0b000, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectMemory(expected, Size::Word));
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});
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}
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#[test]
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fn target_indirect_immediate_long() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Word;
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let expected = 0x12345678;
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decoder.bus.write_beu32(Instant::START, INIT_ADDR, expected).unwrap();
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let target = decoder.get_mode_as_target(0b111, 0b001, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectMemory(expected, Size::Long));
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});
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}
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#[test]
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fn target_immediate() {
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run_decode_test(M68kType::MC68010, |decoder| {
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let size = Size::Word;
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let expected = 0x1234;
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decoder.bus.write_beu16(Instant::START, INIT_ADDR, expected as u16).unwrap();
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let target = decoder.get_mode_as_target(0b111, 0b100, Some(size)).unwrap();
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assert_eq!(target, Target::Immediate(expected));
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});
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}
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}
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#[cfg(test)]
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mod execute_unit_tests {
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use femtos::{Instant, Frequency};
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use emulator_hal::bus::BusAccess;
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use emulator_hal::step::Step;
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use emulator_hal_memory::MemoryBlock;
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use crate::{M68k, M68kType};
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use crate::execute::{Used, M68kCycle, M68kCycleExecutor};
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use crate::instructions::{Instruction, Target, Size};
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const INIT_STACK: u32 = 0x00002000;
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const INIT_ADDR: u32 = 0x00000010;
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#[allow(clippy::uninit_vec)]
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fn run_execute_test<F>(cputype: M68kType, mut test_func: F)
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where
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F: FnMut(M68kCycleExecutor<&mut MemoryBlock<u32, Instant>>),
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{
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// Insert basic initialization
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let len = 0x10_0000;
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let mut data = Vec::with_capacity(len);
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unsafe { data.set_len(len); }
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let mut memory = MemoryBlock::from(data);
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memory.write_beu32(Instant::START, 0, INIT_STACK as u32).unwrap();
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memory.write_beu32(Instant::START, 4, INIT_ADDR as u32).unwrap();
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let mut cpu = M68k::from_type(cputype, Frequency::from_mhz(10));
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cpu.step(Instant::START, &mut memory).unwrap();
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let cycle = M68kCycle::new(&mut cpu, Instant::START);
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let mut executor = cycle.begin(&mut cpu, &mut memory);
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executor.cycle.decoder.init(true, executor.state.pc);
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assert_eq!(executor.state.pc, INIT_ADDR as u32);
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assert_eq!(executor.state.ssp, INIT_STACK as u32);
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assert_eq!(executor.cycle.decoder.instruction, Instruction::NOP);
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test_func(executor);
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}
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//
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// Addressing Mode Target Tests
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//
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#[test]
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fn target_value_direct_d() {
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run_execute_test(M68kType::MC68010, |mut cycle| {
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let size = Size::Word;
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let expected = 0x1234;
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let target = Target::DirectDReg(1);
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cycle.state.d_reg[1] = expected;
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let result = cycle.get_target_value(target, size, Used::Once).unwrap();
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assert_eq!(result, expected);
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});
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}
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#[test]
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fn target_value_direct_a() {
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run_execute_test(M68kType::MC68010, |mut cycle| {
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let size = Size::Word;
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let expected = 0x1234;
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let target = Target::DirectAReg(2);
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cycle.state.a_reg[2] = expected;
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let result = cycle.get_target_value(target, size, Used::Once).unwrap();
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assert_eq!(result, expected);
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});
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}
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#[test]
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fn target_value_indirect_a() {
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run_execute_test(M68kType::MC68010, |mut cycle| {
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let size = Size::Long;
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let expected = 0x12345678;
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let target = Target::IndirectAReg(2);
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cycle.bus.write_beu32(Instant::START, INIT_ADDR, expected).unwrap();
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cycle.state.a_reg[2] = INIT_ADDR as u32;
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let result = cycle.get_target_value(target, size, Used::Once).unwrap();
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assert_eq!(result, expected);
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});
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}
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#[test]
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fn target_value_indirect_a_inc() {
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run_execute_test(M68kType::MC68010, |mut cycle| {
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let size = Size::Long;
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let expected = 0x12345678;
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let target = Target::IndirectARegInc(2);
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cycle.bus.write_beu32(Instant::START, INIT_ADDR, expected).unwrap();
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cycle.state.a_reg[2] = INIT_ADDR as u32;
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let result = cycle.get_target_value(target, size, Used::Once).unwrap();
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assert_eq!(result, expected);
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assert_eq!(cycle.state.a_reg[2], (INIT_ADDR as u32) + 4);
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});
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}
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#[test]
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fn target_value_indirect_a_dec() {
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run_execute_test(M68kType::MC68010, |mut cycle| {
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let size = Size::Long;
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let expected = 0x12345678;
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let target = Target::IndirectARegDec(2);
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cycle.bus.write_beu32(Instant::START, INIT_ADDR, expected).unwrap();
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cycle.state.a_reg[2] = (INIT_ADDR as u32) + 4;
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let result = cycle.get_target_value(target, size, Used::Once).unwrap();
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assert_eq!(result, expected);
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assert_eq!(cycle.state.a_reg[2], INIT_ADDR as u32);
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});
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}
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#[test]
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fn target_value_immediate() {
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run_execute_test(M68kType::MC68010, |mut cycle| {
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let size = Size::Word;
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let expected = 0x1234;
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let target = Target::Immediate(expected);
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let result = cycle.get_target_value(target, size, Used::Once).unwrap();
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assert_eq!(result, expected);
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});
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}
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}
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