mirror of
https://github.com/transistorfet/moa.git
synced 2024-11-24 23:32:46 +00:00
196 lines
10 KiB
Rust
196 lines
10 KiB
Rust
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use moa_core::{System, MemoryBlock, BusPort, Address, Addressable, wrap_transmutable};
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use moa_m68k::{M68k, M68kType};
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use moa_m68k::instructions::{Instruction, Target, Size, Sign, XRegister, BaseRegister, IndexRegister, Direction, ShiftDirection};
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use moa_m68k::assembler::M68kAssembler;
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const INIT_STACK: Address = 0x00002000;
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const INIT_ADDR: Address = 0x00000010;
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struct TestCase {
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cpu: M68kType,
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data: &'static [u16],
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ins: Option<Instruction>,
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}
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const DECODE_TESTS: &'static [TestCase] = &[
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// MC68000
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TestCase { cpu: M68kType::MC68000, data: &[0x4e71], ins: Some(Instruction::NOP) },
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// TODO I think this one is illegal (which is causing problems for the assembler)
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//TestCase { cpu: M68kType::MC68000, data: &[0x0008, 0x00FF], ins: Some(Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x003C, 0x00FF], ins: Some(Instruction::ORtoCCR(0xFF)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x007C, 0x1234], ins: Some(Instruction::ORtoSR(0x1234)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0263, 0x1234], ins: Some(Instruction::AND(Target::Immediate(0x1234), Target::IndirectARegDec(3), Size::Word)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0240, 0x1234], ins: Some(Instruction::AND(Target::Immediate(0x1234), Target::DirectDReg(0), Size::Word)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x02A3, 0x1234, 0x5678], ins: Some(Instruction::AND(Target::Immediate(0x12345678), Target::IndirectARegDec(3), Size::Long)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0280, 0x1234, 0x5678], ins: Some(Instruction::AND(Target::Immediate(0x12345678), Target::DirectDReg(0), Size::Long)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x023C, 0x1234], ins: Some(Instruction::ANDtoCCR(0x34)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x027C, 0xF8FF], ins: Some(Instruction::ANDtoSR(0xF8FF)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x4240], ins: Some(Instruction::CLR(Target::DirectDReg(0), Size::Word)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x4280], ins: Some(Instruction::CLR(Target::DirectDReg(0), Size::Long)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x4250], ins: Some(Instruction::CLR(Target::IndirectAReg(0), Size::Word)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x4290], ins: Some(Instruction::CLR(Target::IndirectAReg(0), Size::Long)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0487, 0x1234, 0x5678], ins: Some(Instruction::SUB(Target::Immediate(0x12345678), Target::DirectDReg(7), Size::Long)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x063A, 0x1234, 0x0055], ins: Some(Instruction::ADD(Target::Immediate(0x34), Target::IndirectRegOffset(BaseRegister::PC, None, 0x55), Size::Byte)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0A23, 0x1234], ins: Some(Instruction::EOR(Target::Immediate(0x34), Target::IndirectARegDec(3), Size::Byte)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0A3C, 0x1234], ins: Some(Instruction::EORtoCCR(0x34)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0A7C, 0xF8FF], ins: Some(Instruction::EORtoSR(0xF8FF)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0020], ins: Some(Instruction::CMP(Target::Immediate(0x20), Target::DirectDReg(0), Size::Byte)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0030], ins: Some(Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0010], ins: Some(Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x81FC, 0x0003], ins: Some(Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed)) },
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TestCase { cpu: M68kType::MC68000, data: &[0xC1FC, 0x0276], ins: Some(Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed)) },
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TestCase { cpu: M68kType::MC68000, data: &[0xCDC5], ins: Some(Instruction::MULW(Target::DirectDReg(5), 6, Sign::Signed)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0108, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::FromTarget)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0148, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Long, Direction::FromTarget)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x0188, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::ToTarget)) },
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TestCase { cpu: M68kType::MC68000, data: &[0x01C8, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Long, Direction::ToTarget)) },
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TestCase { cpu: M68kType::MC68000, data: &[0xE300], ins: Some(Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left)) },
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TestCase { cpu: M68kType::MC68000, data: &[0xE200], ins: Some(Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right)) },
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TestCase { cpu: M68kType::MC68000, data: &[0xE318], ins: Some(Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left)) },
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TestCase { cpu: M68kType::MC68000, data: &[0xE218], ins: Some(Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right)) },
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TestCase { cpu: M68kType::MC68000, data: &[0xA000], ins: Some(Instruction::UnimplementedA(0xA000)) },
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TestCase { cpu: M68kType::MC68000, data: &[0xFFFF], ins: Some(Instruction::UnimplementedF(0xFFFF)) },
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// MC68030
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TestCase { cpu: M68kType::MC68030, data: &[0x4C3C, 0x0800, 0x0000, 0x0097], ins: Some(Instruction::MULL(Target::Immediate(0x97), None, 0, Sign::Signed)) },
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TestCase { cpu: M68kType::MC68030, data: &[0x21BC, 0x0010, 0x14C4, 0x09B0, 0x0010, 0xDF40], ins: Some(Instruction::MOVE(Target::Immediate(1053892), Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Long }), 0x10df40), Size::Long)) },
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// Should Fail
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];
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fn init_decode_test(cputype: M68kType) -> (M68k, System) {
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let mut system = System::default();
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// Insert basic initialization
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let data = vec![0; 0x00100000];
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let mem = MemoryBlock::new(data);
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system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap();
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system.get_bus().write_beu32(0, INIT_STACK as u32).unwrap();
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system.get_bus().write_beu32(4, INIT_ADDR as u32).unwrap();
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// Initialize the CPU and make sure it's in the expected state
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let port = if cputype <= M68kType::MC68010 {
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BusPort::new(0, 24, 16, system.bus.clone())
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} else {
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BusPort::new(0, 24, 16, system.bus.clone())
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};
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let mut cpu = M68k::new(cputype, 10_000_000, port);
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cpu.init().unwrap();
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assert_eq!(cpu.state.pc, INIT_ADDR as u32);
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assert_eq!(cpu.state.ssp, INIT_STACK as u32);
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cpu.decoder.init(INIT_ADDR as u32);
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assert_eq!(cpu.decoder.start, INIT_ADDR as u32);
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assert_eq!(cpu.decoder.instruction, Instruction::NOP);
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(cpu, system)
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}
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fn load_memory(system: &System, data: &[u16]) {
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let mut addr = INIT_ADDR;
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for word in data {
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system.get_bus().write_beu16(addr, *word).unwrap();
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addr += 2;
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}
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}
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fn run_decode_test(case: &TestCase) {
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let (mut cpu, system) = init_decode_test(case.cpu);
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load_memory(&system, case.data);
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match &case.ins {
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Some(ins) => {
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cpu.decode_next().unwrap();
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assert_eq!(cpu.decoder.instruction, ins.clone());
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},
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None => {
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let next = cpu.decode_next();
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println!("{:?}", cpu.decoder.instruction);
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assert!(next.is_err());
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},
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}
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}
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#[test]
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pub fn run_decode_tests() {
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for case in DECODE_TESTS {
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println!("Testing for {:?}", case.ins);
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run_decode_test(case);
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}
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}
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#[test]
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pub fn run_assembler_tests() {
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let mut tests = 0;
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let mut errors = 0;
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for case in DECODE_TESTS {
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if case.ins.is_some() {
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tests += 1;
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let assembly_text = format!("{}", case.ins.as_ref().unwrap());
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print!("Testing assembling of {:?} ", assembly_text);
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let mut assembler = M68kAssembler::new(M68kType::MC68000);
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match assembler.assemble_words(&assembly_text) {
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Ok(data) => {
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if data == case.data {
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print!("pass");
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} else {
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errors += 1;
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print!("FAILED");
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print!("\nleft: {:?}, right: {:?}", data, case.data);
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}
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println!();
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},
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Err(err) => {
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println!("FAILED\n{:?}", err);
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errors += 1;
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},
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}
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}
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}
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if errors > 0 {
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panic!("{} errors out of {} tests", errors, tests);
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}
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}
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/*
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#[test]
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pub fn run_assembler_opcode_tests() {
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let mut tests = 0;
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let mut errors = 0;
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use super::super::testcases::{TimingCase, TIMING_TESTS};
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for case in TIMING_TESTS {
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tests += 1;
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let assembly_text = format!("{}", case.ins);
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print!("Testing assembling of {:?} from {:?}", assembly_text, case.ins);
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let mut assembler = M68kAssembler::new(M68kType::MC68000);
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match assembler.assemble_words(&assembly_text) {
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Ok(data) => {
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if data[0] == case.data[0] {
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print!("pass");
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} else {
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errors += 1;
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print!("FAILED");
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print!("\nleft: {:#06x}, right: {:#06x}", data[0], case.data[0]);
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}
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println!();
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},
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Err(err) => {
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println!("FAILED\n{:?}", err);
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errors += 1;
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},
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}
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}
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if errors > 0 {
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panic!("{} errors out of {} tests", errors, tests);
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}
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}
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*/
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