1300 lines
49 KiB
Rust
1300 lines
49 KiB
Rust
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use moa_core::{System, Error, ClockTime, ClockDuration, Address, Steppable, Addressable, Interruptable, Debuggable, Transmutable, read_beu16, write_beu16};
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use crate::instructions::{Condition, Instruction, LoadTarget, Target, Register, InterruptMode, RegisterPair, IndexRegister, SpecialRegister, IndexRegisterHalf, Size, Direction, UndocumentedCopy};
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use crate::state::{Z80, Status, Flags};
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use crate::timing::Z80InstructionCycles;
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const DEV_NAME: &str = "z80-cpu";
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const FLAGS_NUMERIC: u8 = 0xC0;
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const FLAGS_ARITHMETIC: u8 = 0x17;
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const FLAGS_CARRY_HALF_CARRY: u8 = 0x11;
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enum RotateType {
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Bit8,
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Bit9,
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}
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impl Steppable for Z80 {
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fn step(&mut self, system: &System) -> Result<ClockDuration, Error> {
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let clocks = if self.reset.get() {
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self.reset()?
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} else if self.bus_request.get() {
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4
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} else {
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self.step_internal(system)?
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};
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Ok(self.frequency.period_duration() * clocks as u64)
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}
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fn on_error(&mut self, system: &System) {
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self.dump_state(system.clock);
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}
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}
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impl Interruptable for Z80 { }
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impl Transmutable for Z80 {
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fn as_steppable(&mut self) -> Option<&mut dyn Steppable> {
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Some(self)
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}
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fn as_interruptable(&mut self) -> Option<&mut dyn Interruptable> {
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Some(self)
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}
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fn as_debuggable(&mut self) -> Option<&mut dyn Debuggable> {
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Some(self)
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}
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}
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#[derive(Clone)]
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pub struct Z80Executor {
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pub current_clock: ClockTime,
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pub took_branch: bool,
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}
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impl Z80Executor {
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pub fn at_time(current_clock: ClockTime) -> Self {
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Self {
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current_clock,
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took_branch: false,
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}
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}
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}
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impl Z80 {
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pub fn step_internal(&mut self, system: &System) -> Result<u16, Error> {
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self.executor = Z80Executor::at_time(system.clock);
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match self.state.status {
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Status::Init => self.init(),
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Status::Halted => Err(Error::new("CPU stopped")),
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Status::Running => {
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match self.cycle_one() {
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Ok(clocks) => Ok(clocks),
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Err(Error::Processor(_)) => {
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Ok(4)
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},
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Err(err) => Err(err),
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}
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},
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}
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}
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pub fn init(&mut self) -> Result<u16, Error> {
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self.state.pc = 0;
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self.state.status = Status::Running;
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Ok(16)
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}
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pub fn reset(&mut self) -> Result<u16, Error> {
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self.clear_state();
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Ok(16)
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}
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pub fn cycle_one(&mut self) -> Result<u16, Error> {
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self.check_breakpoints()?;
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self.decode_next()?;
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self.execute_current()?;
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Ok(Z80InstructionCycles::from_instruction(&self.decoder.instruction, self.decoder.extra_instruction_bytes)?
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.calculate_cycles(self.executor.took_branch))
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}
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pub fn decode_next(&mut self) -> Result<(), Error> {
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self.decoder.decode_at(&mut self.port, self.executor.current_clock, self.state.pc)?;
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self.increment_refresh(self.decoder.end.saturating_sub(self.decoder.start) as u8);
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self.state.pc = self.decoder.end;
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Ok(())
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}
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pub fn execute_current(&mut self) -> Result<(), Error> {
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match self.decoder.instruction {
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Instruction::ADCa(target) => self.execute_adca(target),
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Instruction::ADC16(dest_pair, src_pair) => self.execute_adc16(dest_pair, src_pair),
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Instruction::ADDa(target) => self.execute_adda(target),
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Instruction::ADD16(dest_pair, src_pair) => self.execute_add16(dest_pair, src_pair),
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Instruction::AND(target) => self.execute_and(target),
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Instruction::BIT(bit, target) => self.execute_bit(bit, target),
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Instruction::CALL(addr) => self.execute_call(addr),
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Instruction::CALLcc(cond, addr) => self.execute_callcc(cond, addr),
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Instruction::CCF => self.execute_ccf(),
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Instruction::CP(target) => self.execute_cp(target),
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//Instruction::CPD => {
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//},
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//Instruction::CPDR => {
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//},
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//Instruction::CPI => {
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//},
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//Instruction::CPIR => {
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//},
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Instruction::CPL => self.execute_cpl(),
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Instruction::DAA => self.execute_daa(),
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Instruction::DEC16(regpair) => self.execute_dec16(regpair),
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Instruction::DEC8(target) => self.execute_dec8(target),
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Instruction::DI => self.execute_di(),
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Instruction::DJNZ(offset) => self.execute_djnz(offset),
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Instruction::EI => self.execute_ei(),
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Instruction::EXX => self.execute_exx(),
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Instruction::EXafaf => self.execute_ex_af_af(),
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Instruction::EXhlde => self.execute_ex_hl_de(),
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Instruction::EXsp(regpair) => self.execute_ex_sp(regpair),
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Instruction::HALT => self.execute_halt(),
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Instruction::IM(mode) => self.execute_im(mode),
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Instruction::INC16(regpair) => self.execute_inc16(regpair),
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Instruction::INC8(target) => self.execute_inc8(target),
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//Instruction::IND => {
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//},
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//Instruction::INDR => {
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//},
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Instruction::INI => self.execute_ini(),
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//Instruction::INIR => {
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//},
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Instruction::INic(reg) => self.execute_inic(reg),
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//Instruction::INicz => {
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//},
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Instruction::INx(n) => self.execute_inx(n),
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Instruction::JP(addr) => self.execute_jp(addr),
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Instruction::JPIndirect(regpair) => self.execute_jp_indirect(regpair),
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Instruction::JPcc(cond, addr) => self.execute_jpcc(cond, addr),
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Instruction::JR(offset) => self.execute_jr(offset),
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Instruction::JRcc(cond, offset) => self.execute_jrcc(cond, offset),
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Instruction::LD(dest, src) => self.execute_ld(dest, src),
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Instruction::LDsr(special_reg, dir) => self.execute_ldsr(special_reg, dir),
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Instruction::LDD | Instruction::LDDR | Instruction::LDI | Instruction::LDIR => self.execute_ldx(),
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Instruction::NEG => self.execute_neg(),
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Instruction::NOP => {
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Ok(())
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},
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Instruction::OR(target) => self.execute_or(target),
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//Instruction::OTDR => {
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//},
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//Instruction::OTIR => {
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//},
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//Instruction::OUTD => {
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//},
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//Instruction::OUTI => {
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//},
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Instruction::OUTic(reg) => self.execute_outic(reg),
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//Instruction::OUTicz => {
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//},
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Instruction::OUTx(n) => self.execute_outx(n),
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Instruction::POP(regpair) => self.execute_pop(regpair),
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Instruction::PUSH(regpair) => self.execute_push(regpair),
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Instruction::RES(bit, target, opt_copy) => self.execute_res(bit, target, opt_copy),
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Instruction::RET => self.execute_ret(),
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Instruction::RETI => self.execute_reti(),
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Instruction::RETN => self.execute_retn(),
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Instruction::RETcc(cond) => self.execute_retcc(cond),
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Instruction::RL(target, opt_copy) => self.execute_rl(target, opt_copy),
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Instruction::RLA => self.execute_rla(),
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Instruction::RLC(target, opt_copy) => self.execute_rlc(target, opt_copy),
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Instruction::RLCA => self.execute_rlca(),
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Instruction::RLD => self.execute_rld(),
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Instruction::RR(target, opt_copy) => self.execute_rr(target, opt_copy),
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Instruction::RRA => self.execute_rra(),
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Instruction::RRC(target, opt_copy) => self.execute_rrc(target, opt_copy),
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Instruction::RRCA => self.execute_rrca(),
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Instruction::RRD => self.execute_rrd(),
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Instruction::RST(addr) => self.execute_rst(addr),
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Instruction::SBCa(target) => self.execute_sbca(target),
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Instruction::SBC16(dest_pair, src_pair) => self.execute_sbc16(dest_pair, src_pair),
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Instruction::SCF => self.execute_scf(),
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Instruction::SET(bit, target, opt_copy) => self.execute_set(bit, target, opt_copy),
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Instruction::SLA(target, opt_copy) => self.execute_sla(target, opt_copy),
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Instruction::SLL(target, opt_copy) => self.execute_sll(target, opt_copy),
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Instruction::SRA(target, opt_copy) => self.execute_sra(target, opt_copy),
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Instruction::SRL(target, opt_copy) => self.execute_srl(target, opt_copy),
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Instruction::SUB(target) => self.execute_sub(target),
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Instruction::XOR(target) => self.execute_xor(target),
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_ => {
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Err(Error::new(format!("{}: unimplemented instruction: {:?}", DEV_NAME, self.decoder.instruction)))
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}
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}
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}
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fn execute_adca(&mut self, target: Target) -> Result<(), Error> {
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let src = self.get_target_value(target)?;
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let acc = self.get_register_value(Register::A);
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let (result1, carry1, overflow1, half_carry1) = add_bytes(acc, self.get_flag(Flags::Carry) as u8);
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let (result2, carry2, overflow2, half_carry2) = add_bytes(result1, src);
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self.set_arithmetic_op_flags(result2 as u16, Size::Byte, false, carry1 | carry2, overflow1 ^ overflow2, half_carry1 | half_carry2);
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self.set_register_value(Register::A, result2);
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Ok(())
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}
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fn execute_adc16(&mut self, dest_pair: RegisterPair, src_pair: RegisterPair) -> Result<(), Error> {
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let src = self.get_register_pair_value(src_pair);
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let dest = self.get_register_pair_value(dest_pair);
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let (result1, carry1, overflow1, half_carry1) = add_words(dest, src);
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let (result2, carry2, overflow2, half_carry2) = add_words(result1, self.get_flag(Flags::Carry) as u16);
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self.set_arithmetic_op_flags(result2, Size::Word, false, carry1 | carry2, overflow1 ^ overflow2, half_carry1 | half_carry2);
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self.set_register_pair_value(dest_pair, result2);
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Ok(())
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}
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fn execute_adda(&mut self, target: Target) -> Result<(), Error> {
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let src = self.get_target_value(target)?;
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let acc = self.get_register_value(Register::A);
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let (result, carry, overflow, half_carry) = add_bytes(acc, src);
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self.set_arithmetic_op_flags(result as u16, Size::Byte, false, carry, overflow, half_carry);
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self.set_register_value(Register::A, result);
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Ok(())
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}
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fn execute_add16(&mut self, dest_pair: RegisterPair, src_pair: RegisterPair) -> Result<(), Error> {
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let src = self.get_register_pair_value(src_pair);
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let dest = self.get_register_pair_value(dest_pair);
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let (result, carry, _, half_carry) = add_words(dest, src);
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self.set_flag(Flags::AddSubtract, false);
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self.set_flag(Flags::Carry, carry);
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self.set_flag(Flags::HalfCarry, half_carry);
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self.set_register_pair_value(dest_pair, result);
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Ok(())
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}
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fn execute_and(&mut self, target: Target) -> Result<(), Error> {
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let acc = self.get_register_value(Register::A);
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let value = self.get_target_value(target)?;
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let result = acc & value;
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self.set_register_value(Register::A, result);
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self.set_logic_op_flags(result, false, true);
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Ok(())
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}
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fn execute_bit(&mut self, bit: u8, target: Target) -> Result<(), Error> {
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let value = self.get_target_value(target)?;
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let result = value & (1 << bit);
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self.set_flag(Flags::Zero, result == 0);
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self.set_flag(Flags::Sign, bit == 7 && result != 0);
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self.set_flag(Flags::Parity, result == 0);
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self.set_flag(Flags::AddSubtract, false);
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self.set_flag(Flags::HalfCarry, true);
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Ok(())
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}
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fn execute_call(&mut self, addr: u16) -> Result<(), Error> {
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self.push_word(self.decoder.end)?;
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self.state.pc = addr;
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Ok(())
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}
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fn execute_callcc(&mut self, cond: Condition, addr: u16) -> Result<(), Error> {
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if self.get_current_condition(cond) {
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self.executor.took_branch = true;
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self.push_word(self.decoder.end)?;
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self.state.pc = addr;
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}
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Ok(())
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}
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fn execute_ccf(&mut self) -> Result<(), Error> {
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self.set_flag(Flags::AddSubtract, false);
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self.set_flag(Flags::HalfCarry, self.get_flag(Flags::Carry));
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self.set_flag(Flags::Carry, !self.get_flag(Flags::Carry));
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Ok(())
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}
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fn execute_cp(&mut self, target: Target) -> Result<(), Error> {
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let src = self.get_target_value(target)?;
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let acc = self.get_register_value(Register::A);
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let (result, carry, overflow, half_carry) = sub_bytes(acc, src);
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self.set_arithmetic_op_flags(result as u16, Size::Byte, true, carry, overflow, half_carry);
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Ok(())
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}
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//Instruction::CPD => {
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//}
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//Instruction::CPDR => {
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//}
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//Instruction::CPI => {
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//}
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//Instruction::CPIR => {
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//}
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fn execute_cpl(&mut self) -> Result<(), Error> {
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let value = self.get_register_value(Register::A);
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self.set_register_value(Register::A, !value);
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self.set_flag(Flags::HalfCarry, true);
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self.set_flag(Flags::AddSubtract, true);
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Ok(())
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}
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fn execute_daa(&mut self) -> Result<(), Error> {
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// From <http://z80-heaven.wikidot.com/instructions-set:daa>
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// if the least significant four bits of A contain a non-BCD digit (i. e. it is
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// greater than 9) or the H flag is set, then $06 is added to the register. Then
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// the four most significant bits are checked. If this more significant digit
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// also happens to be greater than 9 or the C flag is set, then $60 is added.
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// From <http://www.z80.info/zip/z80-documented.pdf>
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//
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// CF | high | HF | low | diff
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// | nibble | | nibble |
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//----------------------------------
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// 0 | 0-9 | 0 | 0-9 | 00
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// 0 | 0-9 | 1 | 0-9 | 06
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// 0 | 0-8 | * | a-f | 06
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// 0 | a-f | 0 | 0-9 | 60
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// 1 | * | 0 | 0-9 | 60
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// 1 | * | 1 | 0-9 | 66
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// 1 | * | * | a-f | 66
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// 0 | 9-f | * | a-f | 66
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// 0 | a-f | 1 | 0-9 | 66
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let mut value = self.get_register_value(Register::A);
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let mut carry = false;
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let mut half_carry = false;
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if (value & 0x0F) > 9 || self.get_flag(Flags::HalfCarry) {
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let (result, _, _, half_carry1) = add_bytes(value, 6);
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value = result;
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half_carry = half_carry1;
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}
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if (value & 0xF0) > 0x90 || self.get_flag(Flags::Carry) {
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let (result, _, _, half_carry2) = add_bytes(value, 0x60);
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value = result;
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half_carry |= half_carry2;
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carry = true;
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}
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self.set_register_value(Register::A, value);
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self.set_numeric_flags(value as u16, Size::Byte);
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self.set_parity_flags(value);
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self.set_flag(Flags::HalfCarry, half_carry);
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self.set_flag(Flags::Carry, carry);
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Ok(())
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}
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fn execute_dec16(&mut self, regpair: RegisterPair) -> Result<(), Error> {
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let value = self.get_register_pair_value(regpair);
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let (result, _, _, _) = sub_words(value, 1);
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self.set_register_pair_value(regpair, result);
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Ok(())
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}
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fn execute_dec8(&mut self, target: Target) -> Result<(), Error> {
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let value = self.get_target_value(target)?;
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let (result, _, overflow, half_carry) = sub_bytes(value, 1);
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let carry = self.get_flag(Flags::Carry); // Preserve the carry bit, according to Z80 reference
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self.set_arithmetic_op_flags(result as u16, Size::Byte, true, carry, overflow, half_carry);
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self.set_target_value(target, result)?;
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Ok(())
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}
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fn execute_di(&mut self) -> Result<(), Error> {
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self.state.iff1 = false;
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self.state.iff2 = false;
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Ok(())
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}
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fn execute_djnz(&mut self, offset: i8) -> Result<(), Error> {
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let value = self.get_register_value(Register::B);
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let result = value.wrapping_sub(1);
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self.set_register_value(Register::B, result);
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if result != 0 {
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self.executor.took_branch = true;
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self.state.pc = self.state.pc.wrapping_add_signed(offset as i16);
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}
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Ok(())
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}
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fn execute_ei(&mut self) -> Result<(), Error> {
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self.state.iff1 = true;
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self.state.iff2 = true;
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Ok(())
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}
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fn execute_exx(&mut self) -> Result<(), Error> {
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for i in 0..6 {
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let (normal, shadow) = (self.state.reg[i], self.state.shadow_reg[i]);
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self.state.reg[i] = shadow;
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self.state.shadow_reg[i] = normal;
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}
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Ok(())
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}
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fn execute_ex_af_af(&mut self) -> Result<(), Error> {
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for i in 6..8 {
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let (normal, shadow) = (self.state.reg[i], self.state.shadow_reg[i]);
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self.state.reg[i] = shadow;
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self.state.shadow_reg[i] = normal;
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}
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Ok(())
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}
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fn execute_ex_hl_de(&mut self) -> Result<(), Error> {
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let (hl, de) = (self.get_register_pair_value(RegisterPair::HL), self.get_register_pair_value(RegisterPair::DE));
|
|
self.set_register_pair_value(RegisterPair::DE, hl);
|
|
self.set_register_pair_value(RegisterPair::HL, de);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_ex_sp(&mut self, regpair: RegisterPair) -> Result<(), Error> {
|
|
let reg_value = self.get_register_pair_value(regpair);
|
|
let sp = self.get_register_pair_value(RegisterPair::SP);
|
|
let sp_value = self.read_port_u16(sp)?;
|
|
self.set_register_pair_value(regpair, sp_value);
|
|
self.write_port_u16(sp, reg_value)?;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_halt(&mut self) -> Result<(), Error> {
|
|
self.state.status = Status::Halted;
|
|
self.state.pc -= 1;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_im(&mut self, mode: InterruptMode) -> Result<(), Error> {
|
|
self.state.im = mode;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_inc16(&mut self, regpair: RegisterPair) -> Result<(), Error> {
|
|
let value = self.get_register_pair_value(regpair);
|
|
|
|
let (result, _, _, _) = add_words(value, 1);
|
|
|
|
self.set_register_pair_value(regpair, result);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_inc8(&mut self, target: Target) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let (result, _, overflow, half_carry) = add_bytes(value, 1);
|
|
let carry = self.get_flag(Flags::Carry); // Preserve the carry bit, according to Z80 reference
|
|
self.set_arithmetic_op_flags(result as u16, Size::Byte, false, carry, overflow, half_carry);
|
|
|
|
self.set_target_value(target, result)?;
|
|
Ok(())
|
|
}
|
|
|
|
//Instruction::IND => {
|
|
//},
|
|
//Instruction::INDR => {
|
|
//}
|
|
|
|
fn execute_ini(&mut self) -> Result<(), Error> {
|
|
let b = self.get_register_value(Register::B);
|
|
let c = self.get_register_value(Register::C);
|
|
let value = self.read_ioport_value(b, c)?;
|
|
|
|
self.set_load_target_value(LoadTarget::IndirectRegByte(RegisterPair::HL), value as u16)?;
|
|
let hl = self.get_register_pair_value(RegisterPair::HL).wrapping_add(1);
|
|
self.set_register_pair_value(RegisterPair::HL, hl);
|
|
let b = self.get_register_value(Register::B).wrapping_sub(1);
|
|
self.set_register_value(Register::B, b);
|
|
Ok(())
|
|
}
|
|
|
|
//Instruction::INIR => {
|
|
//}
|
|
|
|
fn execute_inic(&mut self, reg: Register) -> Result<(), Error> {
|
|
let b = self.get_register_value(Register::B);
|
|
let c = self.get_register_value(Register::C);
|
|
let value = self.read_ioport_value(b, c)?;
|
|
|
|
self.set_register_value(reg, value);
|
|
self.set_numeric_flags(value as u16, Size::Byte);
|
|
self.set_parity_flags(value);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
Ok(())
|
|
}
|
|
|
|
//Instruction::INicz => {
|
|
//}
|
|
|
|
fn execute_inx(&mut self, n: u8) -> Result<(), Error> {
|
|
let a = self.get_register_value(Register::A);
|
|
let value = self.read_ioport_value(a, n)?;
|
|
self.set_register_value(Register::A, value);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_jp(&mut self, addr: u16) -> Result<(), Error> {
|
|
self.state.pc = addr;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_jp_indirect(&mut self, regpair: RegisterPair) -> Result<(), Error> {
|
|
let value = self.get_register_pair_value(regpair);
|
|
self.state.pc = value;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_jpcc(&mut self, cond: Condition, addr: u16) -> Result<(), Error> {
|
|
if self.get_current_condition(cond) {
|
|
self.executor.took_branch = true;
|
|
self.state.pc = addr;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_jr(&mut self, offset: i8) -> Result<(), Error> {
|
|
self.state.pc = self.state.pc.wrapping_add_signed(offset as i16);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_jrcc(&mut self, cond: Condition, offset: i8) -> Result<(), Error> {
|
|
if self.get_current_condition(cond) {
|
|
self.executor.took_branch = true;
|
|
self.state.pc = self.state.pc.wrapping_add_signed(offset as i16);
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_ld(&mut self, dest: LoadTarget, src: LoadTarget) -> Result<(), Error> {
|
|
let src_value = self.get_load_target_value(src)?;
|
|
self.set_load_target_value(dest, src_value)?;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_ldsr(&mut self, special_reg: SpecialRegister, dir: Direction) -> Result<(), Error> {
|
|
let addr = match special_reg {
|
|
SpecialRegister::I => &mut self.state.i,
|
|
SpecialRegister::R => &mut self.state.r,
|
|
};
|
|
|
|
match dir {
|
|
Direction::FromAcc => {
|
|
*addr = self.state.reg[Register::A as usize];
|
|
},
|
|
Direction::ToAcc => {
|
|
self.state.reg[Register::A as usize] = *addr;
|
|
let value = self.state.reg[Register::A as usize];
|
|
self.set_numeric_flags(value as u16, Size::Byte);
|
|
self.set_flag(Flags::Parity, self.state.iff2);
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
},
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_ldx(&mut self) -> Result<(), Error> {
|
|
let diff = if self.decoder.instruction == Instruction::LDI || self.decoder.instruction == Instruction::LDIR {
|
|
1
|
|
} else {
|
|
-1
|
|
};
|
|
|
|
let src_value = self.get_load_target_value(LoadTarget::IndirectRegByte(RegisterPair::HL))?;
|
|
self.set_load_target_value(LoadTarget::IndirectRegByte(RegisterPair::DE), src_value)?;
|
|
self.add_to_regpair(RegisterPair::DE, diff);
|
|
self.add_to_regpair(RegisterPair::HL, diff);
|
|
let count = self.add_to_regpair(RegisterPair::BC, -1);
|
|
let mask = (Flags::AddSubtract as u8) | (Flags::HalfCarry as u8) | (Flags::Parity as u8);
|
|
let parity = if count != 0 { Flags::Parity as u8 } else { 0 };
|
|
self.set_flags(mask, parity);
|
|
|
|
if (self.decoder.instruction == Instruction::LDIR || self.decoder.instruction == Instruction::LDDR)
|
|
&& count != 0
|
|
{
|
|
self.executor.took_branch = true;
|
|
self.state.pc -= 2;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_neg(&mut self) -> Result<(), Error> {
|
|
let acc = self.get_register_value(Register::A);
|
|
|
|
let (result, carry, overflow, half_carry) = sub_bytes(0, acc);
|
|
self.set_arithmetic_op_flags(result as u16, Size::Byte, true, carry, overflow, half_carry);
|
|
|
|
self.set_register_value(Register::A, result);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_or(&mut self, target: Target) -> Result<(), Error> {
|
|
let acc = self.get_register_value(Register::A);
|
|
let value = self.get_target_value(target)?;
|
|
let result = acc | value;
|
|
self.set_register_value(Register::A, result);
|
|
self.set_logic_op_flags(result, false, false);
|
|
Ok(())
|
|
}
|
|
|
|
//Instruction::OTDR => {
|
|
//},
|
|
//Instruction::OTIR => {
|
|
//},
|
|
//Instruction::OUTD => {
|
|
//},
|
|
//Instruction::OUTI => {
|
|
//}
|
|
|
|
fn execute_outic(&mut self, reg: Register) -> Result<(), Error> {
|
|
let b = self.get_register_value(Register::B);
|
|
let c = self.get_register_value(Register::C);
|
|
let value = self.get_register_value(reg);
|
|
self.write_ioport_value(b, c, value)?;
|
|
Ok(())
|
|
}
|
|
|
|
//Instruction::OUTicz => {
|
|
//}
|
|
|
|
fn execute_outx(&mut self, n: u8) -> Result<(), Error> {
|
|
let a = self.get_register_value(Register::A);
|
|
let value = self.get_register_value(Register::A);
|
|
self.write_ioport_value(a, n, value)?;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_pop(&mut self, regpair: RegisterPair) -> Result<(), Error> {
|
|
let value = self.pop_word()?;
|
|
self.set_register_pair_value(regpair, value);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_push(&mut self, regpair: RegisterPair) -> Result<(), Error> {
|
|
let value = self.get_register_pair_value(regpair);
|
|
self.push_word(value)?;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_res(&mut self, bit: u8, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let mut value = self.get_target_value(target)?;
|
|
value &= !(1 << bit);
|
|
self.set_target_value(target, value)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, value)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_ret(&mut self) -> Result<(), Error> {
|
|
self.state.pc = self.pop_word()?;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_reti(&mut self) -> Result<(), Error> {
|
|
self.state.pc = self.pop_word()?;
|
|
self.state.iff1 = self.state.iff2;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_retn(&mut self) -> Result<(), Error> {
|
|
self.state.pc = self.pop_word()?;
|
|
self.state.iff1 = self.state.iff2;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_retcc(&mut self, cond: Condition) -> Result<(), Error> {
|
|
if self.get_current_condition(cond) {
|
|
self.executor.took_branch = true;
|
|
self.state.pc = self.pop_word()?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rl(&mut self, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let (result, out_bit) = self.rotate_left(value, RotateType::Bit9);
|
|
self.set_logic_op_flags(result, out_bit, false);
|
|
self.set_target_value(target, result)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, result)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rla(&mut self) -> Result<(), Error> {
|
|
let value = self.get_register_value(Register::A);
|
|
let (result, out_bit) = self.rotate_left(value, RotateType::Bit9);
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
self.set_flag(Flags::Carry, out_bit);
|
|
self.set_register_value(Register::A, result);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rlc(&mut self, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let (result, out_bit) = self.rotate_left(value, RotateType::Bit8);
|
|
self.set_logic_op_flags(result, out_bit, false);
|
|
self.set_target_value(target, result)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, result)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rlca(&mut self) -> Result<(), Error> {
|
|
let value = self.get_register_value(Register::A);
|
|
let (result, out_bit) = self.rotate_left(value, RotateType::Bit8);
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
self.set_flag(Flags::Carry, out_bit);
|
|
self.set_register_value(Register::A, result);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rld(&mut self) -> Result<(), Error> {
|
|
let a = self.get_register_value(Register::A);
|
|
let mem = self.get_load_target_value(LoadTarget::IndirectRegByte(RegisterPair::HL))? as u8;
|
|
|
|
let lower_a = a & 0x0F;
|
|
let a = (a & 0xF0) | (mem >> 4);
|
|
let mem = (mem << 4) | lower_a;
|
|
|
|
self.set_register_value(Register::A, a);
|
|
self.set_load_target_value(LoadTarget::IndirectRegByte(RegisterPair::HL), mem as u16)?;
|
|
|
|
self.set_numeric_flags(a as u16, Size::Byte);
|
|
self.set_parity_flags(a);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rr(&mut self, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let (result, out_bit) = self.rotate_right(value, RotateType::Bit9);
|
|
self.set_logic_op_flags(result, out_bit, false);
|
|
self.set_target_value(target, result)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, result)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rra(&mut self) -> Result<(), Error> {
|
|
let value = self.get_register_value(Register::A);
|
|
let (result, out_bit) = self.rotate_right(value, RotateType::Bit9);
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
self.set_flag(Flags::Carry, out_bit);
|
|
self.set_register_value(Register::A, result);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rrc(&mut self, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let (result, out_bit) = self.rotate_right(value, RotateType::Bit8);
|
|
self.set_logic_op_flags(result, out_bit, false);
|
|
self.set_target_value(target, result)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, result)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rrca(&mut self) -> Result<(), Error> {
|
|
let value = self.get_register_value(Register::A);
|
|
let (result, out_bit) = self.rotate_right(value, RotateType::Bit8);
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
self.set_flag(Flags::Carry, out_bit);
|
|
self.set_register_value(Register::A, result);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rrd(&mut self) -> Result<(), Error> {
|
|
let a = self.get_register_value(Register::A);
|
|
let mem = self.get_load_target_value(LoadTarget::IndirectRegByte(RegisterPair::HL))? as u8;
|
|
|
|
let lower_mem = mem & 0x0F;
|
|
let mem = (a << 4) | (mem >> 4);
|
|
let a = (a & 0xF0) | lower_mem;
|
|
|
|
self.set_register_value(Register::A, a);
|
|
self.set_load_target_value(LoadTarget::IndirectRegByte(RegisterPair::HL), mem as u16)?;
|
|
|
|
self.set_numeric_flags(a as u16, Size::Byte);
|
|
self.set_parity_flags(a);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_rst(&mut self, addr: u8) -> Result<(), Error> {
|
|
self.push_word(self.decoder.end)?;
|
|
self.state.pc = addr as u16;
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_sbca(&mut self, target: Target) -> Result<(), Error> {
|
|
let src = self.get_target_value(target)?;
|
|
let acc = self.get_register_value(Register::A);
|
|
|
|
let (result1, carry1, overflow1, half_carry1) = sub_bytes(acc, src);
|
|
let (result2, carry2, overflow2, half_carry2) = sub_bytes(result1, self.get_flag(Flags::Carry) as u8);
|
|
self.set_arithmetic_op_flags(result2 as u16, Size::Byte, true, carry1 | carry2, overflow1 ^ overflow2, half_carry1 | half_carry2);
|
|
|
|
self.set_register_value(Register::A, result2);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_sbc16(&mut self, dest_pair: RegisterPair, src_pair: RegisterPair) -> Result<(), Error> {
|
|
let src = self.get_register_pair_value(src_pair);
|
|
let dest = self.get_register_pair_value(dest_pair);
|
|
|
|
let (result1, carry1, overflow1, half_carry1) = sub_words(dest, self.get_flag(Flags::Carry) as u16);
|
|
let (result2, carry2, overflow2, half_carry2) = sub_words(result1, src);
|
|
self.set_arithmetic_op_flags(result2, Size::Word, true, carry1 | carry2, overflow1 ^ overflow2, half_carry1 | half_carry2);
|
|
|
|
self.set_register_pair_value(dest_pair, result2);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_scf(&mut self) -> Result<(), Error> {
|
|
self.set_flag(Flags::AddSubtract, false);
|
|
self.set_flag(Flags::HalfCarry, false);
|
|
self.set_flag(Flags::Carry, true);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_set(&mut self, bit: u8, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let mut value = self.get_target_value(target)?;
|
|
value |= 1 << bit;
|
|
self.set_target_value(target, value)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, value)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_sla(&mut self, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let out_bit = get_msb(value as u16, Size::Byte);
|
|
let result = value << 1;
|
|
self.set_logic_op_flags(result, out_bit, false);
|
|
self.set_target_value(target, result)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, result)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_sll(&mut self, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let out_bit = get_msb(value as u16, Size::Byte);
|
|
let result = (value << 1) | 0x01;
|
|
self.set_logic_op_flags(result, out_bit, false);
|
|
self.set_target_value(target, result)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, result)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_sra(&mut self, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let out_bit = (value & 0x01) != 0;
|
|
let msb_mask = if get_msb(value as u16, Size::Byte) { 0x80 } else { 0 };
|
|
let result = (value >> 1) | msb_mask;
|
|
self.set_logic_op_flags(result, out_bit, false);
|
|
self.set_target_value(target, result)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, result)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_srl(&mut self, target: Target, opt_copy: UndocumentedCopy) -> Result<(), Error> {
|
|
let value = self.get_target_value(target)?;
|
|
let out_bit = (value & 0x01) != 0;
|
|
let result = value >> 1;
|
|
self.set_logic_op_flags(result, out_bit, false);
|
|
self.set_target_value(target, result)?;
|
|
if let Some(target) = opt_copy {
|
|
self.set_target_value(target, result)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_sub(&mut self, target: Target) -> Result<(), Error> {
|
|
let src = self.get_target_value(target)?;
|
|
let acc = self.get_register_value(Register::A);
|
|
|
|
let (result, carry, overflow, half_carry) = sub_bytes(acc, src);
|
|
self.set_arithmetic_op_flags(result as u16, Size::Byte, true, carry, overflow, half_carry);
|
|
|
|
self.set_register_value(Register::A, result);
|
|
Ok(())
|
|
}
|
|
|
|
fn execute_xor(&mut self, target: Target) -> Result<(), Error> {
|
|
let acc = self.get_register_value(Register::A);
|
|
let value = self.get_target_value(target)?;
|
|
let result = acc ^ value;
|
|
self.set_register_value(Register::A, result);
|
|
self.set_logic_op_flags(result, false, false);
|
|
Ok(())
|
|
}
|
|
|
|
|
|
fn rotate_left(&mut self, mut value: u8, rtype: RotateType) -> (u8, bool) {
|
|
let out_bit = get_msb(value as u16, Size::Byte);
|
|
|
|
let in_bit = match rtype {
|
|
RotateType::Bit9 => self.get_flag(Flags::Carry),
|
|
RotateType::Bit8 => out_bit,
|
|
};
|
|
|
|
value <<= 1;
|
|
value |= in_bit as u8;
|
|
(value, out_bit)
|
|
}
|
|
|
|
fn rotate_right(&mut self, mut value: u8, rtype: RotateType) -> (u8, bool) {
|
|
let out_bit = (value & 0x01) != 0;
|
|
|
|
let in_bit = match rtype {
|
|
RotateType::Bit9 => self.get_flag(Flags::Carry),
|
|
RotateType::Bit8 => out_bit,
|
|
};
|
|
|
|
value >>= 1;
|
|
value |= if in_bit { 0x80 } else { 0 };
|
|
(value, out_bit)
|
|
}
|
|
|
|
fn add_to_regpair(&mut self, regpair: RegisterPair, value: i16) -> u16 {
|
|
let addr = match regpair {
|
|
RegisterPair::BC => &mut self.state.reg[0..2],
|
|
RegisterPair::DE => &mut self.state.reg[2..4],
|
|
RegisterPair::HL => &mut self.state.reg[4..6],
|
|
RegisterPair::AF => &mut self.state.reg[6..8],
|
|
_ => panic!("RegPair is not supported by inc/dec"),
|
|
};
|
|
|
|
let result = (read_beu16(addr) as i16).wrapping_add(value) as u16;
|
|
write_beu16(addr, result);
|
|
result
|
|
}
|
|
|
|
|
|
|
|
fn push_word(&mut self, value: u16) -> Result<(), Error> {
|
|
self.state.sp = self.state.sp.wrapping_sub(1);
|
|
self.write_port_u8(self.state.sp, (value >> 8) as u8)?;
|
|
self.state.sp = self.state.sp.wrapping_sub(1);
|
|
self.write_port_u8(self.state.sp, (value & 0x00FF) as u8)?;
|
|
Ok(())
|
|
}
|
|
|
|
fn pop_word(&mut self) -> Result<u16, Error> {
|
|
let mut value;
|
|
value = self.read_port_u8(self.state.sp)? as u16;
|
|
self.state.sp = self.state.sp.wrapping_add(1);
|
|
value |= (self.read_port_u8(self.state.sp)? as u16) << 8;
|
|
self.state.sp = self.state.sp.wrapping_add(1);
|
|
Ok(value)
|
|
}
|
|
|
|
fn get_load_target_value(&mut self, target: LoadTarget) -> Result<u16, Error> {
|
|
let value = match target {
|
|
LoadTarget::DirectRegByte(reg) => self.get_register_value(reg) as u16,
|
|
LoadTarget::DirectRegHalfByte(reg) => self.get_index_register_half_value(reg) as u16,
|
|
LoadTarget::DirectRegWord(regpair) => self.get_register_pair_value(regpair),
|
|
LoadTarget::IndirectRegByte(regpair) => {
|
|
let addr = self.get_register_pair_value(regpair);
|
|
self.read_port_u8(addr)? as u16
|
|
},
|
|
LoadTarget::IndirectOffsetByte(index_reg, offset) => {
|
|
let addr = self.get_index_register_value(index_reg);
|
|
self.read_port_u8((addr as i16).wrapping_add(offset as i16) as u16)? as u16
|
|
},
|
|
LoadTarget::IndirectRegWord(regpair) => {
|
|
let addr = self.get_register_pair_value(regpair);
|
|
self.read_port_u16(addr)?
|
|
},
|
|
LoadTarget::IndirectByte(addr) => {
|
|
self.read_port_u8(addr)? as u16
|
|
},
|
|
LoadTarget::IndirectWord(addr) => {
|
|
self.read_port_u16(addr)?
|
|
},
|
|
LoadTarget::ImmediateByte(data) => data as u16,
|
|
LoadTarget::ImmediateWord(data) => data,
|
|
_ => panic!("Unsupported LoadTarget for set"),
|
|
};
|
|
Ok(value)
|
|
}
|
|
|
|
fn set_load_target_value(&mut self, target: LoadTarget, value: u16) -> Result<(), Error> {
|
|
match target {
|
|
LoadTarget::DirectRegByte(reg) => self.set_register_value(reg, value as u8),
|
|
LoadTarget::DirectRegHalfByte(reg) => self.set_index_register_half_value(reg, value as u8),
|
|
LoadTarget::DirectRegWord(regpair) => self.set_register_pair_value(regpair, value),
|
|
LoadTarget::IndirectRegByte(regpair) => {
|
|
let addr = self.get_register_pair_value(regpair);
|
|
self.write_port_u8(addr, value as u8)?;
|
|
},
|
|
LoadTarget::IndirectOffsetByte(index_reg, offset) => {
|
|
let addr = self.get_index_register_value(index_reg);
|
|
self.write_port_u8((addr as i16).wrapping_add(offset as i16) as u16, value as u8)?;
|
|
},
|
|
LoadTarget::IndirectRegWord(regpair) => {
|
|
let addr = self.get_register_pair_value(regpair);
|
|
self.write_port_u16(addr, value)?;
|
|
},
|
|
LoadTarget::IndirectByte(addr) => {
|
|
self.write_port_u8(addr, value as u8)?;
|
|
},
|
|
LoadTarget::IndirectWord(addr) => {
|
|
self.write_port_u16(addr, value)?;
|
|
},
|
|
_ => panic!("Unsupported LoadTarget for set: {:?}", target),
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn get_target_value(&mut self, target: Target) -> Result<u8, Error> {
|
|
match target {
|
|
Target::DirectReg(reg) => Ok(self.get_register_value(reg)),
|
|
Target::DirectRegHalf(reg) => Ok(self.get_index_register_half_value(reg)),
|
|
Target::IndirectReg(regpair) => {
|
|
let addr = self.get_register_pair_value(regpair);
|
|
Ok(self.read_port_u8(addr)?)
|
|
},
|
|
Target::IndirectOffset(reg, offset) => {
|
|
let addr = self.get_index_register_value(reg).wrapping_add_signed(offset as i16);
|
|
Ok(self.read_port_u8(addr)?)
|
|
},
|
|
Target::Immediate(data) => Ok(data),
|
|
}
|
|
}
|
|
|
|
fn set_target_value(&mut self, target: Target, value: u8) -> Result<(), Error> {
|
|
match target {
|
|
Target::DirectReg(reg) => self.set_register_value(reg, value),
|
|
Target::DirectRegHalf(reg) => self.set_index_register_half_value(reg, value),
|
|
Target::IndirectReg(regpair) => {
|
|
let addr = self.get_register_pair_value(regpair);
|
|
self.write_port_u8(addr, value)?;
|
|
},
|
|
Target::IndirectOffset(reg, offset) => {
|
|
let addr = self.get_index_register_value(reg).wrapping_add_signed(offset as i16);
|
|
self.write_port_u8(addr, value)?;
|
|
},
|
|
_ => panic!("Unsupported LoadTarget for set"),
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn increment_refresh(&mut self, count: u8) {
|
|
self.state.r = (self.state.r & 0x80) | ((self.state.r + count) & 0x7F);
|
|
}
|
|
|
|
fn read_port_u8(&mut self, addr: u16) -> Result<u8, Error> {
|
|
self.increment_refresh(1);
|
|
self.port.read_u8(self.executor.current_clock, addr as Address)
|
|
}
|
|
|
|
fn write_port_u8(&mut self, addr: u16, value: u8) -> Result<(), Error> {
|
|
self.increment_refresh(1);
|
|
self.port.write_u8(self.executor.current_clock, addr as Address, value)
|
|
}
|
|
|
|
fn read_port_u16(&mut self, addr: u16) -> Result<u16, Error> {
|
|
self.increment_refresh(2);
|
|
self.port.read_leu16(self.executor.current_clock, addr as Address)
|
|
}
|
|
|
|
fn write_port_u16(&mut self, addr: u16, value: u16) -> Result<(), Error> {
|
|
self.increment_refresh(2);
|
|
self.port.write_leu16(self.executor.current_clock, addr as Address, value)
|
|
}
|
|
|
|
fn read_ioport_value(&mut self, upper: u8, lower: u8) -> Result<u8, Error> {
|
|
let addr = ((upper as Address) << 8) | (lower as Address);
|
|
if let Some(io) = self.ioport.as_mut() {
|
|
Ok(io.read_u8(self.executor.current_clock, addr)?)
|
|
} else {
|
|
Ok(0)
|
|
}
|
|
}
|
|
|
|
fn write_ioport_value(&mut self, upper: u8, lower: u8, value: u8) -> Result<(), Error> {
|
|
let addr = ((upper as Address) << 8) | (lower as Address);
|
|
if let Some(io) = self.ioport.as_mut() {
|
|
io.write_u8(self.executor.current_clock, addr, value)?
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
|
|
fn get_register_value(&mut self, reg: Register) -> u8 {
|
|
self.state.reg[reg as usize]
|
|
}
|
|
|
|
fn set_register_value(&mut self, reg: Register, value: u8) {
|
|
self.state.reg[reg as usize] = value;
|
|
}
|
|
|
|
fn get_index_register_half_value(&mut self, reg: IndexRegisterHalf) -> u8 {
|
|
match reg {
|
|
IndexRegisterHalf::IXH => (self.state.ix >> 8) as u8,
|
|
IndexRegisterHalf::IXL => (self.state.ix & 0x00FF) as u8,
|
|
IndexRegisterHalf::IYH => (self.state.iy >> 8) as u8,
|
|
IndexRegisterHalf::IYL => (self.state.iy & 0x00FF) as u8,
|
|
}
|
|
}
|
|
|
|
fn set_index_register_half_value(&mut self, reg: IndexRegisterHalf, value: u8) {
|
|
match reg {
|
|
IndexRegisterHalf::IXH => { self.state.ix = (self.state.ix & 0x00FF) | (value as u16) << 8; },
|
|
IndexRegisterHalf::IXL => { self.state.ix = (self.state.ix & 0xFF00) | value as u16; },
|
|
IndexRegisterHalf::IYH => { self.state.iy = (self.state.iy & 0x00FF) | (value as u16) << 8; },
|
|
IndexRegisterHalf::IYL => { self.state.iy = (self.state.iy & 0xFF00) | value as u16; },
|
|
}
|
|
}
|
|
|
|
fn get_register_pair_value(&mut self, regpair: RegisterPair) -> u16 {
|
|
match regpair {
|
|
RegisterPair::BC => read_beu16(&self.state.reg[0..2]),
|
|
RegisterPair::DE => read_beu16(&self.state.reg[2..4]),
|
|
RegisterPair::HL => read_beu16(&self.state.reg[4..6]),
|
|
RegisterPair::AF => read_beu16(&self.state.reg[6..8]),
|
|
RegisterPair::SP => self.state.sp,
|
|
RegisterPair::IX => self.state.ix,
|
|
RegisterPair::IY => self.state.iy,
|
|
}
|
|
}
|
|
|
|
fn set_register_pair_value(&mut self, regpair: RegisterPair, value: u16) {
|
|
match regpair {
|
|
RegisterPair::BC => { write_beu16(&mut self.state.reg[0..2], value); },
|
|
RegisterPair::DE => { write_beu16(&mut self.state.reg[2..4], value); },
|
|
RegisterPair::HL => { write_beu16(&mut self.state.reg[4..6], value); },
|
|
RegisterPair::AF => { write_beu16(&mut self.state.reg[6..8], value); },
|
|
RegisterPair::SP => { self.state.sp = value; },
|
|
RegisterPair::IX => { self.state.ix = value; },
|
|
RegisterPair::IY => { self.state.iy = value; },
|
|
}
|
|
}
|
|
|
|
fn get_index_register_value(&mut self, reg: IndexRegister) -> u16 {
|
|
match reg {
|
|
IndexRegister::IX => self.state.ix,
|
|
IndexRegister::IY => self.state.iy,
|
|
}
|
|
}
|
|
|
|
fn get_current_condition(&mut self, cond: Condition) -> bool {
|
|
match cond {
|
|
Condition::NotZero => !self.get_flag(Flags::Zero),
|
|
Condition::Zero => self.get_flag(Flags::Zero),
|
|
Condition::NotCarry => !self.get_flag(Flags::Carry),
|
|
Condition::Carry => self.get_flag(Flags::Carry),
|
|
Condition::ParityOdd => !self.get_flag(Flags::Parity),
|
|
Condition::ParityEven => self.get_flag(Flags::Parity),
|
|
Condition::Positive => !self.get_flag(Flags::Sign),
|
|
Condition::Negative => self.get_flag(Flags::Sign),
|
|
}
|
|
}
|
|
|
|
fn set_numeric_flags(&mut self, value: u16, size: Size) {
|
|
let sign = if get_msb(value, size) { Flags::Sign as u8 } else { 0 };
|
|
let zero = if value == 0 { Flags::Zero as u8 } else { 0 };
|
|
self.set_flags(FLAGS_NUMERIC, sign | zero);
|
|
}
|
|
|
|
fn set_parity_flags(&mut self, value: u8) {
|
|
let parity = if (value.count_ones() & 0x01) == 0 { Flags::Parity as u8 } else { 0 };
|
|
self.set_flags(Flags::Parity as u8, parity);
|
|
}
|
|
|
|
fn set_arithmetic_op_flags(&mut self, value: u16, size: Size, addsub: bool, carry: bool, overflow: bool, half_carry: bool) {
|
|
self.state.reg[Register::F as usize] = 0;
|
|
self.set_numeric_flags(value, size);
|
|
|
|
let addsub_flag = if addsub { Flags::AddSubtract as u8 } else { 0 };
|
|
let overflow_flag = if overflow { Flags::Parity as u8 } else { 0 };
|
|
let carry_flag = if carry { Flags::Carry as u8 } else { 0 };
|
|
let half_carry_flag = if half_carry { Flags::HalfCarry as u8 } else { 0 };
|
|
self.set_flags(FLAGS_ARITHMETIC, addsub_flag | overflow_flag | carry_flag | half_carry_flag);
|
|
}
|
|
|
|
fn set_logic_op_flags(&mut self, value: u8, carry: bool, half_carry: bool) {
|
|
self.state.reg[Register::F as usize] = 0;
|
|
self.set_numeric_flags(value as u16, Size::Byte);
|
|
self.set_parity_flags(value);
|
|
|
|
let carry_flag = if carry { Flags::Carry as u8 } else { 0 };
|
|
let half_carry_flag = if half_carry { Flags::HalfCarry as u8 } else { 0 };
|
|
self.set_flags(FLAGS_CARRY_HALF_CARRY, carry_flag | half_carry_flag);
|
|
}
|
|
|
|
fn get_flag(&self, flag: Flags) -> bool {
|
|
self.get_flags() & (flag as u8) != 0
|
|
}
|
|
|
|
fn set_flag(&mut self, flag: Flags, value: bool) {
|
|
self.state.reg[Register::F as usize] &= !(flag as u8);
|
|
if value {
|
|
self.state.reg[Register::F as usize] |= flag as u8;
|
|
}
|
|
}
|
|
|
|
fn get_flags(&self) -> u8 {
|
|
self.state.reg[Register::F as usize]
|
|
}
|
|
|
|
fn set_flags(&mut self, mask: u8, values: u8) {
|
|
self.state.reg[Register::F as usize] = (self.state.reg[Register::F as usize] & !mask) | values;
|
|
}
|
|
}
|
|
|
|
fn add_bytes(operand1: u8, operand2: u8) -> (u8, bool, bool, bool) {
|
|
let (result, carry) = operand1.overflowing_add(operand2);
|
|
let overflow = (operand1 & 0x80) == (operand2 & 0x80) && (operand1 & 0x80) != (result & 0x80);
|
|
let half_carry = (operand1 & 0x0F) + (operand2 & 0x0F) >= 0x10;
|
|
(result, carry, overflow, half_carry)
|
|
}
|
|
|
|
fn add_words(operand1: u16, operand2: u16) -> (u16, bool, bool, bool) {
|
|
let (result, carry) = operand1.overflowing_add(operand2);
|
|
let overflow = (operand1 & 0x8000) == (operand2 & 0x8000) && (operand1 & 0x8000) != (result & 0x8000);
|
|
let half_carry = (operand1 & 0x0FFF) + (operand2 & 0x0FFF) >= 0x1000;
|
|
(result, carry, overflow, half_carry)
|
|
}
|
|
|
|
fn sub_bytes(operand1: u8, operand2: u8) -> (u8, bool, bool, bool) {
|
|
let (result, carry) = operand1.overflowing_sub(operand2);
|
|
let overflow = (operand1 & 0x80) != (operand2 & 0x80) && (operand1 & 0x80) != (result & 0x80);
|
|
let half_carry = (operand1 & 0x0F) < (operand2 & 0x0F);
|
|
(result, carry, overflow, half_carry)
|
|
}
|
|
|
|
fn sub_words(operand1: u16, operand2: u16) -> (u16, bool, bool, bool) {
|
|
let (result, carry) = operand1.overflowing_sub(operand2);
|
|
let overflow = (operand1 & 0x8000) != (operand2 & 0x8000) && (operand1 & 0x8000) != (result & 0x8000);
|
|
let half_carry = (operand1 & 0x0FFF) < (operand2 & 0x0FFF);
|
|
(result, carry, overflow, half_carry)
|
|
}
|
|
|
|
fn get_msb(value: u16, size: Size) -> bool {
|
|
match size {
|
|
Size::Byte => (value & 0x0080) != 0,
|
|
Size::Word => (value & 0x8000) != 0,
|
|
}
|
|
}
|
|
|