302 lines
9.6 KiB
Rust
302 lines
9.6 KiB
Rust
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use moa_core::Error;
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use crate::instructions::{Instruction, Target, LoadTarget, RegisterPair};
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pub enum Z80InstructionCycles {
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Single(u16),
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Branch {
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taken: u16,
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not_taken: u16
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},
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Repeating {
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repeating: u16,
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terminating: u16,
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},
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}
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impl Z80InstructionCycles {
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pub fn calculate_cycles(&self, took_branch: bool) -> u16 {
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match self {
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Z80InstructionCycles::Single(cycles) => *cycles,
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Z80InstructionCycles::Branch { taken, not_taken } => if took_branch { *taken } else { *not_taken },
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Z80InstructionCycles::Repeating { repeating, terminating } => if took_branch { *repeating } else { *terminating },
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}
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}
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pub fn from_instruction(instruction: &Instruction, extra: u16) -> Result<Z80InstructionCycles, Error> {
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let cycles = match instruction {
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Instruction::ADCa(target) |
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Instruction::ADDa(target) |
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Instruction::AND(target) |
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Instruction::CP(target) |
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Instruction::SBCa(target) |
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Instruction::SUB(target) |
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Instruction::OR(target) |
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Instruction::XOR(target) => {
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match target {
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Target::DirectReg(_) |
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Target::DirectRegHalf(_) => 4,
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Target::IndirectReg(_) => 7,
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Target::Immediate(_) => 7,
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Target::IndirectOffset(_, _) => 19,
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}
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},
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Instruction::ADC16(_, _) |
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Instruction::SBC16(_, _) => 15,
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Instruction::ADD16(dest_pair, _) => {
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if !dest_pair.is_index_reg() {
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11
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} else {
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15
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}
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},
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Instruction::BIT(_, target) => {
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match target {
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Target::DirectReg(_) => 8,
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Target::IndirectReg(_) => 12,
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Target::IndirectOffset(_, _) => 20,
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_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
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}
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},
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Instruction::CALL(_) => 17,
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Instruction::CALLcc(_, _) => {
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return Ok(Z80InstructionCycles::Branch {
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taken: 17 + extra,
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not_taken: 10 + extra,
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});
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},
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Instruction::CCF => 4,
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Instruction::CPD |
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Instruction::CPI |
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Instruction::IND |
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Instruction::INI |
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Instruction::LDD |
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Instruction::LDI |
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Instruction::OUTD |
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Instruction::OUTI => 16,
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Instruction::CPDR |
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Instruction::CPIR |
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Instruction::INDR |
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Instruction::INIR |
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Instruction::LDDR |
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Instruction::LDIR |
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Instruction::OTDR |
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Instruction::OTIR => {
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return Ok(Z80InstructionCycles::Repeating {
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repeating: 21 + extra,
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terminating: 16 + extra,
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})
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},
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Instruction::CPL => 4,
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Instruction::DAA => 4,
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Instruction::DEC8(target) |
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Instruction::INC8(target) => {
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match target {
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Target::DirectReg(_) |
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Target::DirectRegHalf(_) => 4,
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Target::IndirectReg(_) => 11,
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Target::IndirectOffset(_, _) => 23,
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_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
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}
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},
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Instruction::DEC16(regpair) |
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Instruction::INC16(regpair) => {
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if !regpair.is_index_reg() {
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6
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} else {
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10
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}
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},
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Instruction::DI |
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Instruction::EI => 4,
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Instruction::DJNZ(_) => {
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return Ok(Z80InstructionCycles::Branch {
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taken: 13 + extra,
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not_taken: 8 + extra,
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});
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},
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Instruction::EXX => 4,
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Instruction::EXafaf => 4,
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Instruction::EXhlde => 4,
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Instruction::EXsp(regpair) => {
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if !regpair.is_index_reg() {
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19
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} else {
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23
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}
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},
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Instruction::HALT => 4,
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Instruction::IM(_) => 8,
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Instruction::INic(_) |
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Instruction::INicz |
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Instruction::OUTic(_) |
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Instruction::OUTicz => 12,
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Instruction::INx(_) |
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Instruction::OUTx(_) => 11,
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Instruction::JP(_) => 10,
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Instruction::JR(_) => 12,
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Instruction::JPIndirect(regpair) => {
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if !regpair.is_index_reg() {
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4
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} else {
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8
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}
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},
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Instruction::JPcc(_, _) => 10,
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Instruction::JRcc(_, _) => {
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return Ok(Z80InstructionCycles::Branch {
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taken: 12 + extra,
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not_taken: 7 + extra,
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});
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},
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Instruction::LD(dest, src) => {
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match (dest, src) {
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// 8-Bit Operations
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(LoadTarget::DirectRegByte(_), LoadTarget::DirectRegByte(_)) => 4,
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(LoadTarget::DirectRegHalfByte(_), LoadTarget::DirectRegByte(_)) |
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(LoadTarget::DirectRegByte(_), LoadTarget::DirectRegHalfByte(_)) |
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(LoadTarget::DirectRegHalfByte(_), LoadTarget::DirectRegHalfByte(_)) => 8,
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(LoadTarget::DirectRegByte(_) | LoadTarget::DirectRegHalfByte(_), LoadTarget::ImmediateByte(_)) => 7,
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(LoadTarget::IndirectRegByte(_), LoadTarget::ImmediateByte(_)) => 10,
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(LoadTarget::IndirectOffsetByte(_, _), _) |
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(_, LoadTarget::IndirectOffsetByte(_, _)) => 19,
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(_, LoadTarget::IndirectRegByte(_)) |
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(LoadTarget::IndirectRegByte(_), _) => 7,
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(_, LoadTarget::IndirectByte(_)) |
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(LoadTarget::IndirectByte(_), _) => 13,
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// 16-Bit Operations
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(LoadTarget::DirectRegWord(regpair), LoadTarget::ImmediateWord(_)) |
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(LoadTarget::ImmediateWord(_), LoadTarget::DirectRegWord(regpair)) => {
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if !regpair.is_index_reg() {
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10
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} else {
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14
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}
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},
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(LoadTarget::DirectRegWord(_), LoadTarget::DirectRegWord(regpair)) => {
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if !regpair.is_index_reg() {
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6
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} else {
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10
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}
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},
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(LoadTarget::IndirectWord(_), LoadTarget::DirectRegWord(RegisterPair::HL)) |
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(LoadTarget::DirectRegWord(RegisterPair::HL), LoadTarget::IndirectWord(_)) => 16,
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(LoadTarget::IndirectWord(_), _) |
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(_, LoadTarget::IndirectWord(_)) => 20,
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_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
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}
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},
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Instruction::LDsr(_, _) => 9,
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Instruction::NEG => 8,
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Instruction::NOP => 4,
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Instruction::POP(regpair) => {
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if !regpair.is_index_reg() {
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10
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} else {
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14
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}
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},
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Instruction::PUSH(regpair) => {
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if !regpair.is_index_reg() {
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11
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} else {
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15
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}
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},
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Instruction::RES(_, target, _) |
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Instruction::SET(_, target, _) => {
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match target {
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Target::DirectReg(_) => 8,
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Target::IndirectReg(_) => 15,
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Target::IndirectOffset(_, _) => 23,
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_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
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}
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},
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Instruction::RET => 10,
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Instruction::RETI => 14,
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Instruction::RETN => 14,
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Instruction::RETcc(_) => {
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return Ok(Z80InstructionCycles::Branch {
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taken: 11 + extra,
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not_taken: 5 + extra,
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});
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},
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Instruction::RL(target, _) |
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Instruction::RLC(target, _) |
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Instruction::RR(target, _) |
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Instruction::RRC(target, _) |
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Instruction::SLA(target, _) |
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Instruction::SLL(target, _) |
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Instruction::SRA(target, _) |
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Instruction::SRL(target, _) => {
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match target {
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Target::DirectReg(_) => 8,
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Target::IndirectReg(_) => 15,
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Target::IndirectOffset(_, _) => 23,
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_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
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}
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},
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Instruction::RLA |
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Instruction::RLCA |
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Instruction::RRA |
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Instruction::RRCA => 4,
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Instruction::RLD => 18,
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Instruction::RRD => 18,
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Instruction::RST(_) => 11,
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Instruction::SCF => 4,
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};
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Ok(Z80InstructionCycles::Single(cycles + extra))
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}
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}
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