mirror of
https://github.com/transistorfet/moa.git
synced 2024-06-02 15:41:47 +00:00
fd056c8d7b
This is the proof-of-concept using computie, since it only needs one peripheral and the m68k cpu, which was already rewritten and tested
462 lines
13 KiB
Rust
462 lines
13 KiB
Rust
use std::fs;
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use std::cmp;
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use std::rc::Rc;
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use std::cell::RefCell;
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use std::fmt::Write;
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use femtos::Instant;
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use emulator_hal::{BusAccess, Error as BusError};
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use crate::error::Error;
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use crate::devices::{Address, Device, DeviceInterface, MoaBus};
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impl BusError for Error {}
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/// A contiguous block of `Addressable` memory, backed by a `Vec`
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pub struct MemoryBlock {
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read_only: bool,
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contents: Vec<u8>,
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}
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impl MemoryBlock {
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pub fn new(contents: Vec<u8>) -> MemoryBlock {
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MemoryBlock {
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read_only: false,
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contents,
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}
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}
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pub fn load(filename: &str) -> Result<MemoryBlock, Error> {
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match fs::read(filename) {
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Ok(contents) => Ok(MemoryBlock::new(contents)),
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Err(_) => Err(Error::new(format!("Error reading contents of {}", filename))),
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}
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}
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pub fn load_at(&mut self, addr: Address, filename: &str) -> Result<(), Error> {
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match fs::read(filename) {
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Ok(contents) => {
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self.contents[(addr as usize)..(addr as usize) + contents.len()].copy_from_slice(&contents);
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Ok(())
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},
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Err(_) => Err(Error::new(format!("Error reading contents of {}", filename))),
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}
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}
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pub fn size(&self) -> usize {
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self.contents.len()
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}
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pub fn read_only(&mut self) {
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self.read_only = true;
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}
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pub fn resize(&mut self, new_size: usize) {
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self.contents.resize(new_size, 0);
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}
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}
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impl BusAccess<Address> for MemoryBlock {
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type Instant = Instant;
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// TODO this is temporary
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type Error = Error;
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#[inline]
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fn read(&mut self, _clock: Self::Instant, addr: Address, data: &mut [u8]) -> Result<usize, Self::Error> {
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data.copy_from_slice(&self.contents[(addr as usize)..(addr as usize) + data.len()]);
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Ok(data.len())
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}
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#[inline]
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fn write(&mut self, _clock: Self::Instant, addr: Address, data: &[u8]) -> Result<usize, Self::Error> {
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if self.read_only {
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return Err(Error::breakpoint(format!(
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"Attempt to write to read-only memory at {:x} with data {:?}",
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addr, data
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)));
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}
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self.contents[(addr as usize)..(addr as usize) + data.len()].copy_from_slice(data);
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Ok(data.len())
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}
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}
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impl DeviceInterface for MemoryBlock {
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fn as_bus_access(&mut self) -> Option<&mut MoaBus> {
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Some(self)
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}
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}
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/*
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/// An address adapter that repeats the address space of the subdevice over the given range
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pub struct AddressRepeater {
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subdevice: Device,
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range: Address,
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}
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impl AddressRepeater {
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pub fn new(subdevice: Device, range: Address) -> Self {
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Self {
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subdevice,
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range,
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}
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}
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}
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impl Addressable for AddressRepeater {
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fn size(&self) -> usize {
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self.range as usize
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}
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fn read(&mut self, clock: Instant, addr: Address, data: &mut [u8]) -> Result<(), Error> {
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let size = self.subdevice.borrow_mut().as_addressable().unwrap().size() as Address;
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self.subdevice
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.borrow_mut()
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.as_addressable()
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.unwrap()
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.read(clock, addr % size, data)
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}
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fn write(&mut self, clock: Instant, addr: Address, data: &[u8]) -> Result<(), Error> {
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let size = self.subdevice.borrow_mut().as_addressable().unwrap().size() as Address;
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self.subdevice
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.borrow_mut()
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.as_addressable()
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.unwrap()
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.write(clock, addr % size, data)
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}
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}
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impl Transmutable for AddressRepeater {
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fn as_addressable(&mut self) -> Option<&mut dyn Addressable> {
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Some(self)
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}
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}
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/// An address adapter that uses a closure to translate the address before accessing the subdevice
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pub struct AddressTranslator {
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subdevice: Device,
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size: usize,
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func: Box<dyn Fn(Address) -> Address>,
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}
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impl AddressTranslator {
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pub fn new<F>(subdevice: Device, size: usize, func: F) -> Self
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where
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F: Fn(Address) -> Address + 'static,
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{
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Self {
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subdevice,
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size,
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func: Box::new(func),
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}
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}
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}
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impl Addressable for AddressTranslator {
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fn size(&self) -> usize {
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self.size
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}
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fn read(&mut self, clock: Instant, addr: Address, data: &mut [u8]) -> Result<(), Error> {
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self.subdevice
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.borrow_mut()
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.as_addressable()
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.unwrap()
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.read(clock, (self.func)(addr), data)
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}
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fn write(&mut self, clock: Instant, addr: Address, data: &[u8]) -> Result<(), Error> {
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self.subdevice
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.borrow_mut()
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.as_addressable()
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.unwrap()
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.write(clock, (self.func)(addr), data)
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}
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}
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impl Transmutable for AddressTranslator {
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fn as_addressable(&mut self) -> Option<&mut dyn Addressable> {
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Some(self)
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}
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}
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*/
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#[derive(Clone)]
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pub struct Block {
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pub base: Address,
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pub size: usize,
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pub dev: Device,
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}
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/// A bus-like collection of `Addressable` `Device`s mapped to different address ranges
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///
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/// This is the fundamental means of connecting devices together to a CPU implementation.
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#[derive(Clone, Default)]
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pub struct Bus {
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blocks: Vec<Block>,
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ignore_unmapped: bool,
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watchers: Vec<Address>,
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watcher_modified: bool,
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}
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impl Bus {
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pub fn set_ignore_unmapped(&mut self, ignore_unmapped: bool) {
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self.ignore_unmapped = ignore_unmapped;
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}
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pub fn clear_all_bus_devices(&mut self) {
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self.blocks.clear();
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}
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pub fn size(&self) -> usize {
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let block = &self.blocks[self.blocks.len() - 1];
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(block.base as usize) + block.size
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}
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pub fn insert(&mut self, base: Address, dev: Device, size: usize) {
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let block = Block {
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base,
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size,
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dev,
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};
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let i = self
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.blocks
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.iter()
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.position(|cur| cur.base > block.base)
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.unwrap_or(self.blocks.len());
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self.blocks.insert(i, block);
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}
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pub fn get_device_at(&self, addr: Address, count: usize) -> Result<(Device, Address), Error> {
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for block in &self.blocks {
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if addr >= block.base && addr < (block.base + block.size as Address) {
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let relative_addr = addr - block.base;
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if relative_addr as usize + count <= block.size {
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return Ok((block.dev.clone(), relative_addr));
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} else {
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return Err(Error::new(format!("Error reading address {:#010x}", addr)));
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}
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}
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}
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Err(Error::new(format!("No segment found at {:#010x}", addr)))
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}
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pub fn dump_memory(&mut self, clock: Instant, mut addr: Address, mut count: Address) {
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while count > 0 {
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let mut line = format!("{:#010x}: ", addr);
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let to = if count < 16 { count / 2 } else { 8 };
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for _ in 0..to {
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let word = self.read_beu16(clock, addr);
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if word.is_err() {
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println!("{}", line);
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return;
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}
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write!(line, "{:#06x} ", word.unwrap()).unwrap();
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addr += 2;
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count -= 2;
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}
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println!("{}", line);
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}
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}
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pub fn add_watcher(&mut self, addr: Address) {
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self.watchers.push(addr);
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}
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pub fn remove_watcher(&mut self, addr: Address) {
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self.watchers.push(addr);
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if let Some(index) = self.watchers.iter().position(|a| *a == addr) {
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self.watchers.remove(index);
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}
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}
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pub fn check_and_reset_watcher_modified(&mut self) -> bool {
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let result = self.watcher_modified;
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self.watcher_modified = false;
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result
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}
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}
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impl BusAccess<Address> for Bus {
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type Instant = Instant;
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type Error = Error;
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#[inline]
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fn read(&mut self, clock: Self::Instant, addr: Address, data: &mut [u8]) -> Result<usize, Self::Error> {
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let (dev, relative_addr) = match self.get_device_at(addr, data.len()) {
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Ok(result) => result,
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Err(err) if self.ignore_unmapped => {
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log::info!("{:?}", err);
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return Ok(0);
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},
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Err(err) => return Err(err),
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};
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let result = dev.borrow_mut().as_bus_access().unwrap().read(clock, relative_addr, data);
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result
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}
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#[inline]
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fn write(&mut self, clock: Self::Instant, addr: Address, data: &[u8]) -> Result<usize, Self::Error> {
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if self.watchers.iter().any(|a| *a == addr) {
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println!("watch: writing to address {:#06x} with {:?}", addr, data);
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self.watcher_modified = true;
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}
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let (dev, relative_addr) = match self.get_device_at(addr, data.len()) {
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Ok(result) => result,
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Err(err) if self.ignore_unmapped => {
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log::info!("{:?}", err);
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return Ok(0);
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},
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Err(err) => return Err(err),
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};
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let result = dev.borrow_mut().as_bus_access().unwrap().write(clock, relative_addr, data);
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result
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}
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}
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/*
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/// An adapter for limiting the access requests of a device (eg. CPU) on a `Bus` to the address
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/// and data widths of the device
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#[derive(Clone)]
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pub struct BusPort {
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offset: Address,
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address_mask: Address,
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data_width: u8,
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subdevice: Rc<RefCell<Bus>>,
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}
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impl BusPort {
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pub fn new(offset: Address, address_bits: u8, data_bits: u8, bus: Rc<RefCell<Bus>>) -> Self {
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Self {
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offset,
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address_mask: (1 << address_bits) - 1,
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data_width: data_bits / 8,
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subdevice: bus,
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}
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}
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pub fn dump_memory(&mut self, clock: Instant, addr: Address, count: Address) {
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self.subdevice
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.borrow_mut()
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.dump_memory(clock, self.offset + (addr & self.address_mask), count)
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}
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#[inline]
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pub fn address_mask(&self) -> Address {
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self.address_mask
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}
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#[inline]
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pub fn data_width(&self) -> u8 {
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self.data_width
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}
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}
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impl Addressable for BusPort {
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fn size(&self) -> usize {
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self.subdevice.borrow().size()
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}
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fn read(&mut self, clock: Instant, addr: Address, data: &mut [u8]) -> Result<(), Error> {
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let addr = self.offset + (addr & self.address_mask);
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let mut subdevice = self.subdevice.borrow_mut();
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for i in (0..data.len()).step_by(self.data_width as usize) {
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let addr_index = (addr + i as Address) & self.address_mask;
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let end = cmp::min(i + self.data_width as usize, data.len());
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Addressable::read(&mut *subdevice, clock, addr_index, &mut data[i..end])?;
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}
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Ok(())
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}
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fn write(&mut self, clock: Instant, addr: Address, data: &[u8]) -> Result<(), Error> {
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let addr = self.offset + (addr & self.address_mask);
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let mut subdevice = self.subdevice.borrow_mut();
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for i in (0..data.len()).step_by(self.data_width as usize) {
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let addr_index = (addr + i as Address) & self.address_mask;
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let end = cmp::min(i + self.data_width as usize, data.len());
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Addressable::write(&mut *subdevice, clock, addr_index, &data[i..end])?;
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}
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Ok(())
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}
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}
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*/
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pub fn dump_slice(data: &[u8], mut count: usize) {
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let mut addr = 0;
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while count > 0 {
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let mut line = format!("{:#010x}: ", addr);
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let to = if count < 16 { count / 2 } else { 8 };
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for _ in 0..to {
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let word = u16::from_be_bytes(data[addr..addr + 2].try_into().unwrap());
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write!(line, "{:#06x} ", word).unwrap();
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addr += 2;
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count -= 2;
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}
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println!("{}", line);
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}
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}
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pub fn dump_memory<Bus, Address, Instant>(bus: &mut Bus, clock: Instant, addr: Address, count: Address)
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where
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Bus: BusAccess<Address, Instant = Instant>,
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Address: From<u64> + Into<u64> + Copy,
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Instant: Copy,
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{
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let mut addr = addr.into();
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let mut count = count.into();
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while count > 0 {
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let mut line = format!("{:#010x}: ", addr);
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let to = if count < 16 { count / 2 } else { 8 };
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for _ in 0..to {
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let word = bus.read_beu16(clock, Address::from(addr));
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if word.is_err() {
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println!("{}", line);
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return;
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}
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write!(line, "{:#06x} ", word.unwrap()).unwrap();
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addr += 2;
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count -= 2;
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}
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println!("{}", line);
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}
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}
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/*
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impl BusError for Error {}
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impl BusAccess<u64> for &mut dyn Addressable {
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type Instant = Instant;
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type Error = Error;
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fn read(&mut self, now: Instant, addr: Address, data: &mut [u8]) -> Result<usize, Self::Error> {
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(*self).read(now, addr, data)?;
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Ok(data.len())
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}
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fn write(&mut self, now: Instant, addr: Address, data: &[u8]) -> Result<usize, Self::Error> {
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(*self).write(now, addr, data)?;
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Ok(data.len())
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}
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}
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impl BusAccess<u64> for Bus {
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type Instant = Instant;
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type Error = Error;
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fn read(&mut self, now: Instant, addr: Address, data: &mut [u8]) -> Result<usize, Self::Error> {
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Addressable::read(self, now, addr, data)?;
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Ok(data.len())
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}
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fn write(&mut self, now: Instant, addr: Address, data: &[u8]) -> Result<usize, Self::Error> {
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Addressable::write(self, now, addr, data)?;
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Ok(data.len())
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}
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}
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*/
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