Working on a total FPU rewrite based on softfloat
5 instructions down, a million more to go
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/*----------------------------------------------------------------------------
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| One of the macros `BIGENDIAN' or `LITTLEENDIAN' must be defined.
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*----------------------------------------------------------------------------*/
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#define LITTLEENDIAN
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/*----------------------------------------------------------------------------
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| The macro `BITS64' can be defined to indicate that 64-bit integer types are
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| supported by the compiler.
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*----------------------------------------------------------------------------*/
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#define BITS64
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/*----------------------------------------------------------------------------
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| Each of the following `typedef's defines the most convenient type that holds
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| integers of at least as many bits as specified. For example, `uint8' should
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| be the most convenient type that can hold unsigned integers of as many as
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| 8 bits. The `flag' type must be able to hold either a 0 or 1. For most
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| implementations of C, `flag', `uint8', and `int8' should all be `typedef'ed
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| to the same as `int'.
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*----------------------------------------------------------------------------*/
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typedef char flag;
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typedef unsigned char uint8;
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typedef signed char int8;
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typedef int uint16;
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typedef int int16;
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typedef unsigned int uint32;
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typedef signed int int32;
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#ifdef BITS64
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typedef unsigned long long int uint64;
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typedef signed long long int int64;
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#endif
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/*----------------------------------------------------------------------------
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| Each of the following `typedef's defines a type that holds integers
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| of _exactly_ the number of bits specified. For instance, for most
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| implementation of C, `bits16' and `sbits16' should be `typedef'ed to
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| `unsigned short int' and `signed short int' (or `short int'), respectively.
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*----------------------------------------------------------------------------*/
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typedef unsigned char bits8;
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typedef signed char sbits8;
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typedef unsigned short int bits16;
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typedef signed short int sbits16;
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typedef unsigned int bits32;
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typedef signed int sbits32;
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#ifdef BITS64
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typedef unsigned long long int bits64;
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typedef signed long long int sbits64;
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#endif
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#ifdef BITS64
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/*----------------------------------------------------------------------------
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| The `LIT64' macro takes as its argument a textual integer literal and
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| if necessary ``marks'' the literal as having a 64-bit integer type.
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| For example, the GNU C Compiler (`gcc') requires that 64-bit literals be
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| appended with the letters `LL' standing for `long long', which is `gcc's
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| name for the 64-bit integer type. Some compilers may allow `LIT64' to be
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| defined as the identity macro: `#define LIT64( a ) a'.
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*----------------------------------------------------------------------------*/
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#define LIT64( a ) a##LL
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#endif
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/*----------------------------------------------------------------------------
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| The macro `INLINE' can be used before functions that should be inlined. If
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| a compiler does not support explicit inlining, this macro should be defined
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| to be `static'.
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*----------------------------------------------------------------------------*/
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#define INLINE static
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/*============================================================================
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This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
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Arithmetic Package, Release 2b.
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Written by John R. Hauser. This work was made possible in part by the
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International Computer Science Institute, located at Suite 600, 1947 Center
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Street, Berkeley, California 94704. Funding was partially provided by the
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National Science Foundation under grant MIP-9311980. The original version
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of this code was written as part of a project to build a fixed-point vector
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processor in collaboration with the University of California at Berkeley,
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overseen by Profs. Nelson Morgan and John Wawrzynek. More information
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is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
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arithmetic/SoftFloat.html'.
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THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
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been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
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RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
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AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
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COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
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EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
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INSTITUTE (possibly via similar legal notice) AGAINST ALL LOSSES, COSTS, OR
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OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
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Derivative works are acceptable, even for commercial purposes, so long as
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(1) the source code for the derivative work includes prominent notice that
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the work is derivative, and (2) the source code includes prominent notice with
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these four paragraphs for those parts of this code that are retained.
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=============================================================================*/
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/*----------------------------------------------------------------------------
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| Shifts `a' right by the number of bits given in `count'. If any nonzero
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| bits are shifted off, they are ``jammed'' into the least significant bit of
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| the result by setting the least significant bit to 1. The value of `count'
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| can be arbitrarily large; in particular, if `count' is greater than 32, the
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| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
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| The result is stored in the location pointed to by `zPtr'.
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*----------------------------------------------------------------------------*/
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INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )
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{
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bits32 z;
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if ( count == 0 ) {
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z = a;
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}
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else if ( count < 32 ) {
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z = ( a>>count ) | ( ( a<<( ( - count ) & 31 ) ) != 0 );
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}
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else {
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z = ( a != 0 );
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}
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*zPtr = z;
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}
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/*----------------------------------------------------------------------------
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| Shifts `a' right by the number of bits given in `count'. If any nonzero
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| bits are shifted off, they are ``jammed'' into the least significant bit of
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| the result by setting the least significant bit to 1. The value of `count'
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| can be arbitrarily large; in particular, if `count' is greater than 64, the
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| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
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| The result is stored in the location pointed to by `zPtr'.
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*----------------------------------------------------------------------------*/
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INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr )
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{
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bits64 z;
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if ( count == 0 ) {
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z = a;
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}
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else if ( count < 64 ) {
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z = ( a>>count ) | ( ( a<<( ( - count ) & 63 ) ) != 0 );
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}
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else {
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z = ( a != 0 );
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}
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*zPtr = z;
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}
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/*----------------------------------------------------------------------------
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| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
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| _plus_ the number of bits given in `count'. The shifted result is at most
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| 64 nonzero bits; this is stored at the location pointed to by `z0Ptr'. The
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| bits shifted off form a second 64-bit result as follows: The _last_ bit
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| shifted off is the most-significant bit of the extra result, and the other
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| 63 bits of the extra result are all zero if and only if _all_but_the_last_
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| bits shifted off were all zero. This extra result is stored in the location
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| pointed to by `z1Ptr'. The value of `count' can be arbitrarily large.
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| (This routine makes more sense if `a0' and `a1' are considered to form
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| a fixed-point value with binary point between `a0' and `a1'. This fixed-
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| point value is shifted right by the number of bits given in `count', and
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| the integer part of the result is returned at the location pointed to by
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| `z0Ptr'. The fractional part of the result may be slightly corrupted as
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| described above, and is returned at the location pointed to by `z1Ptr'.)
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*----------------------------------------------------------------------------*/
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INLINE void
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shift64ExtraRightJamming(
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bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
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{
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bits64 z0, z1;
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int8 negCount = ( - count ) & 63;
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if ( count == 0 ) {
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z1 = a1;
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z0 = a0;
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}
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else if ( count < 64 ) {
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z1 = ( a0<<negCount ) | ( a1 != 0 );
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z0 = a0>>count;
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}
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else {
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if ( count == 64 ) {
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z1 = a0 | ( a1 != 0 );
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}
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else {
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z1 = ( ( a0 | a1 ) != 0 );
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}
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z0 = 0;
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}
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*z1Ptr = z1;
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*z0Ptr = z0;
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}
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/*----------------------------------------------------------------------------
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| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
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| number of bits given in `count'. Any bits shifted off are lost. The value
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| of `count' can be arbitrarily large; in particular, if `count' is greater
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| than 128, the result will be 0. The result is broken into two 64-bit pieces
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| which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
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*----------------------------------------------------------------------------*/
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INLINE void
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shift128Right(
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bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
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{
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bits64 z0, z1;
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int8 negCount = ( - count ) & 63;
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if ( count == 0 ) {
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z1 = a1;
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z0 = a0;
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}
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else if ( count < 64 ) {
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z1 = ( a0<<negCount ) | ( a1>>count );
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z0 = a0>>count;
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}
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else {
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z1 = ( count < 64 ) ? ( a0>>( count & 63 ) ) : 0;
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z0 = 0;
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}
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*z1Ptr = z1;
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*z0Ptr = z0;
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}
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/*----------------------------------------------------------------------------
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| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
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| number of bits given in `count'. If any nonzero bits are shifted off, they
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| are ``jammed'' into the least significant bit of the result by setting the
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| least significant bit to 1. The value of `count' can be arbitrarily large;
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| in particular, if `count' is greater than 128, the result will be either
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| 0 or 1, depending on whether the concatenation of `a0' and `a1' is zero or
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| nonzero. The result is broken into two 64-bit pieces which are stored at
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| the locations pointed to by `z0Ptr' and `z1Ptr'.
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*----------------------------------------------------------------------------*/
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INLINE void
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shift128RightJamming(
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bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
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{
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bits64 z0, z1;
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int8 negCount = ( - count ) & 63;
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if ( count == 0 ) {
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z1 = a1;
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z0 = a0;
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}
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else if ( count < 64 ) {
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z1 = ( a0<<negCount ) | ( a1>>count ) | ( ( a1<<negCount ) != 0 );
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z0 = a0>>count;
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}
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else {
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if ( count == 64 ) {
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z1 = a0 | ( a1 != 0 );
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}
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else if ( count < 128 ) {
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z1 = ( a0>>( count & 63 ) ) | ( ( ( a0<<negCount ) | a1 ) != 0 );
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}
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else {
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z1 = ( ( a0 | a1 ) != 0 );
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}
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z0 = 0;
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}
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*z1Ptr = z1;
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*z0Ptr = z0;
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}
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/*----------------------------------------------------------------------------
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| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' right
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| by 64 _plus_ the number of bits given in `count'. The shifted result is
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| at most 128 nonzero bits; these are broken into two 64-bit pieces which are
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| stored at the locations pointed to by `z0Ptr' and `z1Ptr'. The bits shifted
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| off form a third 64-bit result as follows: The _last_ bit shifted off is
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| the most-significant bit of the extra result, and the other 63 bits of the
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| extra result are all zero if and only if _all_but_the_last_ bits shifted off
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| were all zero. This extra result is stored in the location pointed to by
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| `z2Ptr'. The value of `count' can be arbitrarily large.
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| (This routine makes more sense if `a0', `a1', and `a2' are considered
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| to form a fixed-point value with binary point between `a1' and `a2'. This
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| fixed-point value is shifted right by the number of bits given in `count',
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| and the integer part of the result is returned at the locations pointed to
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| by `z0Ptr' and `z1Ptr'. The fractional part of the result may be slightly
|
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| corrupted as described above, and is returned at the location pointed to by
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| `z2Ptr'.)
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*----------------------------------------------------------------------------*/
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INLINE void
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shift128ExtraRightJamming(
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bits64 a0,
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bits64 a1,
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bits64 a2,
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int16 count,
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bits64 *z0Ptr,
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bits64 *z1Ptr,
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bits64 *z2Ptr
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)
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{
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bits64 z0, z1, z2;
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int8 negCount = ( - count ) & 63;
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if ( count == 0 ) {
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z2 = a2;
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z1 = a1;
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z0 = a0;
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}
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else {
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if ( count < 64 ) {
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z2 = a1<<negCount;
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z1 = ( a0<<negCount ) | ( a1>>count );
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z0 = a0>>count;
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}
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else {
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if ( count == 64 ) {
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z2 = a1;
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z1 = a0;
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}
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else {
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a2 |= a1;
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if ( count < 128 ) {
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z2 = a0<<negCount;
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z1 = a0>>( count & 63 );
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}
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else {
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z2 = ( count == 128 ) ? a0 : ( a0 != 0 );
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z1 = 0;
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}
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}
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z0 = 0;
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}
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z2 |= ( a2 != 0 );
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}
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*z2Ptr = z2;
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*z1Ptr = z1;
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*z0Ptr = z0;
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}
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/*----------------------------------------------------------------------------
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| Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the
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| number of bits given in `count'. Any bits shifted off are lost. The value
|
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| of `count' must be less than 64. The result is broken into two 64-bit
|
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| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
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*----------------------------------------------------------------------------*/
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INLINE void
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shortShift128Left(
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bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
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{
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*z1Ptr = a1<<count;
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*z0Ptr =
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( count == 0 ) ? a0 : ( a0<<count ) | ( a1>>( ( - count ) & 63 ) );
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}
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/*----------------------------------------------------------------------------
|
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| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left
|
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| by the number of bits given in `count'. Any bits shifted off are lost.
|
||||
| The value of `count' must be less than 64. The result is broken into three
|
||||
| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',
|
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| `z1Ptr', and `z2Ptr'.
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*----------------------------------------------------------------------------*/
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INLINE void
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shortShift192Left(
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bits64 a0,
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bits64 a1,
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bits64 a2,
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int16 count,
|
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bits64 *z0Ptr,
|
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bits64 *z1Ptr,
|
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bits64 *z2Ptr
|
||||
)
|
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{
|
||||
bits64 z0, z1, z2;
|
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int8 negCount;
|
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|
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z2 = a2<<count;
|
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z1 = a1<<count;
|
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z0 = a0<<count;
|
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if ( 0 < count ) {
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negCount = ( ( - count ) & 63 );
|
||||
z1 |= a2>>negCount;
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z0 |= a1>>negCount;
|
||||
}
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*z2Ptr = z2;
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*z1Ptr = z1;
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||||
*z0Ptr = z0;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit
|
||||
| value formed by concatenating `b0' and `b1'. Addition is modulo 2^128, so
|
||||
| any carry out is lost. The result is broken into two 64-bit pieces which
|
||||
| are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
|
||||
*----------------------------------------------------------------------------*/
|
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INLINE void
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add128(
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bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
|
||||
{
|
||||
bits64 z1;
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||||
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z1 = a1 + b1;
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*z1Ptr = z1;
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*z0Ptr = a0 + b0 + ( z1 < a1 );
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||||
|
||||
}
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||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the
|
||||
| 192-bit value formed by concatenating `b0', `b1', and `b2'. Addition is
|
||||
| modulo 2^192, so any carry out is lost. The result is broken into three
|
||||
| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',
|
||||
| `z1Ptr', and `z2Ptr'.
|
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*----------------------------------------------------------------------------*/
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INLINE void
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add192(
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bits64 a0,
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bits64 a1,
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bits64 a2,
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bits64 b0,
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bits64 b1,
|
||||
bits64 b2,
|
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bits64 *z0Ptr,
|
||||
bits64 *z1Ptr,
|
||||
bits64 *z2Ptr
|
||||
)
|
||||
{
|
||||
bits64 z0, z1, z2;
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||||
int8 carry0, carry1;
|
||||
|
||||
z2 = a2 + b2;
|
||||
carry1 = ( z2 < a2 );
|
||||
z1 = a1 + b1;
|
||||
carry0 = ( z1 < a1 );
|
||||
z0 = a0 + b0;
|
||||
z1 += carry1;
|
||||
z0 += ( z1 < carry1 );
|
||||
z0 += carry0;
|
||||
*z2Ptr = z2;
|
||||
*z1Ptr = z1;
|
||||
*z0Ptr = z0;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the
|
||||
| 128-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo
|
||||
| 2^128, so any borrow out (carry out) is lost. The result is broken into two
|
||||
| 64-bit pieces which are stored at the locations pointed to by `z0Ptr' and
|
||||
| `z1Ptr'.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE void
|
||||
sub128(
|
||||
bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
|
||||
{
|
||||
|
||||
*z1Ptr = a1 - b1;
|
||||
*z0Ptr = a0 - b0 - ( a1 < b1 );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2'
|
||||
| from the 192-bit value formed by concatenating `a0', `a1', and `a2'.
|
||||
| Subtraction is modulo 2^192, so any borrow out (carry out) is lost. The
|
||||
| result is broken into three 64-bit pieces which are stored at the locations
|
||||
| pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE void
|
||||
sub192(
|
||||
bits64 a0,
|
||||
bits64 a1,
|
||||
bits64 a2,
|
||||
bits64 b0,
|
||||
bits64 b1,
|
||||
bits64 b2,
|
||||
bits64 *z0Ptr,
|
||||
bits64 *z1Ptr,
|
||||
bits64 *z2Ptr
|
||||
)
|
||||
{
|
||||
bits64 z0, z1, z2;
|
||||
int8 borrow0, borrow1;
|
||||
|
||||
z2 = a2 - b2;
|
||||
borrow1 = ( a2 < b2 );
|
||||
z1 = a1 - b1;
|
||||
borrow0 = ( a1 < b1 );
|
||||
z0 = a0 - b0;
|
||||
z0 -= ( z1 < borrow1 );
|
||||
z1 -= borrow1;
|
||||
z0 -= borrow0;
|
||||
*z2Ptr = z2;
|
||||
*z1Ptr = z1;
|
||||
*z0Ptr = z0;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Multiplies `a' by `b' to obtain a 128-bit product. The product is broken
|
||||
| into two 64-bit pieces which are stored at the locations pointed to by
|
||||
| `z0Ptr' and `z1Ptr'.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )
|
||||
{
|
||||
bits32 aHigh, aLow, bHigh, bLow;
|
||||
bits64 z0, zMiddleA, zMiddleB, z1;
|
||||
|
||||
aLow = a;
|
||||
aHigh = a>>32;
|
||||
bLow = b;
|
||||
bHigh = b>>32;
|
||||
z1 = ( (bits64) aLow ) * bLow;
|
||||
zMiddleA = ( (bits64) aLow ) * bHigh;
|
||||
zMiddleB = ( (bits64) aHigh ) * bLow;
|
||||
z0 = ( (bits64) aHigh ) * bHigh;
|
||||
zMiddleA += zMiddleB;
|
||||
z0 += ( ( (bits64) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );
|
||||
zMiddleA <<= 32;
|
||||
z1 += zMiddleA;
|
||||
z0 += ( z1 < zMiddleA );
|
||||
*z1Ptr = z1;
|
||||
*z0Ptr = z0;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Multiplies the 128-bit value formed by concatenating `a0' and `a1' by
|
||||
| `b' to obtain a 192-bit product. The product is broken into three 64-bit
|
||||
| pieces which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and
|
||||
| `z2Ptr'.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE void
|
||||
mul128By64To192(
|
||||
bits64 a0,
|
||||
bits64 a1,
|
||||
bits64 b,
|
||||
bits64 *z0Ptr,
|
||||
bits64 *z1Ptr,
|
||||
bits64 *z2Ptr
|
||||
)
|
||||
{
|
||||
bits64 z0, z1, z2, more1;
|
||||
|
||||
mul64To128( a1, b, &z1, &z2 );
|
||||
mul64To128( a0, b, &z0, &more1 );
|
||||
add128( z0, more1, 0, z1, &z0, &z1 );
|
||||
*z2Ptr = z2;
|
||||
*z1Ptr = z1;
|
||||
*z0Ptr = z0;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the
|
||||
| 128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit
|
||||
| product. The product is broken into four 64-bit pieces which are stored at
|
||||
| the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE void
|
||||
mul128To256(
|
||||
bits64 a0,
|
||||
bits64 a1,
|
||||
bits64 b0,
|
||||
bits64 b1,
|
||||
bits64 *z0Ptr,
|
||||
bits64 *z1Ptr,
|
||||
bits64 *z2Ptr,
|
||||
bits64 *z3Ptr
|
||||
)
|
||||
{
|
||||
bits64 z0, z1, z2, z3;
|
||||
bits64 more1, more2;
|
||||
|
||||
mul64To128( a1, b1, &z2, &z3 );
|
||||
mul64To128( a1, b0, &z1, &more2 );
|
||||
add128( z1, more2, 0, z2, &z1, &z2 );
|
||||
mul64To128( a0, b0, &z0, &more1 );
|
||||
add128( z0, more1, 0, z1, &z0, &z1 );
|
||||
mul64To128( a0, b1, &more1, &more2 );
|
||||
add128( more1, more2, 0, z2, &more1, &z2 );
|
||||
add128( z0, z1, 0, more1, &z0, &z1 );
|
||||
*z3Ptr = z3;
|
||||
*z2Ptr = z2;
|
||||
*z1Ptr = z1;
|
||||
*z0Ptr = z0;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns an approximation to the 64-bit integer quotient obtained by dividing
|
||||
| `b' into the 128-bit value formed by concatenating `a0' and `a1'. The
|
||||
| divisor `b' must be at least 2^63. If q is the exact quotient truncated
|
||||
| toward zero, the approximation returned lies between q and q + 2 inclusive.
|
||||
| If the exact quotient q is larger than 64 bits, the maximum positive 64-bit
|
||||
| unsigned integer is returned.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b )
|
||||
{
|
||||
bits64 b0, b1;
|
||||
bits64 rem0, rem1, term0, term1;
|
||||
bits64 z;
|
||||
|
||||
if ( b <= a0 ) return LIT64( 0xFFFFFFFFFFFFFFFF );
|
||||
b0 = b>>32;
|
||||
z = ( b0<<32 <= a0 ) ? LIT64( 0xFFFFFFFF00000000 ) : ( a0 / b0 )<<32;
|
||||
mul64To128( b, z, &term0, &term1 );
|
||||
sub128( a0, a1, term0, term1, &rem0, &rem1 );
|
||||
while ( ( (sbits64) rem0 ) < 0 ) {
|
||||
z -= LIT64( 0x100000000 );
|
||||
b1 = b<<32;
|
||||
add128( rem0, rem1, b0, b1, &rem0, &rem1 );
|
||||
}
|
||||
rem0 = ( rem0<<32 ) | ( rem1>>32 );
|
||||
z |= ( b0<<32 <= rem0 ) ? 0xFFFFFFFF : rem0 / b0;
|
||||
return z;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns an approximation to the square root of the 32-bit significand given
|
||||
| by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of
|
||||
| `aExp' (the least significant bit) is 1, the integer returned approximates
|
||||
| 2^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp'
|
||||
| is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either
|
||||
| case, the approximation returned lies strictly within +/-2 of the exact
|
||||
| value.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static bits32 estimateSqrt32( int16 aExp, bits32 a )
|
||||
{
|
||||
static const bits16 sqrtOddAdjustments[] = {
|
||||
0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,
|
||||
0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67
|
||||
};
|
||||
static const bits16 sqrtEvenAdjustments[] = {
|
||||
0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,
|
||||
0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002
|
||||
};
|
||||
int8 index;
|
||||
bits32 z;
|
||||
|
||||
index = ( a>>27 ) & 15;
|
||||
if ( aExp & 1 ) {
|
||||
z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];
|
||||
z = ( ( a / z )<<14 ) + ( z<<15 );
|
||||
a >>= 1;
|
||||
}
|
||||
else {
|
||||
z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];
|
||||
z = a / z + z;
|
||||
z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );
|
||||
if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );
|
||||
}
|
||||
return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the number of leading 0 bits before the most-significant 1 bit of
|
||||
| `a'. If `a' is zero, 32 is returned.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static int8 countLeadingZeros32( bits32 a )
|
||||
{
|
||||
static const int8 countLeadingZerosHigh[] = {
|
||||
8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
};
|
||||
int8 shiftCount;
|
||||
|
||||
shiftCount = 0;
|
||||
if ( a < 0x10000 ) {
|
||||
shiftCount += 16;
|
||||
a <<= 16;
|
||||
}
|
||||
if ( a < 0x1000000 ) {
|
||||
shiftCount += 8;
|
||||
a <<= 8;
|
||||
}
|
||||
shiftCount += countLeadingZerosHigh[ a>>24 ];
|
||||
return shiftCount;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the number of leading 0 bits before the most-significant 1 bit of
|
||||
| `a'. If `a' is zero, 64 is returned.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static int8 countLeadingZeros64( bits64 a )
|
||||
{
|
||||
int8 shiftCount;
|
||||
|
||||
shiftCount = 0;
|
||||
if ( a < ( (bits64) 1 )<<32 ) {
|
||||
shiftCount += 32;
|
||||
}
|
||||
else {
|
||||
a >>= 32;
|
||||
}
|
||||
shiftCount += countLeadingZeros32( a );
|
||||
return shiftCount;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'
|
||||
| is equal to the 128-bit value formed by concatenating `b0' and `b1'.
|
||||
| Otherwise, returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
|
||||
{
|
||||
|
||||
return ( a0 == b0 ) && ( a1 == b1 );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
|
||||
| than or equal to the 128-bit value formed by concatenating `b0' and `b1'.
|
||||
| Otherwise, returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
|
||||
{
|
||||
|
||||
return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
|
||||
| than the 128-bit value formed by concatenating `b0' and `b1'. Otherwise,
|
||||
| returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
|
||||
{
|
||||
|
||||
return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is
|
||||
| not equal to the 128-bit value formed by concatenating `b0' and `b1'.
|
||||
| Otherwise, returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
INLINE flag ne128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
|
||||
{
|
||||
|
||||
return ( a0 != b0 ) || ( a1 != b1 );
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,464 @@
|
|||
|
||||
/*============================================================================
|
||||
|
||||
This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
|
||||
Arithmetic Package, Release 2b.
|
||||
|
||||
Written by John R. Hauser. This work was made possible in part by the
|
||||
International Computer Science Institute, located at Suite 600, 1947 Center
|
||||
Street, Berkeley, California 94704. Funding was partially provided by the
|
||||
National Science Foundation under grant MIP-9311980. The original version
|
||||
of this code was written as part of a project to build a fixed-point vector
|
||||
processor in collaboration with the University of California at Berkeley,
|
||||
overseen by Profs. Nelson Morgan and John Wawrzynek. More information
|
||||
is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
|
||||
arithmetic/SoftFloat.html'.
|
||||
|
||||
THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
|
||||
been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
|
||||
RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
|
||||
AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
|
||||
COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
|
||||
EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
|
||||
INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
|
||||
OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
|
||||
|
||||
Derivative works are acceptable, even for commercial purposes, so long as
|
||||
(1) the source code for the derivative work includes prominent notice that
|
||||
the work is derivative, and (2) the source code includes prominent notice with
|
||||
these four paragraphs for those parts of this code that are retained.
|
||||
|
||||
=============================================================================*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Underflow tininess-detection mode, statically initialized to default value.
|
||||
| (The declaration in `softfloat.h' must match the `int8' type here.)
|
||||
*----------------------------------------------------------------------------*/
|
||||
int8 float_detect_tininess = float_tininess_after_rounding;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Raises the exceptions specified by `flags'. Floating-point traps can be
|
||||
| defined here if desired. It is currently not possible for such a trap
|
||||
| to substitute a result value. If traps are not implemented, this routine
|
||||
| should be simply `float_exception_flags |= flags;'.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
void float_raise( int8 flags )
|
||||
{
|
||||
|
||||
float_exception_flags |= flags;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Internal canonical NaN format.
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef struct {
|
||||
flag sign;
|
||||
bits64 high, low;
|
||||
} commonNaNT;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated single-precision NaN.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define float32_default_nan 0xFFC00000
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the single-precision floating-point value `a' is a NaN;
|
||||
| otherwise returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
flag float32_is_nan( float32 a )
|
||||
{
|
||||
|
||||
return ( 0xFF000000 < (bits32) ( a<<1 ) );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the single-precision floating-point value `a' is a signaling
|
||||
| NaN; otherwise returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
flag float32_is_signaling_nan( float32 a )
|
||||
{
|
||||
|
||||
return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of converting the single-precision floating-point NaN
|
||||
| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
|
||||
| exception is raised.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static commonNaNT float32ToCommonNaN( float32 a )
|
||||
{
|
||||
commonNaNT z;
|
||||
|
||||
if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
|
||||
z.sign = a>>31;
|
||||
z.low = 0;
|
||||
z.high = ( (bits64) a )<<41;
|
||||
return z;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of converting the canonical NaN `a' to the single-
|
||||
| precision floating-point format.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static float32 commonNaNToFloat32( commonNaNT a )
|
||||
{
|
||||
|
||||
return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Takes two single-precision floating-point values `a' and `b', one of which
|
||||
| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
|
||||
| signaling NaN, the invalid exception is raised.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static float32 propagateFloat32NaN( float32 a, float32 b )
|
||||
{
|
||||
flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
|
||||
|
||||
aIsNaN = float32_is_nan( a );
|
||||
aIsSignalingNaN = float32_is_signaling_nan( a );
|
||||
bIsNaN = float32_is_nan( b );
|
||||
bIsSignalingNaN = float32_is_signaling_nan( b );
|
||||
a |= 0x00400000;
|
||||
b |= 0x00400000;
|
||||
if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
|
||||
if ( aIsSignalingNaN ) {
|
||||
if ( bIsSignalingNaN ) goto returnLargerSignificand;
|
||||
return bIsNaN ? b : a;
|
||||
}
|
||||
else if ( aIsNaN ) {
|
||||
if ( bIsSignalingNaN | ! bIsNaN ) return a;
|
||||
returnLargerSignificand:
|
||||
if ( (bits32) ( a<<1 ) < (bits32) ( b<<1 ) ) return b;
|
||||
if ( (bits32) ( b<<1 ) < (bits32) ( a<<1 ) ) return a;
|
||||
return ( a < b ) ? a : b;
|
||||
}
|
||||
else {
|
||||
return b;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated double-precision NaN.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define float64_default_nan LIT64( 0xFFF8000000000000 )
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the double-precision floating-point value `a' is a NaN;
|
||||
| otherwise returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
flag float64_is_nan( float64 a )
|
||||
{
|
||||
|
||||
return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the double-precision floating-point value `a' is a signaling
|
||||
| NaN; otherwise returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
flag float64_is_signaling_nan( float64 a )
|
||||
{
|
||||
|
||||
return
|
||||
( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
|
||||
&& ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of converting the double-precision floating-point NaN
|
||||
| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
|
||||
| exception is raised.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static commonNaNT float64ToCommonNaN( float64 a )
|
||||
{
|
||||
commonNaNT z;
|
||||
|
||||
if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
|
||||
z.sign = a>>63;
|
||||
z.low = 0;
|
||||
z.high = a<<12;
|
||||
return z;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of converting the canonical NaN `a' to the double-
|
||||
| precision floating-point format.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static float64 commonNaNToFloat64( commonNaNT a )
|
||||
{
|
||||
|
||||
return
|
||||
( ( (bits64) a.sign )<<63 )
|
||||
| LIT64( 0x7FF8000000000000 )
|
||||
| ( a.high>>12 );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Takes two double-precision floating-point values `a' and `b', one of which
|
||||
| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
|
||||
| signaling NaN, the invalid exception is raised.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static float64 propagateFloat64NaN( float64 a, float64 b )
|
||||
{
|
||||
flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
|
||||
|
||||
aIsNaN = float64_is_nan( a );
|
||||
aIsSignalingNaN = float64_is_signaling_nan( a );
|
||||
bIsNaN = float64_is_nan( b );
|
||||
bIsSignalingNaN = float64_is_signaling_nan( b );
|
||||
a |= LIT64( 0x0008000000000000 );
|
||||
b |= LIT64( 0x0008000000000000 );
|
||||
if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
|
||||
if ( aIsSignalingNaN ) {
|
||||
if ( bIsSignalingNaN ) goto returnLargerSignificand;
|
||||
return bIsNaN ? b : a;
|
||||
}
|
||||
else if ( aIsNaN ) {
|
||||
if ( bIsSignalingNaN | ! bIsNaN ) return a;
|
||||
returnLargerSignificand:
|
||||
if ( (bits64) ( a<<1 ) < (bits64) ( b<<1 ) ) return b;
|
||||
if ( (bits64) ( b<<1 ) < (bits64) ( a<<1 ) ) return a;
|
||||
return ( a < b ) ? a : b;
|
||||
}
|
||||
else {
|
||||
return b;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#ifdef FLOATX80
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated extended double-precision NaN. The
|
||||
| `high' and `low' values hold the most- and least-significant bits,
|
||||
| respectively.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define floatx80_default_nan_high 0xFFFF
|
||||
#define floatx80_default_nan_low LIT64( 0xC000000000000000 )
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the extended double-precision floating-point value `a' is a
|
||||
| NaN; otherwise returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
flag floatx80_is_nan( floatx80 a )
|
||||
{
|
||||
|
||||
return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the extended double-precision floating-point value `a' is a
|
||||
| signaling NaN; otherwise returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
flag floatx80_is_signaling_nan( floatx80 a )
|
||||
{
|
||||
bits64 aLow;
|
||||
|
||||
aLow = a.low & ~ LIT64( 0x4000000000000000 );
|
||||
return
|
||||
( ( a.high & 0x7FFF ) == 0x7FFF )
|
||||
&& (bits64) ( aLow<<1 )
|
||||
&& ( a.low == aLow );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of converting the extended double-precision floating-
|
||||
| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
|
||||
| invalid exception is raised.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static commonNaNT floatx80ToCommonNaN( floatx80 a )
|
||||
{
|
||||
commonNaNT z;
|
||||
|
||||
if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
|
||||
z.sign = a.high>>15;
|
||||
z.low = 0;
|
||||
z.high = a.low<<1;
|
||||
return z;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of converting the canonical NaN `a' to the extended
|
||||
| double-precision floating-point format.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static floatx80 commonNaNToFloatx80( commonNaNT a )
|
||||
{
|
||||
floatx80 z;
|
||||
|
||||
z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );
|
||||
z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
|
||||
return z;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Takes two extended double-precision floating-point values `a' and `b', one
|
||||
| of which is a NaN, and returns the appropriate NaN result. If either `a' or
|
||||
| `b' is a signaling NaN, the invalid exception is raised.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )
|
||||
{
|
||||
flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
|
||||
|
||||
aIsNaN = floatx80_is_nan( a );
|
||||
aIsSignalingNaN = floatx80_is_signaling_nan( a );
|
||||
bIsNaN = floatx80_is_nan( b );
|
||||
bIsSignalingNaN = floatx80_is_signaling_nan( b );
|
||||
a.low |= LIT64( 0xC000000000000000 );
|
||||
b.low |= LIT64( 0xC000000000000000 );
|
||||
if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
|
||||
if ( aIsSignalingNaN ) {
|
||||
if ( bIsSignalingNaN ) goto returnLargerSignificand;
|
||||
return bIsNaN ? b : a;
|
||||
}
|
||||
else if ( aIsNaN ) {
|
||||
if ( bIsSignalingNaN | ! bIsNaN ) return a;
|
||||
returnLargerSignificand:
|
||||
if ( a.low < b.low ) return b;
|
||||
if ( b.low < a.low ) return a;
|
||||
return ( a.high < b.high ) ? a : b;
|
||||
}
|
||||
else {
|
||||
return b;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef FLOAT128
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated quadruple-precision NaN. The `high' and
|
||||
| `low' values hold the most- and least-significant bits, respectively.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
|
||||
#define float128_default_nan_low LIT64( 0x0000000000000000 )
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the quadruple-precision floating-point value `a' is a NaN;
|
||||
| otherwise returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
flag float128_is_nan( float128 a )
|
||||
{
|
||||
|
||||
return
|
||||
( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
|
||||
&& ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns 1 if the quadruple-precision floating-point value `a' is a
|
||||
| signaling NaN; otherwise returns 0.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
flag float128_is_signaling_nan( float128 a )
|
||||
{
|
||||
|
||||
return
|
||||
( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
|
||||
&& ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of converting the quadruple-precision floating-point NaN
|
||||
| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
|
||||
| exception is raised.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static commonNaNT float128ToCommonNaN( float128 a )
|
||||
{
|
||||
commonNaNT z;
|
||||
|
||||
if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
|
||||
z.sign = a.high>>63;
|
||||
shortShift128Left( a.high, a.low, 16, &z.high, &z.low );
|
||||
return z;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Returns the result of converting the canonical NaN `a' to the quadruple-
|
||||
| precision floating-point format.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static float128 commonNaNToFloat128( commonNaNT a )
|
||||
{
|
||||
float128 z;
|
||||
|
||||
shift128Right( a.high, a.low, 16, &z.high, &z.low );
|
||||
z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );
|
||||
return z;
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Takes two quadruple-precision floating-point values `a' and `b', one of
|
||||
| which is a NaN, and returns the appropriate NaN result. If either `a' or
|
||||
| `b' is a signaling NaN, the invalid exception is raised.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static float128 propagateFloat128NaN( float128 a, float128 b )
|
||||
{
|
||||
flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
|
||||
|
||||
aIsNaN = float128_is_nan( a );
|
||||
aIsSignalingNaN = float128_is_signaling_nan( a );
|
||||
bIsNaN = float128_is_nan( b );
|
||||
bIsSignalingNaN = float128_is_signaling_nan( b );
|
||||
a.high |= LIT64( 0x0000800000000000 );
|
||||
b.high |= LIT64( 0x0000800000000000 );
|
||||
if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
|
||||
if ( aIsSignalingNaN ) {
|
||||
if ( bIsSignalingNaN ) goto returnLargerSignificand;
|
||||
return bIsNaN ? b : a;
|
||||
}
|
||||
else if ( aIsNaN ) {
|
||||
if ( bIsSignalingNaN | ! bIsNaN ) return a;
|
||||
returnLargerSignificand:
|
||||
if ( lt128( a.high<<1, a.low, b.high<<1, b.low ) ) return b;
|
||||
if ( lt128( b.high<<1, b.low, a.high<<1, a.low ) ) return a;
|
||||
return ( a.high < b.high ) ? a : b;
|
||||
}
|
||||
else {
|
||||
return b;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,259 @@
|
|||
|
||||
/*============================================================================
|
||||
|
||||
This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
|
||||
Package, Release 2b.
|
||||
|
||||
Written by John R. Hauser. This work was made possible in part by the
|
||||
International Computer Science Institute, located at Suite 600, 1947 Center
|
||||
Street, Berkeley, California 94704. Funding was partially provided by the
|
||||
National Science Foundation under grant MIP-9311980. The original version
|
||||
of this code was written as part of a project to build a fixed-point vector
|
||||
processor in collaboration with the University of California at Berkeley,
|
||||
overseen by Profs. Nelson Morgan and John Wawrzynek. More information
|
||||
is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
|
||||
arithmetic/SoftFloat.html'.
|
||||
|
||||
THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
|
||||
been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
|
||||
RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
|
||||
AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
|
||||
COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
|
||||
EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
|
||||
INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
|
||||
OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
|
||||
|
||||
Derivative works are acceptable, even for commercial purposes, so long as
|
||||
(1) the source code for the derivative work includes prominent notice that
|
||||
the work is derivative, and (2) the source code includes prominent notice with
|
||||
these four paragraphs for those parts of this code that are retained.
|
||||
|
||||
=============================================================================*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| The macro `FLOATX80' must be defined to enable the extended double-precision
|
||||
| floating-point format `floatx80'. If this macro is not defined, the
|
||||
| `floatx80' type will not be defined, and none of the functions that either
|
||||
| input or output the `floatx80' type will be defined. The same applies to
|
||||
| the `FLOAT128' macro and the quadruple-precision format `float128'.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define FLOATX80
|
||||
#define FLOAT128
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE floating-point types.
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef unsigned int float32;
|
||||
typedef unsigned long long float64;
|
||||
#ifdef FLOATX80
|
||||
typedef struct {
|
||||
unsigned long long low;
|
||||
unsigned short high;
|
||||
} floatx80;
|
||||
#endif
|
||||
#ifdef FLOAT128
|
||||
typedef struct {
|
||||
unsigned long long low, high;
|
||||
} float128;
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE floating-point underflow tininess-detection mode.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern signed char float_detect_tininess;
|
||||
enum {
|
||||
float_tininess_after_rounding = 0,
|
||||
float_tininess_before_rounding = 1
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE floating-point rounding mode.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern signed char float_rounding_mode;
|
||||
enum {
|
||||
float_round_nearest_even = 0,
|
||||
float_round_down = 1,
|
||||
float_round_up = 2,
|
||||
float_round_to_zero = 3
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE floating-point exception flags.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern signed char float_exception_flags;
|
||||
enum {
|
||||
float_flag_invalid = 1,
|
||||
float_flag_divbyzero = 4,
|
||||
float_flag_overflow = 8,
|
||||
float_flag_underflow = 16,
|
||||
float_flag_inexact = 32
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Routine to raise any or all of the software IEC/IEEE floating-point
|
||||
| exception flags.
|
||||
*----------------------------------------------------------------------------*/
|
||||
void float_raise( signed char );
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE integer-to-floating-point conversion routines.
|
||||
*----------------------------------------------------------------------------*/
|
||||
float32 int32_to_float32( int );
|
||||
float64 int32_to_float64( int );
|
||||
#ifdef FLOATX80
|
||||
floatx80 int32_to_floatx80( int );
|
||||
#endif
|
||||
#ifdef FLOAT128
|
||||
float128 int32_to_float128( int );
|
||||
#endif
|
||||
float32 int64_to_float32( long long );
|
||||
float64 int64_to_float64( long long );
|
||||
#ifdef FLOATX80
|
||||
floatx80 int64_to_floatx80( long long );
|
||||
#endif
|
||||
#ifdef FLOAT128
|
||||
float128 int64_to_float128( long long );
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE single-precision conversion routines.
|
||||
*----------------------------------------------------------------------------*/
|
||||
int float32_to_int32( float32 );
|
||||
int float32_to_int32_round_to_zero( float32 );
|
||||
long long float32_to_int64( float32 );
|
||||
long long float32_to_int64_round_to_zero( float32 );
|
||||
float64 float32_to_float64( float32 );
|
||||
#ifdef FLOATX80
|
||||
floatx80 float32_to_floatx80( float32 );
|
||||
#endif
|
||||
#ifdef FLOAT128
|
||||
float128 float32_to_float128( float32 );
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE single-precision operations.
|
||||
*----------------------------------------------------------------------------*/
|
||||
float32 float32_round_to_int( float32 );
|
||||
float32 float32_add( float32, float32 );
|
||||
float32 float32_sub( float32, float32 );
|
||||
float32 float32_mul( float32, float32 );
|
||||
float32 float32_div( float32, float32 );
|
||||
float32 float32_rem( float32, float32 );
|
||||
float32 float32_sqrt( float32 );
|
||||
char float32_eq( float32, float32 );
|
||||
char float32_le( float32, float32 );
|
||||
char float32_lt( float32, float32 );
|
||||
char float32_eq_signaling( float32, float32 );
|
||||
char float32_le_quiet( float32, float32 );
|
||||
char float32_lt_quiet( float32, float32 );
|
||||
char float32_is_signaling_nan( float32 );
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE double-precision conversion routines.
|
||||
*----------------------------------------------------------------------------*/
|
||||
int float64_to_int32( float64 );
|
||||
int float64_to_int32_round_to_zero( float64 );
|
||||
long long float64_to_int64( float64 );
|
||||
long long float64_to_int64_round_to_zero( float64 );
|
||||
float32 float64_to_float32( float64 );
|
||||
#ifdef FLOATX80
|
||||
floatx80 float64_to_floatx80( float64 );
|
||||
#endif
|
||||
#ifdef FLOAT128
|
||||
float128 float64_to_float128( float64 );
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE double-precision operations.
|
||||
*----------------------------------------------------------------------------*/
|
||||
float64 float64_round_to_int( float64 );
|
||||
float64 float64_add( float64, float64 );
|
||||
float64 float64_sub( float64, float64 );
|
||||
float64 float64_mul( float64, float64 );
|
||||
float64 float64_div( float64, float64 );
|
||||
float64 float64_rem( float64, float64 );
|
||||
float64 float64_sqrt( float64 );
|
||||
char float64_eq( float64, float64 );
|
||||
char float64_le( float64, float64 );
|
||||
char float64_lt( float64, float64 );
|
||||
char float64_eq_signaling( float64, float64 );
|
||||
char float64_le_quiet( float64, float64 );
|
||||
char float64_lt_quiet( float64, float64 );
|
||||
char float64_is_signaling_nan( float64 );
|
||||
|
||||
#ifdef FLOATX80
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE extended double-precision conversion routines.
|
||||
*----------------------------------------------------------------------------*/
|
||||
int floatx80_to_int32( floatx80 );
|
||||
int floatx80_to_int32_round_to_zero( floatx80 );
|
||||
long long floatx80_to_int64( floatx80 );
|
||||
long long floatx80_to_int64_round_to_zero( floatx80 );
|
||||
float32 floatx80_to_float32( floatx80 );
|
||||
float64 floatx80_to_float64( floatx80 );
|
||||
#ifdef FLOAT128
|
||||
float128 floatx80_to_float128( floatx80 );
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE extended double-precision rounding precision. Valid
|
||||
| values are 32, 64, and 80.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern signed char floatx80_rounding_precision;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE extended double-precision operations.
|
||||
*----------------------------------------------------------------------------*/
|
||||
floatx80 floatx80_round_to_int( floatx80 );
|
||||
floatx80 floatx80_add( floatx80, floatx80 );
|
||||
floatx80 floatx80_sub( floatx80, floatx80 );
|
||||
floatx80 floatx80_mul( floatx80, floatx80 );
|
||||
floatx80 floatx80_div( floatx80, floatx80 );
|
||||
floatx80 floatx80_rem( floatx80, floatx80 );
|
||||
floatx80 floatx80_sqrt( floatx80 );
|
||||
char floatx80_eq( floatx80, floatx80 );
|
||||
char floatx80_le( floatx80, floatx80 );
|
||||
char floatx80_lt( floatx80, floatx80 );
|
||||
char floatx80_eq_signaling( floatx80, floatx80 );
|
||||
char floatx80_le_quiet( floatx80, floatx80 );
|
||||
char floatx80_lt_quiet( floatx80, floatx80 );
|
||||
char floatx80_is_signaling_nan( floatx80 );
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef FLOAT128
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE quadruple-precision conversion routines.
|
||||
*----------------------------------------------------------------------------*/
|
||||
int float128_to_int32( float128 );
|
||||
int float128_to_int32_round_to_zero( float128 );
|
||||
long long float128_to_int64( float128 );
|
||||
long long float128_to_int64_round_to_zero( float128 );
|
||||
float32 float128_to_float32( float128 );
|
||||
float64 float128_to_float64( float128 );
|
||||
#ifdef FLOATX80
|
||||
floatx80 float128_to_floatx80( float128 );
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE quadruple-precision operations.
|
||||
*----------------------------------------------------------------------------*/
|
||||
float128 float128_round_to_int( float128 );
|
||||
float128 float128_add( float128, float128 );
|
||||
float128 float128_sub( float128, float128 );
|
||||
float128 float128_mul( float128, float128 );
|
||||
float128 float128_div( float128, float128 );
|
||||
float128 float128_rem( float128, float128 );
|
||||
float128 float128_sqrt( float128 );
|
||||
char float128_eq( float128, float128 );
|
||||
char float128_le( float128, float128 );
|
||||
char float128_lt( float128, float128 );
|
||||
char float128_eq_signaling( float128, float128 );
|
||||
char float128_le_quiet( float128, float128 );
|
||||
char float128_lt_quiet( float128, float128 );
|
||||
char float128_is_signaling_nan( float128 );
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <math.h>
|
||||
#include "softfloat.h"
|
||||
|
||||
floatx80 f[8];
|
||||
|
||||
int main (void)
|
||||
{
|
||||
float128 a = int64_to_float128(123);
|
||||
float128 b = int64_to_float128(123);
|
||||
float128 c = float128_mul(a, b);
|
||||
|
||||
int32_t c_int = float128_to_int32(c);
|
||||
|
||||
|
||||
printf("123 * 123 = %d (expected %d)\n", c_int, 123 * 123);
|
||||
|
||||
printf("%f\n", a);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,536 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2014, Peter Rutenbar <pruten@gmail.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include "../core/shoebill.h"
|
||||
#include "../core/SoftFloat/softfloat.h"
|
||||
|
||||
#pragma mark Structures and macros
|
||||
|
||||
// Mode control byte
|
||||
#define mc_rnd (fpu->fpcr.b._mc_rnd)
|
||||
#define mc_prec (fpu->fpcr.b._mc_prec)
|
||||
|
||||
// Exception enable byte
|
||||
#define ee_inex1 (fpu->fpcr.b._ee_inex1)
|
||||
#define ee_inex2 (fpu->fpcr.b._ee_inex2)
|
||||
#define ee_dz (fpu->fpcr.b._ee_dz)
|
||||
#define ee_unfl (fpu->fpcr.b._ee_unfl)
|
||||
#define ee_ovfl (fpu->fpcr.b._ee_ovfl)
|
||||
#define ee_operr (fpu->fpcr.b._ee_operr)
|
||||
#define ee_snan (fpu->fpcr.b._ee_snan)
|
||||
#define ee_bsun (fpu->fpcr.b._ee_bsun)
|
||||
|
||||
// Accrued exception byte
|
||||
#define ae_inex (fpu->fpsr.b._ae_inex)
|
||||
#define ae_dz (fpu->fpsr.b._ae_dz)
|
||||
#define ae_unfl (fpu->fpsr.b._ae_unfl)
|
||||
#define ae_ovfl (fpu->fpsr.b._ae_ovfl)
|
||||
#define ae_iop (fpu->fpsr.b._ae_iop)
|
||||
|
||||
// Exception status byte
|
||||
#define es_inex1 (fpu->fpsr.b._es_inex1)
|
||||
#define es_inex2 (fpu->fpsr.b._es_inex2)
|
||||
#define es_dz (fpu->fpsr.b._es_dz)
|
||||
#define es_unfl (fpu->fpsr.b._es_unfl)
|
||||
#define es_ovfl (fpu->fpsr.b._es_ovfl)
|
||||
#define es_operr (fpu->fpsr.b._es_operr)
|
||||
#define es_snan (fpu->fpsr.b._es_snan)
|
||||
#define es_bsun (fpu->fpsr.b._es_bsun)
|
||||
|
||||
// Quotient byte
|
||||
#define qu_quotient (fpu->fpsr.b._qu_quotient)
|
||||
#define qu_s (fpu->fpsr.b._qu_s) /* quotient sign */
|
||||
|
||||
// Condition codes
|
||||
#define cc_nan (fpu->fpsr.b._cc_nan)
|
||||
#define cc_i (fpu->fpsr.b._cc_i)
|
||||
#define cc_z (fpu->fpsr.b._cc_z)
|
||||
#define cc_n (fpu->fpsr.b._cc_n)
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t fpiar; // FPU iaddr
|
||||
|
||||
union { // fpcr, fpu control register
|
||||
struct {
|
||||
// Mode control byte
|
||||
uint16_t _mc_zero : 4; // zero/dummy
|
||||
uint16_t _mc_rnd : 2; // rounding mode
|
||||
uint16_t _mc_prec : 2; // rounding precision
|
||||
// Exception enable byte
|
||||
uint16_t _ee_inex1 : 1; // inexact decimal input
|
||||
uint16_t _ee_inex2 : 1; // inxact operation
|
||||
uint16_t _ee_dz : 1; // divide by zero
|
||||
uint16_t _ee_unfl : 1; // underflow
|
||||
uint16_t _ee_ovfl : 1; // overflow
|
||||
uint16_t _ee_operr : 1; // operand error
|
||||
uint16_t _ee_snan : 1; // signalling not a number
|
||||
uint16_t _ee_bsun : 1; // branch/set on unordered
|
||||
} b;
|
||||
|
||||
uint16_t raw;
|
||||
} fpcr;
|
||||
|
||||
union { // fpsr, fpu status register
|
||||
struct {
|
||||
// Accrued exception byte
|
||||
uint32_t _dummy1 : 3; // dummy/zero
|
||||
uint32_t _ae_inex : 1; // inexact
|
||||
uint32_t _ae_dz : 1; // divide by zero
|
||||
uint32_t _ae_unfl : 1; // underflow
|
||||
uint32_t _ae_ovfl : 1; // overflow
|
||||
uint32_t _ae_iop : 1; // invalid operation
|
||||
// Exception status byte
|
||||
uint32_t _es_inex1 : 1; // inexact decimal input
|
||||
uint32_t _es_inex2 : 1; // inxact operation
|
||||
uint32_t _es_dz : 1; // divide by zero
|
||||
uint32_t _es_unfl : 1; // underflow
|
||||
uint32_t _es_ovfl : 1; // overflow
|
||||
uint32_t _es_operr : 1; // operand error
|
||||
uint32_t _es_snan : 1; // signalling not a number
|
||||
uint32_t _es_bsun : 1; // branch/set on unordered
|
||||
// Quotient byte
|
||||
uint32_t _qu_quotient : 7;
|
||||
uint32_t _qu_s : 1;
|
||||
// Condition code byte
|
||||
uint32_t _cc_nan : 1; // not a number
|
||||
uint32_t _cc_i : 1; // infinity
|
||||
uint32_t _cc_z : 1; // zero
|
||||
uint32_t _cc_n : 1; // negative
|
||||
uint32_t _dummy2 : 4; // dummy/zero
|
||||
} b;
|
||||
uint32_t raw;
|
||||
} fpsr;
|
||||
|
||||
floatx80 fp[8]; // 80 bit floating point general registers
|
||||
|
||||
} fpu_state_t;
|
||||
|
||||
|
||||
#define fpu_get_state_ptr() fpu_state_t *fpu = (fpu_state_t*)shoe.fpu_state
|
||||
#define nextword() ({const uint16_t w=lget(shoe.pc,2); if (shoe.abort) {return;}; shoe.pc+=2; w;})
|
||||
#define nextlong() ({const uint32_t L=lget(shoe.pc,4); if (shoe.abort) {return;}; shoe.pc+=4; L;})
|
||||
#define verify_supervisor() {if (!sr_s()) {throw_privilege_violation(); return;}}
|
||||
|
||||
#pragma mark FPU exception throwers
|
||||
enum fpu_vector_t {
|
||||
fpu_vector_ftrapcc = 7,
|
||||
fpu_vector_fline = 11,
|
||||
fpu_vector_coprocessor_protocol_violation = 13, // won't be using this one
|
||||
fpu_vector_bsun = 48,
|
||||
fpu_vector_inexact = 49,
|
||||
fpu_vector_divide_by_zero = 50,
|
||||
fpu_vector_underflow = 51,
|
||||
fpu_vector_operr = 52,
|
||||
fpu_vector_overflow = 53,
|
||||
fpu_vector_snan = 54
|
||||
};
|
||||
|
||||
#define expush(_dat, _sz) {\
|
||||
const uint32_t sz = (_sz); \
|
||||
lset(shoe.a[7] - sz, sz, (_dat)); \
|
||||
if (shoe.abort) assert(!"fpu: expush: double fault during lset!"); \
|
||||
shoe.a[7] -= sz; \
|
||||
}
|
||||
|
||||
static void throw_fpu_pre_instruction_exception(enum fpu_vector_t vector)
|
||||
{
|
||||
throw_frame_zero(shoe.orig_sr, shoe.orig_pc, vector);
|
||||
}
|
||||
// Note: I may be able to get away without implementing the
|
||||
// mid-instruction exception.
|
||||
|
||||
/*
|
||||
* _bsun_test() is called by every inst_f*cc instruction
|
||||
* to test whether the bsun exception is enabled, throw an
|
||||
* exception if so, and otherwise just set the appropriate
|
||||
* bit in fpsr, and update the accrued exception byte.
|
||||
*/
|
||||
static _Bool _bsun_test()
|
||||
{
|
||||
fpu_get_state_ptr();
|
||||
|
||||
// BSUN counts against the IOP accrued exception bit
|
||||
ae_iop = 1;
|
||||
|
||||
// Set the BSUN exception status bit
|
||||
es_bsun = 1;
|
||||
|
||||
// If the BSUN exception isn't enabled, then we can just return
|
||||
if (!ee_bsun)
|
||||
return 0; // 0 -> elected not to throw an exception
|
||||
|
||||
throw_fpu_pre_instruction_exception(fpu_vector_bsun);
|
||||
return 1;
|
||||
}
|
||||
|
||||
#pragma mark Second-hop instructions
|
||||
|
||||
static void inst_fmath (const uint16_t ext)
|
||||
{
|
||||
~decompose(shoe.op, 1111 001 000 MMMMMM);
|
||||
~decompose(ext, 0 a 0 sss ddd eeeeeee);
|
||||
|
||||
const uint8_t src_in_ea = a;
|
||||
const uint8_t source_specifier = s;
|
||||
const uint8_t dest_register = d;
|
||||
const uint8_t extension = e;
|
||||
|
||||
_Bool do_write_back_result = 1;
|
||||
|
||||
float128 source, result;
|
||||
|
||||
if (src_in_ea) {
|
||||
source = _fpu_read_ea(M, source_specifier);
|
||||
if (shoe.abort)
|
||||
return ;
|
||||
}
|
||||
else
|
||||
source = floatx80_to_float128(fpu->fp[source_specifier]);
|
||||
|
||||
float128 dest = floatx80_to_float128(fpu->fp[dest_register]);
|
||||
|
||||
|
||||
assert(!"fmath");
|
||||
}
|
||||
|
||||
static void inst_fmove (const uint16_t ext)
|
||||
{
|
||||
assert(!"fmove");
|
||||
}
|
||||
|
||||
static void inst_fmovem_control (const uint16_t ext)
|
||||
{
|
||||
assert(!"fmovem_control");
|
||||
}
|
||||
|
||||
static void inst_fmovem (const uint16_t ext)
|
||||
{
|
||||
assert(!"fmovem");
|
||||
}
|
||||
|
||||
|
||||
#pragma mark First-hop decoder table inst implementations
|
||||
/*
|
||||
* The table generated by decoder_gen.c will refer directly
|
||||
* to these instructions. inst_fpu_other() will handle all
|
||||
* other FPU instructions.
|
||||
*/
|
||||
|
||||
static _Bool fpu_test_cc(uint8_t cc)
|
||||
{
|
||||
fpu_get_state_ptr();
|
||||
const _Bool z = cc_z;
|
||||
const _Bool n = cc_n;
|
||||
const _Bool nan = cc_nan;
|
||||
|
||||
switch (cc & 0x0f) {
|
||||
case 0: // false
|
||||
return 0;
|
||||
case 1: // equal
|
||||
return z;
|
||||
case 2: // greater than
|
||||
return !(nan | z | n);
|
||||
case 3: // greater than or equal
|
||||
return z | !(nan | n);
|
||||
case 4: // less than
|
||||
return n & !(nan | z);
|
||||
case 5: // less than or equal
|
||||
return z | (n & !nan);
|
||||
case 6: // greater or less than
|
||||
return !(nan | z);
|
||||
case 7: // ordered
|
||||
return !nan;
|
||||
case 8: // unordered
|
||||
return nan;
|
||||
case 9: // not (greater or less than)
|
||||
return nan | z;
|
||||
case 10: // not (less than or equal)
|
||||
return nan | !(n | z);
|
||||
case 11: // not (less than)
|
||||
return nan | (z | !n);
|
||||
case 12: // not (greater than or equal)
|
||||
return nan | (n & !z);
|
||||
case 13: // not (greater than)
|
||||
return nan | z | n;
|
||||
case 14: // not equal
|
||||
return !z;
|
||||
case 15: // true
|
||||
return 1;
|
||||
}
|
||||
|
||||
assert(0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void inst_fscc () {
|
||||
fpu_get_state_ptr();
|
||||
|
||||
// fscc can throw an exception
|
||||
fpu->fpiar = shoe.orig_pc;
|
||||
|
||||
const uint16_t ext = nextword();
|
||||
|
||||
~decompose(shoe.op, 1111 001 001 MMMMMM);
|
||||
~decompose(ext, 0000 0000 000 b cccc);
|
||||
|
||||
/*
|
||||
* inst_f*cc instructions throw a pre-instruction exception
|
||||
* if b && cc_nan
|
||||
*/
|
||||
if (b && _bsun_test())
|
||||
return ;
|
||||
|
||||
shoe.dat = fpu_test_cc(c) ? 0xff : 0;
|
||||
|
||||
call_ea_write(M, 1);
|
||||
}
|
||||
|
||||
void inst_fbcc () {
|
||||
fpu_get_state_ptr();
|
||||
|
||||
// fbcc can throw an exception
|
||||
fpu->fpiar = shoe.orig_pc;
|
||||
|
||||
~decompose(shoe.op, 1111 001 01 s 0bcccc); // b => raise BSUN if NaN
|
||||
const uint8_t sz = 2 << s;
|
||||
|
||||
/*
|
||||
* inst_f*cc instructions throw a pre-instruction exception
|
||||
* if b && cc_nan
|
||||
*/
|
||||
if (b && _bsun_test())
|
||||
return ;
|
||||
|
||||
if (fpu_test_cc(c)) {
|
||||
const uint16_t ext = nextword();
|
||||
uint32_t displacement;
|
||||
|
||||
if (s) {
|
||||
const uint16_t ext2 = nextword();
|
||||
displacement = (ext << 16) | ext2;
|
||||
}
|
||||
else
|
||||
displacement = (int16_t)ext;
|
||||
|
||||
shoe.pc = shoe.orig_pc + 2 + displacement;
|
||||
}
|
||||
else
|
||||
shoe.pc += sz;
|
||||
}
|
||||
|
||||
void inst_fsave () {
|
||||
fpu_get_state_ptr();
|
||||
verify_supervisor();
|
||||
|
||||
// Don't modify fpiar for fsave
|
||||
|
||||
~decompose(shoe.op, 1111 001 100 MMMMMM);
|
||||
~decompose(shoe.op, 1111 001 100 mmmrrr);
|
||||
|
||||
const uint32_t size = 0x1c; // IDLE frame
|
||||
const uint16_t frame_header = 0xfd18;
|
||||
uint32_t addr;
|
||||
|
||||
if (m == 4)
|
||||
addr = shoe.a[r] - size;
|
||||
else {
|
||||
call_ea_addr(M);
|
||||
addr = shoe.dat;
|
||||
}
|
||||
|
||||
lset(addr, 2, frame_header);
|
||||
if (shoe.abort)
|
||||
return ;
|
||||
|
||||
if (m == 4)
|
||||
shoe.a[r] = addr;
|
||||
|
||||
}
|
||||
|
||||
void inst_frestore () {
|
||||
fpu_get_state_ptr();
|
||||
verify_supervisor();
|
||||
|
||||
// Don't modify fpiar for frestore
|
||||
|
||||
~decompose(shoe.op, 1111 001 101 MMMMMM);
|
||||
~decompose(shoe.op, 1111 001 101 mmmrrr);
|
||||
|
||||
uint32_t addr, size;
|
||||
|
||||
if (m == 3)
|
||||
addr = shoe.a[r];
|
||||
else {
|
||||
call_ea_addr(M);
|
||||
addr = shoe.dat;
|
||||
}
|
||||
|
||||
const uint16_t word = lget(addr, 2);
|
||||
if (shoe.abort) return ;
|
||||
|
||||
// XXX: These frame sizes are different on 68881/68882/68040
|
||||
if ((word & 0xff00) == 0x0000)
|
||||
size = 4; // NULL state frame
|
||||
else if ((word & 0xff) == 0x0018)
|
||||
size = 0x1c; // IDLE state frame
|
||||
else if ((word & 0xff) == 0x00b4)
|
||||
size = 0xb8; // BUSY state frame
|
||||
else {
|
||||
slog("Frestore encountered an unknown state frame 0x%04x\n", word);
|
||||
assert("inst_frestore: bad state frame");
|
||||
return ;
|
||||
}
|
||||
|
||||
if (m==3) {
|
||||
shoe.a[r] += size;
|
||||
slog("frestore: changing shoe.a[%u] += %u\n", r, size);
|
||||
}
|
||||
}
|
||||
|
||||
void inst_fdbcc () {
|
||||
fpu_get_state_ptr();
|
||||
~decompose(shoe.op, 1111 001 001 001 rrr);
|
||||
|
||||
// fdbcc can throw an exception
|
||||
fpu->fpiar = shoe.orig_pc;
|
||||
|
||||
const uint16_t ext = nextword();
|
||||
~decompose(ext, 0000 0000 000 b cccc);
|
||||
|
||||
/*
|
||||
* inst_f*cc instructions throw a pre-instruction exception
|
||||
* if b && cc_nan
|
||||
*/
|
||||
if (b && _bsun_test())
|
||||
return ;
|
||||
|
||||
if (fpu_test_cc(c)) {
|
||||
shoe.pc += 2;
|
||||
}
|
||||
else {
|
||||
const int16_t disp = nextword();
|
||||
const uint16_t newd = get_d(r, 2) - 1;
|
||||
set_d(r, newd, 2);
|
||||
if (newd != 0xffff)
|
||||
shoe.pc = shoe.orig_pc + 2 + disp;
|
||||
}
|
||||
}
|
||||
|
||||
void inst_ftrapcc () {
|
||||
fpu_get_state_ptr();
|
||||
~decompose(shoe.op, 1111 001 001 111 xyz);
|
||||
|
||||
// ftrapcc can throw an exception
|
||||
fpu->fpiar = shoe.orig_pc;
|
||||
|
||||
// (xyz) == (100) -> sz=0
|
||||
// (xyz) == (010) -> sz=2
|
||||
// (xyz) == (011) -> sz=4
|
||||
const uint32_t sz = y << (z+1);
|
||||
const uint32_t next_pc = shoe.orig_pc + 2 + sz;
|
||||
|
||||
const uint16_t ext = nextword();
|
||||
~decompose(ext, 0000 0000 000 b cccc);
|
||||
|
||||
/*
|
||||
* inst_f*cc instructions throw a pre-instruction exception
|
||||
* if b && cc_nan
|
||||
*/
|
||||
if (b && _bsun_test())
|
||||
return ;
|
||||
|
||||
if (fpu_test_cc(c))
|
||||
throw_frame_two(shoe.sr, next_pc, 7, shoe.orig_pc);
|
||||
else
|
||||
shoe.pc = next_pc;
|
||||
}
|
||||
|
||||
void inst_fnop() {
|
||||
// This is technically fbcc, so we should set fpiar too
|
||||
fpu->fpiar = shoe.orig_pc;
|
||||
}
|
||||
|
||||
void inst_fpu_other () {
|
||||
fpu_get_state_ptr();
|
||||
~decompose(shoe.op, 1111 001 000 MMMMMM);
|
||||
|
||||
const uint16_t ext = nextword();
|
||||
~decompose(ext, ccc xxx yyy eeeeeee);
|
||||
|
||||
switch (c) {
|
||||
case 0: // Reg to reg
|
||||
fpu->fpiar = shoe.orig_pc; // fmath() can throw an exception
|
||||
inst_fmath(ext);
|
||||
return;
|
||||
|
||||
case 1: // unused
|
||||
throw_illegal_instruction();
|
||||
return;
|
||||
|
||||
case 2: // Memory->reg & movec
|
||||
fpu->fpiar = shoe.orig_pc; // fmath() can throw an exception
|
||||
inst_fmath(ext);
|
||||
return;
|
||||
|
||||
case 3: // reg->mem
|
||||
fpu->fpiar = shoe.orig_pc; // fmove() can throw an exception
|
||||
inst_fmove(ext);
|
||||
return;
|
||||
|
||||
case 4: // mem -> sys ctl registers
|
||||
case 5: // sys ctl registers -> mem
|
||||
// fmovem_control() cannot throw an FPU exception (don't modify fpiar)
|
||||
inst_fmovem_control(ext);
|
||||
return;
|
||||
|
||||
case 6: // movem to fp registers
|
||||
case 7: // movem to memory
|
||||
// fmovem() cannot throw an FPU exception (don't modify fpiar)
|
||||
inst_fmovem(ext);
|
||||
return;
|
||||
}
|
||||
|
||||
assert(0); // never get here
|
||||
return;
|
||||
}
|
||||
|
||||
#pragma mark FPU-state initialization and reset
|
||||
|
||||
void fpu_initialize()
|
||||
{
|
||||
fpu_state_t *fpu = (fpu_state_t*)p_alloc(shoe.pool, sizeof(fpu_state_t));
|
||||
memset(fpu, sizeof(fpu_state_t), 0);
|
||||
shoe.fpu_state = fpu;
|
||||
}
|
||||
|
||||
void fpu_reset()
|
||||
{
|
||||
p_free(shoe.fpu_state);
|
||||
fpu_initialize();
|
||||
}
|
Loading…
Reference in New Issue