mirror of
https://github.com/ctm/syn68k.git
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284 lines
7.8 KiB
C
284 lines
7.8 KiB
C
#include "syn68k_private.h"
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#include "block.h"
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#include "mapping.h"
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#include "rangetree.h"
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#include "blockinfo.h"
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#include "alloc.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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static void determine_next_block_addresses (const uint16 *code,
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TempBlockInfo *temp,
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const OpcodeMappingInfo *map);
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/* This function takes a block and a pointer to some m68k code and computes
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* the length of the block and various cc bit information about the block.
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* The info is stored in the block struct.
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*/
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void
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compute_block_info (Block *b, const uint16 *code, TempBlockInfo *temp)
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{
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const uint16 *start_code = code, *old_code;
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int clobbered = 0, may_set = 0, may_not_set = ALL_CCS, needed = 0;
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int next_array_size;
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const OpcodeMappingInfo *map = NULL;
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/* Initialize the next offset array. This lets us step through this
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* code forwards when we actually get around to compiling it.
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*/
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temp->num_68k_instrs = 0;
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next_array_size = 16;
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temp->next_instr_offset = (int8 *) xmalloc (next_array_size * sizeof (int8));
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/* Loop over all instructions in the block and determine information
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* about how this block deals with CC bits.
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*/
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old_code = code;
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do
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{
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int insn_size;
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unsigned m68k_op;
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m68k_op = READUW (US_TO_SYN68K (code));
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map = &opcode_map_info[opcode_map_index[m68k_op]];
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#if 0
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if (opcode_map_index[m68k_op] == 0)
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{
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fprintf (stderr, "m68kop 0x%04X unimplemented!\n", m68k_op);
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abort ();
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}
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#endif
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insn_size = instruction_size (code, map);
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if (insn_size <= 0)
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{
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map = &opcode_map_info[opcode_map_index[0x4AFC]]; /* illegal */
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insn_size = 1;
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}
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/* Update cc bit info for this block. */
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clobbered |= (map->cc_may_set
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& ~(map->cc_may_not_set | map->cc_needed | needed));
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needed |= map->cc_needed & may_not_set;
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may_set |= map->cc_may_set;
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may_not_set &= map->cc_may_not_set;
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/* Grow next instruction offset array iff necessary. We'll
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* leave one extra element for after this loop ends.
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*/
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if (temp->num_68k_instrs >= next_array_size - 1)
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{
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next_array_size *= 2;
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temp->next_instr_offset = (int8 *) xrealloc (temp->next_instr_offset,
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next_array_size
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* sizeof (int8));
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}
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/* Remember offset to next instruction. */
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temp->next_instr_offset[temp->num_68k_instrs++] = insn_size;
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/* Move on to the next instruction. */
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old_code = code;
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code += insn_size;
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}
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while (!map->ends_block);
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/* Terminate the array with a 0 offset. */
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temp->next_instr_offset[temp->num_68k_instrs] = 0;
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/* Figure out where this block goes (if possible). */
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determine_next_block_addresses (old_code, temp, map);
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/* Record the block information we've computed. */
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b->cc_clobbered = clobbered;
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b->cc_may_not_set = may_not_set;
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b->cc_needed = needed;
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b->m68k_start_address = US_TO_SYN68K (start_code);
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b->m68k_code_length = (code - start_code) * sizeof (uint16);
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}
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static void
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determine_next_block_addresses (const uint16 *code, TempBlockInfo *temp,
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const OpcodeMappingInfo *map)
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{
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uint16 m68kop = READUW (US_TO_SYN68K (code));
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BOOL is_bsr = ((m68kop >> 8) == 0x61);
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BOOL is_fixed_jsr = ((m68kop & 0xFFFE) == 0x4EB8 /* jsr abs{w,l}? */
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|| m68kop == 0x4EBA); /* jsr pc@d16? */
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#ifdef DEBUG
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temp->child[0] = temp->child[1] = US_TO_SYN68K (NULL);
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#endif
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/* First see if we can even tell where the child block is. */
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if (map->next_block_dynamic && !is_bsr && !is_fixed_jsr)
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{
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temp->num_child_blocks = 0;
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return;
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}
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/* Is it a Bcc? */
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if ((m68kop >> 12) == 6)
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{
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uint32 t1, t2;
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t1 = (uint32) (code + 1);
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/* Compute branch target. */
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if ((m68kop & 0xFF) == 0)
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{
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t1 += READSW (US_TO_SYN68K (code + 1));
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t2 = (uint32) (code + 2);
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}
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else if ((m68kop & 0xFF) == 0xFF)
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{
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t1 += READSL (US_TO_SYN68K (code + 1));
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t2 = (uint32) (code + 3);
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}
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else
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{
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t1 += ((int8 *)code)[1];
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t2 = (uint32) (code + 1);
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}
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/* Is it a bsr or bra? If so, only one destination address. In the
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* case of bsr, we compute the target address but officially pretend
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* we don't know where it's going.
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*/
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if ((m68kop & 0xFE00) == 0x6000)
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{
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temp->child[0] = t1;
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temp->num_child_blocks = !is_bsr;
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return;
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}
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temp->child[0] = t2;
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temp->child[1] = t1;
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temp->num_child_blocks = 2;
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return;
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}
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/* Is it a dbcc? */
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if ((m68kop >> 12) == 5)
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{
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temp->child[0] = (uint32) (code + 2);
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if ((m68kop >> 8) == 0x50) /* dbt? */
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{
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temp->num_child_blocks = 1;
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return;
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}
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temp->child[1] = ((int32 ) (code + 1)
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+ READSW (US_TO_SYN68K (code + 1)));
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temp->num_child_blocks = 2;
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return;
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}
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switch (m68kop)
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{
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case 0x4EF8: /* Is it a jmp _abs.w? */
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temp->child[0] =
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(uint32) SYN68K_TO_US (READSW (US_TO_SYN68K (code + 1)));
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temp->num_child_blocks = 1;
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return;
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case 0x4EB8: /* Is it a jsr _abs.w? */
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temp->child[0] =
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(uint32) SYN68K_TO_US (READSW (US_TO_SYN68K (code + 1)));
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temp->num_child_blocks = 0; /* Pretend we don't know the dest. */
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return;
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case 0x4EF9: /* Is it a jmp _abs.l? */
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temp->child[0] =
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(uint32) SYN68K_TO_US (READUL (US_TO_SYN68K (code + 1)));
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temp->num_child_blocks = 1;
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return;
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case 0x4EB9: /* Is it a jsr _abs.l? */
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temp->child[0] =
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(uint32) SYN68K_TO_US (READUL (US_TO_SYN68K (code + 1)));
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temp->num_child_blocks = 0;
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return;
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case 0x4EBA: /* Is it a pc-relative jsr? */
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temp->child[0] = (uint32) ((READSW (US_TO_SYN68K (code + 1))
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+ code + 1));
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temp->num_child_blocks = 0;
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return;
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}
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/* Strange, unknown block ender. Probably something capable of trapping.
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* Assume that the subsequent instruction is the target.
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*/
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temp->child[0] = (uint32) (code + map->instruction_words);
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temp->num_child_blocks = 1;
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}
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int
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amode_size (int amode, const uint16 *code, int ref_size)
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{
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uint16 c = READUW (US_TO_SYN68K (code));
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switch (amode) {
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case 0x28: case 0x29: case 0x2A: case 0x2B: /* Addressing mode 5 */
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case 0x2C: case 0x2D: case 0x2E: case 0x2F:
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return 1;
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case 0x38: /* 111/000 (xxx).W */
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return 1;
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case 0x39: /* 111/001 (xxx).L */
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return 2;
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case 0x3C: /* 111/100 #<data> */
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return ref_size == 4 ? 2 : 1; /* Bytes still take 1 full word. */
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case 0x30: case 0x31: case 0x32: case 0x33: /* Addressing mode 6. */
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case 0x34: case 0x35: case 0x36: case 0x37:
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case 0x3B: /* Addressing mode 111/011 */
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if (!(c & 0x100)) /* 8 bit displacement. */
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return 1;
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else if ((c & 0xF) == 0x0)
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return ((c >> 4) & 3);
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return ((c >> 4) & 3) + (c & 3) - 1;
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case 0x3A: /* 111/010 (d16,PC) */
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return 1;
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default:
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return 0;
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}
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}
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/* Given a pointer to an m68k opcode, returns the total number of words
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* that instruction occupies, including operands and memory taken by
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* complex addressing modes.
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*/
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int
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instruction_size (const uint16 *code, const OpcodeMappingInfo *map)
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{
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int size;
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int m68kop = READUW (US_TO_SYN68K (code));
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/* See if we have a conditional branch format operand instruction. */
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if ((m68kop >> 12) == 6)
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{
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if ((m68kop & 0xFF) == 0)
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size = 2;
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else if ((m68kop & 0xFF) == 0xFF)
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size = 3;
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else
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size = 1;
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}
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else
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{
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size = map->instruction_words;
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/* If we have an addressing mode, compute how many words it takes. */
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if (map->amode_size != 0)
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size += amode_size (m68kop & 0x3F, code + size, map->amode_size);
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/* If we have a rev. addressing mode, compute how many words it takes. */
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if (map->reversed_amode_size != 0) /* Is there a rev. addressing mode? */
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size += amode_size (((m68kop >> 9) & 0x7) | ((m68kop >> 3) & 0x38),
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code + size, map->reversed_amode_size);
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}
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return size;
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}
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