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301 lines
8.6 KiB
C
301 lines
8.6 KiB
C
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/*
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VIAEMDEV.c
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Copyright (C) 2020 InvisibleUp
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You can redistribute this file and/or modify it under the terms
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of version 2 of the GNU General Public License as published by
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the Free Software Foundation. You should have received a copy
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of the license along with this file; see the file COPYING.
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This file is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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license for more details.
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*/
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/*
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Versatile Interface Adapter EMulated DEVice
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Emulates the Synertek SY6522 VIA found up until the Mac Plus.
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This code rewritten for target-independance and non-enum based config
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The VIA1 contains the following functionality:
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- Two timers (1 and 2)
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- Serial-to-parallel / parallel-to-serial bi-directional shift register
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- Two 8-bit bi-directional ports (A and B)
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- Ports are per-line settable to input or output
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- Square wave generation
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- Pulse counting
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The M68000 addresses the VIA simply via an interrupt line and a pair of
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registers, much like any other peripheal
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Because just about everything on the Mac is attached to a VIA, it's
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important to track what device is mapped to what line on what port.
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Summary of SY6522 pins:
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1. Phase 2 Clock (Φ2)
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Must be high for data transfer from M68k to occur
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Time base for timers, shift registers, etc.
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2. Chip select (CS1, ¬CS2)
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is a chip select line
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3. Register Select (RS0, RS1, RS2, RS3)
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Name Write Read
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0000 - ORB, IRB Port B output Port B input
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0001 - ORA, IRA Port A output Port A input
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0010 - DDRB Data Direction, port B
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0011 - DDRA Data Direction, port A
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0100 - T1L-L T1 Low-Order Latches T1 Low-Order Counter
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0101 - T1C-H T1 High-Order Counter
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0110 - T1L-L T1 Low-Order Latches
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0111 - T1L-H T1 High-Order Latches
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1000 - T2C-L T2 Low-Order Latches T2 Low-Order Counter
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1001 - T2C-H T2 High-Order Counter
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1010 - SR Shift Register
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1011 - ACR Auxillary Control Register
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1100 - PCR Peripheal Control Register
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1101 - IFR Interrupt flag
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1110 - IER Interrupt enable
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1111 - ORA Same as 0001 but no effect on handshake
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4. Read/Write line
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If low, write (processor to VIA register)
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If high, read (VIA register to processor)
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5. Data Bus (DB0-7)
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Transfers data between VIA and M68l
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6. Reset
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Clears all registers to 0.
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All I/O set to input, disablse timers, SR, interrupts, etc.
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7. IRQ
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8. Peripheal A Port (PA0 - PA7)
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8 lines. Each can be input or output, depending on value of DDRA
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9. Port A Control Lines (CA1/CA2)
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Interrupt inputs or handshake outputs
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Each line controls an internal interrupt flag w/ enable bit
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CA1 controls latching of data on P1 input
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10. Peripheal Port B (PB0 - PB7)
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Same as Port A, with timers!
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PB7 polarity can be controller by timer
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PB6 can count pulses w/ second timer
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11. Port B control lines (CB1/CB2)
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Same as CA
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Shift register serial I/O goes through one of these
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I'm not going to bother to emulate handshaking
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "VIAEMDEV.h"
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/* Global state */
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typedef struct {
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uint8_t PortA_data; // Port A data
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uint8_t PortA_dir; // Direction of Port A bits (0 = in, 1 = out)
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uint8_t PortB_data; // Port A data
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uint8_t PortB_dir; // Direction of Port B bits (0 = in, 1 = out)
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uint8_t SR; // current shift register state
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uint16_t T1_C; // timer 1 count
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uint16_t T1_L; // timer 1 latches
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uint16_t T2_C; // timer 2 count
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uint16_t T2_L; // timer 2 latches
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uint8_t AUX_T1; // Aux - Timer 1 Control (0-3)
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uint8_t AUX_T2; // Aux - Timer 2 Control (0-1)
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uint8_t AUX_SR; // Aux - SR Control (0-7)
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bool AUX_PALE; // Aux - Port A Latch Enable (0-1)
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bool AUX_PBLE; // Aux - Port B Latch Enable (0-1)
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uint8_t PC_CB2; // Perip. - CB2 Control
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uint8_t PC_CB1; // Perip. - CB1 Edge Polarity (0 = -, 1 = +)
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uint8_t PC_CA2; // Perip. - CA2 Control
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uint8_t PC_CA1; // Perip. - CA1 Edge Polarity (0 = -, 1 = +)
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uint8_t IF; // Interrupt Flags
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uint8_t IE; // Interrupt Enable
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} VIA1_State_t;
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VIA1_State_t VIA1_State = {0};
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/*
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For reference: Mac 128/512k port allocations:
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PA7 (I ) SCC ready for read
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PA6 ( O) Alt. screen buffer in use?
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PA5 ( O) Disk SEL line
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PA4 ( O) ROM low-mem overlay
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PA3 ( O) Alt. sound buffer
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PA0-2 ( O) Sound volume
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PB7 ( O) Sound on/off
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PB6 (I ) Horiz. Blank
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PB5 (I ) Mouse Y2
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PB4 (I ) Mouse X2
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PB3 (I ) Mouse button
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PB2 ( O) RTC serial enable
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RB1 ( O) RTC data-clock line
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RB0 (IO) RTC clock serial data
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SR - Keyboard data line
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Timer 1 - Sound generator stuff
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Timer 2 - Disk I/O events
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(or both can be for your own use!)
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IRQ7 - IRQ (all enabled VIA interrupts)
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IRQ6 - Timer 1
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IRQ5 - Timer 2
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IRQ4 - Keyboard clock
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IRQ3 - Keyboard data bit
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IRQ2 - Keyboard data ready
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IRQ1 - VBlank
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IRQ0 - One-second interrupt from RTC
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*/
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// Hardware reset
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void VIA1_Zap(void) {
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memset(&VIA1_State, 0, sizeof(VIA1_State));
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}
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// Software reset
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void VIA1_Reset(void) {
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VIA1_Zap();
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}
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// Write to a register
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void VIA1_Write(uint8_t reg, uint8_t data)
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{
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switch(reg) {
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case 0: // Port B data
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VIA1_State.PortB_data = data;
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break;
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case 1: // Port A data
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case 15:
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VIA1_State.PortA_data = data;
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break;
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case 2: // Port B direction
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VIA1_State.PortB_dir = data;
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break;
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case 3: // Port A direction
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VIA1_State.PortA_dir = data;
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break;
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case 4: // Timer 1 Low-Order Counter
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case 6: // Timer 1 Low-Order Latches
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VIA1_State.T1_L &= 0xFF00 | data;
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break;
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case 5: // Timer 1 High-Order Counter
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VIA1_State.T1_L &= 0x00FF | (data << 8);
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VIA1_State.T1_C = VIA1_State.T1_L;
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VIA1_State.IF &= 0b10111111;
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break;
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case 7: // Timer 1 High-Order Latches
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VIA1_State.T1_L &= 0x00FF | (data << 8);
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break;
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case 8: // Timer 1 Low-Order Counter
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VIA1_State.T2_L &= 0xFF00 | data;
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break;
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case 9: // Timer 2 High-Order Counter
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VIA1_State.T2_L &= 0x00FF | (data << 8);
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VIA1_State.T2_C = VIA1_State.T2_L;
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VIA1_State.IF &= 0b10111111;
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break;
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case 10:
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VIA1_State.SR = data;
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break;
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case 11:
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VIA1_State.AUX_T1 = (data & 0b11000000) >> 6;
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VIA1_State.AUX_T2 = (data & 0b00100000) >> 5;
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VIA1_State.AUX_SR = (data & 0b00011100) >> 2;
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VIA1_State.AUX_PBLE = (data & 0b00000010) >> 1;
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VIA1_State.AUX_PALE = (data & 0b00000001) >> 0;
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break;
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case 12:
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VIA1_State.PC_CB2 = (data & 0b11100000) >> 5;
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VIA1_State.PC_CB1 = (data & 0b00010000) >> 4;
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VIA1_State.PC_CA2 = (data & 0b00001110) >> 1;
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VIA1_State.PC_CA1 = (data & 0b00000001) >> 0;
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break;
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case 13: // Interrupt Flag
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VIA1_State.IF = data;
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break;
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case 14: // Interrupt Enable
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VIA1_State.IE = data;
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break;
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}
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}
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// Read to a register
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uint8_t VIA1_Read(uint8_t reg)
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{
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switch(reg) {
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case 0: // Port B data (technically incorrect but meh)
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return VIA1_State.PortB_data & ~VIA1_State.PortB_dir;
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case 1: // Port A data
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case 15:
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return VIA1_State.PortA_data & ~VIA1_State.PortA_dir;
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case 2: // Port B direction
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return VIA1_State.PortB_dir;
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case 3: // Port A direction
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return VIA1_State.PortA_dir;
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case 4: // Timer 1 Low-Order Counter
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VIA1_State.IF &= 0b10111111;
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return (VIA1_State.T1_C & 0xFF00);
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case 5: // Timer 1 High-Order Counter
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return (VIA1_State.T1_C & 0x00FF) >> 8;
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case 6: // Timer 1 Low-Order Latches
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return (VIA1_State.T1_L & 0xFF00);
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case 7: // Timer 1 High-Order Latches
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return (VIA1_State.T1_L & 0x00FF) >> 8;
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case 8: // Timer 2 Low-Order Counter
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VIA1_State.IF &= 0b11011111;
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return (VIA1_State.T2_C & 0xFF00);
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case 9: // Timer 2 High-Order Counter
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return (VIA1_State.T2_C & 0x00FF) >> 8;
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case 10:
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return VIA1_State.SR;
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case 11:
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return (
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(VIA1_State.AUX_T1 << 6) |
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(VIA1_State.AUX_T2 << 5) |
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(VIA1_State.AUX_SR << 2) |
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(VIA1_State.AUX_PBLE << 1) |
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(VIA1_State.AUX_PALE << 0)
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);
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case 12:
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return (
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(VIA1_State.PC_CB2 << 5) |
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(VIA1_State.PC_CB1 << 4) |
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(VIA1_State.PC_CA2 << 1) |
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(VIA1_State.PC_CA1 << 0)
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);
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case 13: // Interrupt Flag
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return VIA1_State.IF;
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break;
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case 14: // Interrupt Enable
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return VIA1_State.IE;
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break;
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default:
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return 0;
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}
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}
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// Tick timers
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void VIA1_Tick() {
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}
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// Shift in one byte of data to keyboard shift register
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void VIA1_ShiftInData(uint8_t v)
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{
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VIA1_State.SR = v;
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// somehow signal to keyboard that we're ready
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}
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// Shift out one byte of data from keyboard shift register
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uint8_t VIA1_ShiftOutData(void)
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{
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// signal to keyboard to get new data?
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return VIA1_State.SR;
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}
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