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Update PCB component layout

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This commit is contained in:
Terence Boldt 2020-11-16 19:21:56 -05:00
parent be0cae809a
commit ecba35fefe
8 changed files with 75883 additions and 558 deletions
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1
.gitignore vendored
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@ -1,2 +1 @@
fp-info-cache
*-bak *-bak

0
Hardware/Hardware.pretty/Apple II Expansion Edge Connector.kicad_mod → Hardware/Apple2.pretty/Apple II Expansion Edge Connector.kicad_mod
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Hardware/Apple2IORPi.jpg
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1127
Hardware/Apple2IORPi.kicad_pcb
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44
Hardware/Apple2IORPi.pro
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@ -1,4 +1,4 @@
update=Thu 12 Nov 2020 09:17:33 PM update=Mon 16 Nov 2020 05:12:41 PM
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
@ -32,15 +32,15 @@ AllowMicroVias=0
AllowBlindVias=0 AllowBlindVias=0
RequireCourtyardDefinitions=0 RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1 ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2 MinTrackWidth=0.1778
MinViaDiameter=0.4 MinViaDiameter=0.4
MinViaDrill=0.3 MinViaDrill=0.3
MinMicroViaDiameter=0.2 MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999 MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25 MinHoleToHole=0.25
TrackWidth1=0.25 TrackWidth1=0.1778
ViaDiameter1=0.8 ViaDiameter1=0.762
ViaDrill1=0.4 ViaDrill1=0.50038
dPairWidth1=0.2 dPairWidth1=0.2
dPairGap1=0.25 dPairGap1=0.25
dPairViaGap1=0.25 dPairViaGap1=0.25
@ -67,7 +67,7 @@ OthersTextUpright=1
SolderMaskClearance=0.051 SolderMaskClearance=0.051
SolderMaskMinWidth=0.25 SolderMaskMinWidth=0.25
SolderPasteClearance=0 SolderPasteClearance=0
SolderPasteRatio=0 SolderPasteRatio=-0
[pcbnew/Layer.F.Cu] [pcbnew/Layer.F.Cu]
Name=F.Cu Name=F.Cu
Type=0 Type=0
@ -233,14 +233,36 @@ Enabled=1
[pcbnew/Layer.F.Fab] [pcbnew/Layer.F.Fab]
Enabled=1 Enabled=1
[pcbnew/Layer.Rescue] [pcbnew/Layer.Rescue]
Enabled=1 Enabled=0
[pcbnew/Netclasses] [pcbnew/Netclasses]
[pcbnew/Netclasses/Default] [pcbnew/Netclasses/Default]
Name=Default Name=Default
Clearance=0.2 Clearance=0.1778
TrackWidth=0.25 TrackWidth=0.1778
ViaDiameter=0.8 ViaDiameter=0.762
ViaDrill=0.4 ViaDrill=0.50038
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Ground
Clearance=0.254
TrackWidth=0.8128
ViaDiameter=0.762
ViaDrill=0.7112
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=Power
Clearance=0.254
TrackWidth=0.8128
ViaDiameter=0.762
ViaDrill=0.7112
uViaDiameter=0.3 uViaDiameter=0.3
uViaDrill=0.1 uViaDrill=0.1
dPairWidth=0.2 dPairWidth=0.2

2
Hardware/Apple2IORPi.sch
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@ -19,7 +19,7 @@ U 1 1 5FA0A8C3
P 3000 2700 P 3000 2700
F 0 "J0" H 3050 4117 50 0000 C CNN F 0 "J0" H 3050 4117 50 0000 C CNN
F 1 "Apple II Expansion Bus" H 3050 4026 50 0000 C CNN F 1 "Apple II Expansion Bus" H 3050 4026 50 0000 C CNN
F 2 "Hardware:Apple II Expansion Edge Connector" H 3000 2700 50 0001 C CNN F 2 "Apple2:Apple II Expansion Edge Connector" H 3000 2700 50 0001 C CNN
F 3 "~" H 3000 2700 50 0001 C CNN F 3 "~" H 3000 2700 50 0001 C CNN
1 3000 2700 1 3000 2700
1 0 0 -1 1 0 0 -1

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Hardware/fp-info-cache Normal file
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Hardware/fp-lib-table
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(fp_lib_table (fp_lib_table
(lib (name Hardware)(type KiCad)(uri /home/terence/source/Apple2-IO-RPi/Hardware/Hardware.pretty)(options "")(descr "")) (lib (name Apple2)(type KiCad)(uri /home/terence/source/Apple2-IO-RPi/Hardware/Apple2.pretty)(options "")(descr ""))
) )