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This commit is contained in:
freitz85 2017-07-05 19:41:29 +02:00
parent cb9891374f
commit c4d43389c4
4 changed files with 11 additions and 11 deletions
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0
VHDL/address_decoder.sch → VHDL/AddressDecoder.sch
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10
VHDL/spi65.npl → VHDL/AppleIISd.npl
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@ -1,7 +1,7 @@
JDF G JDF G
// Created by Project Navigator ver 1.0 // Created by Project Navigator ver 1.0
PROJECT spi65 PROJECT AppleIISd
DESIGN spi65 DESIGN appleiisd
DEVFAM xc9500xl DEVFAM xc9500xl
DEVFAMTIME 0 DEVFAMTIME 0
DEVICE xc9572xl DEVICE xc9572xl
@ -18,8 +18,8 @@ DEVSIMULATOR Other
SIMULATORTIME 0 SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0 GENERATEDSIMULATIONMODELTIME 0
SOURCE SPI6502B1.1.vhd SOURCE AppleIISd.vhd
SOURCE address_decoder.sch SOURCE AddressDecoder.sch
DEPASSOC spi6502b SPI6502B.ucf DEPASSOC appleiisd AppleIISd.ucf
[STRATEGY-LIST] [STRATEGY-LIST]
Normal=True Normal=True

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VHDL/SPI6502B.ucf → VHDL/AppleIISd.ucf
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12
VHDL/SPI6502B1.1.vhd → VHDL/AppleIISd.vhd
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@ -33,7 +33,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
use address_decoder.ALL; use AddressDecoder.ALL;
-- Uncomment the following library declaration if using -- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values -- arithmetic functions with Signed or Unsigned values
@ -45,7 +45,7 @@ use address_decoder.ALL;
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity SPI6502B is entity AppleIISd is
Port ( cpu_d : inout STD_LOGIC_VECTOR (7 downto 0); Port ( cpu_d : inout STD_LOGIC_VECTOR (7 downto 0);
@ -77,9 +77,9 @@ entity SPI6502B is
constant DIV_WIDTH : integer := 3; constant DIV_WIDTH : integer := 3;
end SPI6502B; end AppleIISd;
architecture Behavioral of SPI6502B is architecture Behavioral of AppleIISd is
-- interface signals -- interface signals
signal selected: std_logic; signal selected: std_logic;
@ -130,7 +130,7 @@ architecture Behavioral of SPI6502B is
signal shiftclk : std_logic; signal shiftclk : std_logic;
component address_decoder component AddressDecoder
port ( A8 : in std_logic; port ( A8 : in std_logic;
A9 : in std_logic; A9 : in std_logic;
A10 : in std_logic; A10 : in std_logic;
@ -144,7 +144,7 @@ architecture Behavioral of SPI6502B is
end component; end component;
begin begin
add_dec : address_decoder add_dec : AddressDecoder
port map (A8=>a8, port map (A8=>a8,
A9=>a9, A9=>a9,
A10=>a10, A10=>a10,