From f685f98029c3a1b27e33d80d7454158cb1e144cc Mon Sep 17 00:00:00 2001
From: freitz85 <freitz85@gmail.com>
Date: Wed, 5 Jul 2017 19:22:02 +0200
Subject: [PATCH] address decoder added

---
 .gitignore                                    |  120 +-
 .untf                                         |    0
 SPI6502B.lfp                                  |   15 +-
 SPI6502B.ucf                                  |   14 +-
 SPI6502B1.1.vhd                               |   45 +-
 _ngo/netlist.lst                              |    2 +-
 _pace.ucf                                     |   71 +-
 address_decoder._u_                           |    0
 address_decoder.lfp                           |   15 +
 address_decoder.sch                           |  240 ++
 address_decoder.ucf                           |   19 +
 address_decoder.vhf                           |  288 ++
 address_decoder_html/fit/applet.js            |  128 +
 address_decoder_html/fit/appletref.htm        |   15 +
 address_decoder_html/fit/asciidoc.htm         |   71 +
 address_decoder_html/fit/backtop.jpg          |  Bin 0 -> 1651 bytes
 address_decoder_html/fit/beginstraight.gif    |  Bin 0 -> 352 bytes
 address_decoder_html/fit/blank.gif            |  Bin 0 -> 43 bytes
 address_decoder_html/fit/blank.htm            |    1 +
 address_decoder_html/fit/briefview.jpg        |  Bin 0 -> 1254 bytes
 address_decoder_html/fit/check.htm            |   10 +
 address_decoder_html/fit/checkNS4.htm         |   10 +
 address_decoder_html/fit/contact.gif          |  Bin 0 -> 741 bytes
 .../fit/coolrunnerII_logo.jpg                 |  Bin 0 -> 9562 bytes
 address_decoder_html/fit/coolrunner_logo.jpg  |  Bin 0 -> 11278 bytes
 address_decoder_html/fit/education.gif        |  Bin 0 -> 816 bytes
 address_decoder_html/fit/endmkt.gif           |  Bin 0 -> 1560 bytes
 address_decoder_html/fit/eqns.js              |  902 +++++
 address_decoder_html/fit/equations.gif        |  Bin 0 -> 20290 bytes
 address_decoder_html/fit/equations.htm        |   13 +
 address_decoder_html/fit/equationsdoc.htm     |   53 +
 address_decoder_html/fit/errors.js            |   41 +
 address_decoder_html/fit/errors1.gif          |  Bin 0 -> 5648 bytes
 address_decoder_html/fit/errors2.gif          |  Bin 0 -> 3603 bytes
 address_decoder_html/fit/errorsdoc.htm        |   91 +
 address_decoder_html/fit/fb.gif               |  Bin 0 -> 10994 bytes
 address_decoder_html/fit/fb1.gif              |  Bin 0 -> 7918 bytes
 address_decoder_html/fit/fbs.js               |    9 +
 address_decoder_html/fit/fbs_FBdoc.htm        |  307 ++
 address_decoder_html/fit/fbsdoc.htm           |  103 +
 address_decoder_html/fit/fbview.jpg           |  Bin 0 -> 2652 bytes
 address_decoder_html/fit/functionblock.gif    |  Bin 0 -> 22502 bytes
 address_decoder_html/fit/genmsg.htm           |   17 +
 address_decoder_html/fit/header.gif           |  Bin 0 -> 7878 bytes
 address_decoder_html/fit/home.gif             |  Bin 0 -> 940 bytes
 address_decoder_html/fit/index.htm            |   15 +
 address_decoder_html/fit/leftnav.js           |  176 +
 address_decoder_html/fit/legend.gif           |  Bin 0 -> 1213 bytes
 address_decoder_html/fit/legend.jpg           |  Bin 0 -> 1256 bytes
 address_decoder_html/fit/logic_legXC95.htm    |    2 +
 address_decoder_html/fit/logic_legXbr.htm     |   15 +
 address_decoder_html/fit/logic_legXpla3.htm   |    3 +
 address_decoder_html/fit/macrocell.gif        |  Bin 0 -> 7699 bytes
 address_decoder_html/fit/mapinputdoc.htm      |  158 +
 address_decoder_html/fit/maplogic.js          |   23 +
 address_decoder_html/fit/maplogicdoc.htm      |  185 +
 address_decoder_html/fit/newappletref.htm     |   15 +
 address_decoder_html/fit/next.jpg             |  Bin 0 -> 1079 bytes
 address_decoder_html/fit/ns4plugin.js         |   55 +
 address_decoder_html/fit/optionsdoc.htm       |  760 ++++
 address_decoder_html/fit/paths.js             |   37 +
 address_decoder_html/fit/pin.gif              |  Bin 0 -> 3093 bytes
 address_decoder_html/fit/pin_legXC95.htm      |   13 +
 address_decoder_html/fit/pin_legXbr.htm       |   20 +
 address_decoder_html/fit/pin_legXpla3.htm     |   13 +
 address_decoder_html/fit/pindiagram.gif       |  Bin 0 -> 21649 bytes
 address_decoder_html/fit/pins.js              |   62 +
 address_decoder_html/fit/pinsdoc.htm          |  265 ++
 address_decoder_html/fit/pinview.jpg          |  Bin 0 -> 1868 bytes
 address_decoder_html/fit/plugin.js            |   96 +
 address_decoder_html/fit/prev.jpg             |  Bin 0 -> 1490 bytes
 address_decoder_html/fit/print.jpg            |  Bin 0 -> 1683 bytes
 address_decoder_html/fit/products.gif         |  Bin 0 -> 828 bytes
 address_decoder_html/fit/purchase.gif         |  Bin 0 -> 642 bytes
 address_decoder_html/fit/report.htm           |   27 +
 address_decoder_html/fit/result.htm           |   14 +
 address_decoder_html/fit/search.gif           |  Bin 0 -> 975 bytes
 address_decoder_html/fit/spacer.gif           |  Bin 0 -> 233 bytes
 address_decoder_html/fit/style.css            |   19 +
 address_decoder_html/fit/summary.js           |   26 +
 address_decoder_html/fit/summarydoc.htm       |  102 +
 address_decoder_html/fit/support.gif          |  Bin 0 -> 760 bytes
 address_decoder_html/fit/tooltips.js          |  143 +
 address_decoder_html/fit/topnav.js            |   28 +
 address_decoder_html/fit/unmapinputdoc.htm    |   65 +
 address_decoder_html/fit/unmaplogicdoc.htm    |   68 +
 address_decoder_html/fit/verboseview.jpg      |  Bin 0 -> 1262 bytes
 address_decoder_html/fit/view.gif             |  Bin 0 -> 2913 bytes
 address_decoder_html/fit/xc9500_logo.gif      |  Bin 0 -> 8103 bytes
 address_decoder_html/fit/xc9500_logo.jpg      |  Bin 0 -> 8318 bytes
 address_decoder_html/fit/xc9500xl_logo.gif    |  Bin 0 -> 9315 bytes
 address_decoder_html/fit/xc9500xl_logo.jpg    |  Bin 0 -> 9908 bytes
 address_decoder_html/fit/xc9500xv_logo.jpg    |  Bin 0 -> 9336 bytes
 address_decoder_html/fit/xcenter.gif          |  Bin 0 -> 868 bytes
 address_decoder_html/fit/xlogo.gif            |  Bin 0 -> 3407 bytes
 address_decoder_html/fit/xml5.jpg             |  Bin 0 -> 117992 bytes
 address_decoder_html/fit/xml6.jpg             |  Bin 0 -> 88780 bytes
 address_decoder_html/fit/xml7.jpg             |  Bin 0 -> 73104 bytes
 address_decoder_html/fit/xml8.jpg             |  Bin 0 -> 41810 bytes
 address_decoder_html/images/CVS/Entries       |   12 +
 address_decoder_html/images/CVS/Repository    |    1 +
 address_decoder_html/images/CVS/Root          |    1 +
 address_decoder_html/images/CVS/Tag           |    1 +
 address_decoder_html/images/blackBar.jpg      |  Bin 0 -> 750 bytes
 address_decoder_html/images/cpldBanner.jpg    |  Bin 0 -> 5897 bytes
 address_decoder_html/images/cr2s_logo.jpg     |  Bin 0 -> 2884 bytes
 address_decoder_html/images/fitterRpt.jpg     |  Bin 0 -> 1341 bytes
 address_decoder_html/images/logo.jpg          |  Bin 0 -> 2922 bytes
 address_decoder_html/images/spacer.jpg        |  Bin 0 -> 444 bytes
 address_decoder_html/images/timingRpt.jpg     |  Bin 0 -> 1480 bytes
 address_decoder_html/images/xbr_logo.jpg      |  Bin 0 -> 2865 bytes
 address_decoder_html/images/xc9500_logo.jpg   |  Bin 0 -> 1979 bytes
 address_decoder_html/images/xc9500xl_logo.jpg |  Bin 0 -> 2922 bytes
 address_decoder_html/images/xc9500xv_logo.jpg |  Bin 0 -> 2499 bytes
 address_decoder_html/images/xpla3_logo.jpg    |  Bin 0 -> 4130 bytes
 address_decoder_html/tim/CVS/Entries          |    9 +
 address_decoder_html/tim/CVS/Repository       |    1 +
 address_decoder_html/tim/CVS/Root             |    1 +
 address_decoder_html/tim/CVS/Tag              |    1 +
 address_decoder_html/tim/cpldta_glossary.htm  |  250 ++
 address_decoder_html/tim/cpldta_style.css     |  144 +
 address_decoder_html/tim/genreport.htm        |   17 +
 address_decoder_html/tim/leftnav.htm          |   37 +
 address_decoder_html/tim/report.htm           |   14 +
 address_decoder_html/tim/timing_report.htm    |   10 +
 address_decoder_html/tim/toc.css              |   36 +
 address_decoder_html/tim/topnav.htm           |   31 +
 spi65.dhp                                     |    2 +-
 spi65.npl                                     |    1 +
 spi6502b.bld                                  |    2 +-
 spi6502b.gyd                                  |   50 +-
 spi6502b.jed                                  | 1318 +++----
 spi6502b.mfd                                  |  586 +--
 spi6502b.ngc                                  |    2 +-
 spi6502b.ngd                                  |    2 +-
 spi6502b.ngr                                  |    2 +-
 spi6502b.pnx                                  |    2 +-
 spi6502b.prj                                  |    1 +
 spi6502b.rpt                                  |  628 +--
 spi6502b.syr                                  |   78 +-
 spi6502b.vm6                                  | 3439 +++++++++--------
 spi6502b.xml                                  |    2 +-
 spi6502b_pad.csv                              |   26 +-
 143 files changed, 8693 insertions(+), 3019 deletions(-)
 create mode 100644 .untf
 create mode 100644 address_decoder._u_
 create mode 100644 address_decoder.lfp
 create mode 100644 address_decoder.sch
 create mode 100644 address_decoder.ucf
 create mode 100644 address_decoder.vhf
 create mode 100644 address_decoder_html/fit/applet.js
 create mode 100644 address_decoder_html/fit/appletref.htm
 create mode 100644 address_decoder_html/fit/asciidoc.htm
 create mode 100644 address_decoder_html/fit/backtop.jpg
 create mode 100644 address_decoder_html/fit/beginstraight.gif
 create mode 100644 address_decoder_html/fit/blank.gif
 create mode 100644 address_decoder_html/fit/blank.htm
 create mode 100644 address_decoder_html/fit/briefview.jpg
 create mode 100644 address_decoder_html/fit/check.htm
 create mode 100644 address_decoder_html/fit/checkNS4.htm
 create mode 100644 address_decoder_html/fit/contact.gif
 create mode 100644 address_decoder_html/fit/coolrunnerII_logo.jpg
 create mode 100644 address_decoder_html/fit/coolrunner_logo.jpg
 create mode 100644 address_decoder_html/fit/education.gif
 create mode 100644 address_decoder_html/fit/endmkt.gif
 create mode 100644 address_decoder_html/fit/eqns.js
 create mode 100644 address_decoder_html/fit/equations.gif
 create mode 100644 address_decoder_html/fit/equations.htm
 create mode 100644 address_decoder_html/fit/equationsdoc.htm
 create mode 100644 address_decoder_html/fit/errors.js
 create mode 100644 address_decoder_html/fit/errors1.gif
 create mode 100644 address_decoder_html/fit/errors2.gif
 create mode 100644 address_decoder_html/fit/errorsdoc.htm
 create mode 100644 address_decoder_html/fit/fb.gif
 create mode 100644 address_decoder_html/fit/fb1.gif
 create mode 100644 address_decoder_html/fit/fbs.js
 create mode 100644 address_decoder_html/fit/fbs_FBdoc.htm
 create mode 100644 address_decoder_html/fit/fbsdoc.htm
 create mode 100644 address_decoder_html/fit/fbview.jpg
 create mode 100644 address_decoder_html/fit/functionblock.gif
 create mode 100644 address_decoder_html/fit/genmsg.htm
 create mode 100644 address_decoder_html/fit/header.gif
 create mode 100644 address_decoder_html/fit/home.gif
 create mode 100644 address_decoder_html/fit/index.htm
 create mode 100644 address_decoder_html/fit/leftnav.js
 create mode 100644 address_decoder_html/fit/legend.gif
 create mode 100644 address_decoder_html/fit/legend.jpg
 create mode 100644 address_decoder_html/fit/logic_legXC95.htm
 create mode 100644 address_decoder_html/fit/logic_legXbr.htm
 create mode 100644 address_decoder_html/fit/logic_legXpla3.htm
 create mode 100644 address_decoder_html/fit/macrocell.gif
 create mode 100644 address_decoder_html/fit/mapinputdoc.htm
 create mode 100644 address_decoder_html/fit/maplogic.js
 create mode 100644 address_decoder_html/fit/maplogicdoc.htm
 create mode 100644 address_decoder_html/fit/newappletref.htm
 create mode 100644 address_decoder_html/fit/next.jpg
 create mode 100644 address_decoder_html/fit/ns4plugin.js
 create mode 100644 address_decoder_html/fit/optionsdoc.htm
 create mode 100644 address_decoder_html/fit/paths.js
 create mode 100644 address_decoder_html/fit/pin.gif
 create mode 100644 address_decoder_html/fit/pin_legXC95.htm
 create mode 100644 address_decoder_html/fit/pin_legXbr.htm
 create mode 100644 address_decoder_html/fit/pin_legXpla3.htm
 create mode 100644 address_decoder_html/fit/pindiagram.gif
 create mode 100644 address_decoder_html/fit/pins.js
 create mode 100644 address_decoder_html/fit/pinsdoc.htm
 create mode 100644 address_decoder_html/fit/pinview.jpg
 create mode 100644 address_decoder_html/fit/plugin.js
 create mode 100644 address_decoder_html/fit/prev.jpg
 create mode 100644 address_decoder_html/fit/print.jpg
 create mode 100644 address_decoder_html/fit/products.gif
 create mode 100644 address_decoder_html/fit/purchase.gif
 create mode 100644 address_decoder_html/fit/report.htm
 create mode 100644 address_decoder_html/fit/result.htm
 create mode 100644 address_decoder_html/fit/search.gif
 create mode 100644 address_decoder_html/fit/spacer.gif
 create mode 100644 address_decoder_html/fit/style.css
 create mode 100644 address_decoder_html/fit/summary.js
 create mode 100644 address_decoder_html/fit/summarydoc.htm
 create mode 100644 address_decoder_html/fit/support.gif
 create mode 100644 address_decoder_html/fit/tooltips.js
 create mode 100644 address_decoder_html/fit/topnav.js
 create mode 100644 address_decoder_html/fit/unmapinputdoc.htm
 create mode 100644 address_decoder_html/fit/unmaplogicdoc.htm
 create mode 100644 address_decoder_html/fit/verboseview.jpg
 create mode 100644 address_decoder_html/fit/view.gif
 create mode 100644 address_decoder_html/fit/xc9500_logo.gif
 create mode 100644 address_decoder_html/fit/xc9500_logo.jpg
 create mode 100644 address_decoder_html/fit/xc9500xl_logo.gif
 create mode 100644 address_decoder_html/fit/xc9500xl_logo.jpg
 create mode 100644 address_decoder_html/fit/xc9500xv_logo.jpg
 create mode 100644 address_decoder_html/fit/xcenter.gif
 create mode 100644 address_decoder_html/fit/xlogo.gif
 create mode 100644 address_decoder_html/fit/xml5.jpg
 create mode 100644 address_decoder_html/fit/xml6.jpg
 create mode 100644 address_decoder_html/fit/xml7.jpg
 create mode 100644 address_decoder_html/fit/xml8.jpg
 create mode 100644 address_decoder_html/images/CVS/Entries
 create mode 100644 address_decoder_html/images/CVS/Repository
 create mode 100644 address_decoder_html/images/CVS/Root
 create mode 100644 address_decoder_html/images/CVS/Tag
 create mode 100644 address_decoder_html/images/blackBar.jpg
 create mode 100644 address_decoder_html/images/cpldBanner.jpg
 create mode 100644 address_decoder_html/images/cr2s_logo.jpg
 create mode 100644 address_decoder_html/images/fitterRpt.jpg
 create mode 100644 address_decoder_html/images/logo.jpg
 create mode 100644 address_decoder_html/images/spacer.jpg
 create mode 100644 address_decoder_html/images/timingRpt.jpg
 create mode 100644 address_decoder_html/images/xbr_logo.jpg
 create mode 100644 address_decoder_html/images/xc9500_logo.jpg
 create mode 100644 address_decoder_html/images/xc9500xl_logo.jpg
 create mode 100644 address_decoder_html/images/xc9500xv_logo.jpg
 create mode 100644 address_decoder_html/images/xpla3_logo.jpg
 create mode 100644 address_decoder_html/tim/CVS/Entries
 create mode 100644 address_decoder_html/tim/CVS/Repository
 create mode 100644 address_decoder_html/tim/CVS/Root
 create mode 100644 address_decoder_html/tim/CVS/Tag
 create mode 100644 address_decoder_html/tim/cpldta_glossary.htm
 create mode 100644 address_decoder_html/tim/cpldta_style.css
 create mode 100644 address_decoder_html/tim/genreport.htm
 create mode 100644 address_decoder_html/tim/leftnav.htm
 create mode 100644 address_decoder_html/tim/report.htm
 create mode 100644 address_decoder_html/tim/timing_report.htm
 create mode 100644 address_decoder_html/tim/toc.css
 create mode 100644 address_decoder_html/tim/topnav.htm

diff --git a/.gitignore b/.gitignore
index aa04e65..58e3919 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,97 @@
-#Gitignore for files generated by Xilinx ISE
+#ignore OS noise
+
+Thumbs.db
+.DS_Store
+
+# Ignore list for Eagle, a PCB layout tool
+
+# Backup files
+*.s#?
+*.b#?
+*.l#?
+
+# Eagle project file
+# It contains a serial number and references to the file structure
+# on your computer.
+# comment the following line if you want to have your project file included.
+eagle.epf
+
+# Autorouter files
+*.pro
+*.job
+
+# CAM files
+*.$$$
+*.cmp
+*.ly2
+*.l15
+*.sol
+*.plc
+*.stc
+*.sts
+*.crc
+*.crs
+
+*.dri
+*.drl
+*.gpi
+*.pls
+
+*.drd
+*.drd.*
+
+*.info
+
+*.eps
+
+# file locks introduced since 7.x
+*.lck
+
+# Xilinx ISE
+# intermediate build files
+*.bgn
+*.bit
+*.bld
+*.cmd_log
+*.drc
+*.ll
+*.lso
+*.msd
+*.msk
+*.ncd
+*.ngc
+*.ngd
+*.ngr
+*.pad
+*.par
+*.pcf
+*.prj
+*.ptwx
+*.rbb
+*.rbd
+*.stx
+*.syr
+*.twr
+*.twx
+*.unroutes
+*.ut
+*.xpi
+*.xst
+*_bitgen.xwbt
+*_envsettings.html
+*_map.map
+*_map.mrp
+*_map.ngm
+*_map.xrpt
+*_ngdbuild.xrpt
+*_pad.csv
+*_pad.txt
+*_par.xrpt
+*_summary.html
+*_summary.xml
+*_usage.xml
+*_xst.xrpt
+
 
 *.log
 *.svf
@@ -38,7 +131,26 @@ impact_impact.xwbt
 spi6502b_html*/
 __projnav*/
 
-#ignore OS noise
+# iMPACT generated files
+_impactbatch.log
+impact.xsl
+impact_impact.xwbt
+ise_impact.cmd
+webtalk_impact.xml
 
-Thumbs.db
-.DS_Store
+# Core Generator generated files
+xaw2verilog.log
+
+# project-wide generated files
+*.gise
+par_usage_statistics.html
+usage_statistics_webtalk.html
+webtalk.log
+webtalk_pn.xml
+
+# generated folders
+iseconfig/
+xlnx_auto_0_xdb/
+xst/
+_ngo/
+_xmsgs/
diff --git a/.untf b/.untf
new file mode 100644
index 0000000..e69de29
diff --git a/SPI6502B.lfp b/SPI6502B.lfp
index 8cce84c..96eff7a 100644
--- a/SPI6502B.lfp
+++ b/SPI6502B.lfp
@@ -1,4 +1,4 @@
-# begin LFP file C:\sources\spi65\SPI6502B.lfp
+# begin LFP file C:\sources\AppleIISd\SPI6502B.lfp
 designfile spi6502b.ngd
 IO_GROUP "spi_Nsel"  ;
 IO_GROUP "spi_miso"  ;
@@ -6,22 +6,9 @@ IO_GROUP "spi_int"  ;
 IO_GROUP "cpu_d"  ;
 IO_GROUP "cpu_a"  ;
 NET "spi_sclk" COLOR=6  ;
-NET "spi_Nsel<3>" COLOR=6 IO_GROUP="spi_Nsel"  ;
-NET "spi_Nsel<2>" COLOR=6 IO_GROUP="spi_Nsel"  ;
-NET "spi_Nsel<1>" COLOR=6 IO_GROUP="spi_Nsel"  ;
-NET "spi_Nsel<0>" COLOR=6 IO_GROUP="spi_Nsel"  ;
 NET "spi_mosi" COLOR=6  ;
-NET "spi_miso<3>" COLOR=6 IO_GROUP="spi_miso"  ;
-NET "spi_miso<2>" COLOR=6 IO_GROUP="spi_miso"  ;
-NET "spi_miso<1>" COLOR=6 IO_GROUP="spi_miso"  ;
-NET "spi_miso<0>" COLOR=6 IO_GROUP="spi_miso"  ;
-NET "spi_int<3>" COLOR=6 IO_GROUP="spi_int"  ;
-NET "spi_int<2>" COLOR=6 IO_GROUP="spi_int"  ;
-NET "spi_int<1>" COLOR=6 IO_GROUP="spi_int"  ;
-NET "spi_int<0>" COLOR=6 IO_GROUP="spi_int"  ;
 NET "Ncs2" COLOR=6  ;
 NET "extclk" COLOR=6  ;
-NET "diag" COLOR=6  ;
 NET "cpu_rnw" COLOR=6  ;
 NET "cpu_Nres" COLOR=6  ;
 NET "cpu_Nphi2" COLOR=6  ;
diff --git a/SPI6502B.ucf b/SPI6502B.ucf
index d030ba8..8a6dd8e 100644
--- a/SPI6502B.ucf
+++ b/SPI6502B.ucf
@@ -3,6 +3,12 @@
 #PACE: Start of Constraints generated by PACE
 
 #PACE: Start of PACE I/O Pin Assignments
+NET "a10"  LOC = "P38"  ;
+NET "b10"  LOC = "P27"  ;
+NET "a8"  LOC = "P36"  ;
+NET "b8"  LOC = "P25"  ;
+NET "a9"  LOC = "P37"  ;
+NET "b9"  LOC = "P26"  ;
 NET "cpu_a<0>"  LOC = "P22"  ;
 NET "cpu_a<1>"  LOC = "P24"  ;
 NET "cpu_d<0>"  LOC = "P2"  ;
@@ -13,14 +19,16 @@ NET "cpu_d<4>"  LOC = "P9"  ;
 NET "cpu_d<5>"  LOC = "P11"  ;
 NET "cpu_d<6>"  LOC = "P12"  ;
 NET "cpu_d<7>"  LOC = "P13"  ;
-NET "cpu_Nirq"  LOC = "P14"  ;
 NET "cpu_Nphi2"  LOC = "P5"  ;
 NET "cpu_Nres"  LOC = "P19"  ;
 NET "cpu_rnw"  LOC = "P7"  ;
-NET "cs1"  LOC = "P20"  ;
-NET "led"  LOC = "P29"  ;
 NET "extclk"  LOC = "P6"  ;
+NET "nio_sel"  LOC = "P40"  ;
+NET "nio_stb"  LOC = "P43"  ;
+NET "led"  LOC = "P29"  ;
 NET "Ncs2"  LOC = "P18"  ;
+NET "ng"  LOC = "P20"  ;
+NET "noe"  LOC = "P14"  ;
 NET "spi_int"  LOC = "P42"  ;
 NET "spi_miso"  LOC = "P44"  ;
 NET "spi_mosi"  LOC = "P35"  ;
diff --git a/SPI6502B1.1.vhd b/SPI6502B1.1.vhd
index e94ed6d..23a4496 100644
--- a/SPI6502B1.1.vhd
+++ b/SPI6502B1.1.vhd
@@ -33,6 +33,8 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
+use address_decoder.ALL;
+
 -- Uncomment the following library declaration if using
 -- arithmetic functions with Signed or Unsigned values
 --use IEEE.NUMERIC_STD.ALL;
@@ -52,7 +54,6 @@ entity SPI6502B is
            cpu_Nres : in  STD_LOGIC;
            cpu_a : in  STD_LOGIC_VECTOR (1 downto 0);
            cpu_Nphi2 : in  STD_LOGIC;
-           cs1 : in  STD_LOGIC;
            Ncs2 : in  STD_LOGIC;
            extclk : in  STD_LOGIC;
            spi_miso: in std_logic;
@@ -60,7 +61,18 @@ entity SPI6502B is
            spi_sclk : out  STD_LOGIC;
            spi_Nsel : out  STD_LOGIC;
 		 spi_int : in  STD_LOGIC;
-           led : out std_logic
+           led : out std_logic;
+
+		a8     : in    std_logic; 
+          a9     : in    std_logic; 
+          a10    : in    std_logic; 
+          nio_sel : in    std_logic; 
+          nio_stb : in    std_logic; 
+          b8   : out   std_logic; 
+          b9   : out   std_logic; 
+          b10  : out   std_logic; 
+          noe     : out   std_logic;
+		ng	  : out 	std_logic
 		);
 			  
 	constant DIV_WIDTH		: integer := 3;
@@ -117,11 +129,36 @@ architecture Behavioral of SPI6502B is
 	signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0);			-- divisor counter
 	
 	signal shiftclk : std_logic;
+
+	component address_decoder
+   port ( A8     : in    std_logic; 
+          A9     : in    std_logic; 
+          A10    : in    std_logic; 
+          CLK : in    std_logic; 
+          NIO_SEL : in    std_logic; 
+          NIO_STB : in    std_logic; 
+          A8_B   : out   std_logic; 
+          A9_B   : out   std_logic; 
+          A10_B  : out   std_logic; 
+          NOE     : out   std_logic);
+	end component;
 	
 begin
+	add_dec : address_decoder
+      port map (A8=>a8,      
+                A9=>a9,
+			 A10=>a10,
+			 CLK=>extclk,
+			 NIO_SEL=>nio_sel,
+			 NIO_STB=>nio_stb,
+			 A8_B=>b8,
+			 A9_B=>b9,
+			 A10_B=>b10,
+			 NOE=>noe);
+	
 			
 	led <= not (bsy or not slavesel); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
-	
+	ng <=  Ncs2 and nio_sel and nio_stb;
 	--------------------------
 	
 	bsy <= start_shifting or shifting2;
@@ -256,7 +293,7 @@ begin
 	-- interface section
 	-- inputs
 	reset <= not (cpu_Nres);
-	selected <= cs1 and not(Ncs2); -- and cpu_phi2;
+	selected <= not(Ncs2); -- and cpu_phi2;
 	is_read <= selected and cpu_Nphi2 and cpu_rnw;
 	int_din <= cpu_d;	
 	slaveint <= not(spi_int);		-- active low interrupt inputs
diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst
index 20f8fc8..42a41ae 100644
--- a/_ngo/netlist.lst
+++ b/_ngo/netlist.lst
@@ -1,2 +1,2 @@
-C:\sources\AppleIISd\spi6502b.ngc 1494085672
+C:\sources\AppleIISd\spi6502b.ngc 1494461294
 OK
diff --git a/_pace.ucf b/_pace.ucf
index add0940..9d5d775 100644
--- a/_pace.ucf
+++ b/_pace.ucf
@@ -1,41 +1,42 @@
-
-NET "cpu_Nphi2"			loc="P5";
-NET "extclk"			loc="P6";
-NET "cpu_rnw"			loc="P7";
-
 #net "diag"				loc="P29";
 
-NET "cpu_d<0>"			loc="P2";
-NET "cpu_d<1>"			loc="P3";
-NET "cpu_d<2>"			loc="P4";
-NET "cpu_d<3>"			loc="P8";
-NET "cpu_d<4>"			loc="P9";
-NET "cpu_d<5>"			loc="P11";
-NET "cpu_d<6>"			loc="P12";
-NET "cpu_d<7>"			loc="P13";
+#PACE: Start of Constraints generated by PACE
 
-NET "cpu_Nirq"			loc="P14";
-NET "Ncs2"				loc="P18";
-NET "cs1"				loc="P20";
-NET "cpu_Nres"			loc="P19";
-	
-NET "cpu_a<0>"			loc="P22";
-NET "cpu_a<1>"			loc="P24";
+#PACE: Start of PACE I/O Pin Assignments
+NET "A10"  LOC = "P38"  ;
+NET "A10_B"  LOC = "P25"  ;
+NET "A8"  LOC = "P36"  ;
+NET "A8_B"  LOC = "P27"  ;
+NET "A9"  LOC = "P37"  ;
+NET "A9_B"  LOC = "P26"  ;
+NET "cpu_a<0>"  LOC = "P22"  ;
+NET "cpu_a<1>"  LOC = "P24"  ;
+NET "cpu_d<0>"  LOC = "P2"  ;
+NET "cpu_d<1>"  LOC = "P3"  ;
+NET "cpu_d<2>"  LOC = "P4"  ;
+NET "cpu_d<3>"  LOC = "P8"  ;
+NET "cpu_d<4>"  LOC = "P9"  ;
+NET "cpu_d<5>"  LOC = "P11"  ;
+NET "cpu_d<6>"  LOC = "P12"  ;
+NET "cpu_d<7>"  LOC = "P13"  ;
+NET "cpu_Nirq"  LOC = "P14"  ;
+NET "cpu_Nphi2"  LOC = "P5"  ;
+NET "cpu_Nres"  LOC = "P19"  ;
+NET "cpu_rnw"  LOC = "P7"  ;
+NET "extclk"  LOC = "P6"  ;
+NET "IO_SEL"  LOC = "P40"  ;
+NET "IO_STB"  LOC = "P43"  ;
+NET "led"  LOC = "P29"  ;
+NET "Ncs2"  LOC = "P18"  ;
+NET "OE"  LOC = "P1"  ;
+NET "spi_int"  LOC = "P42"  ;
+NET "spi_miso"  LOC = "P44"  ;
+NET "spi_mosi"  LOC = "P35"  ;
+NET "spi_Nsel"  LOC = "P28"  ;
+NET "spi_sclk"  LOC = "P34"  ;
 
-NET "spi_int<0>"		loc="P42";
-NET "spi_int<1>"		loc="P40";
-NET "spi_int<2>"		loc="P39";
-NET "spi_int<3>"		loc="P1";
+#PACE: Start of PACE Area Constraints
 
-NET "spi_Nsel<0>"		loc="P28";
-NET "spi_Nsel<1>"		loc="P27";
-NET "spi_Nsel<2>"		loc="P26";
-NET "spi_Nsel<3>"		loc="P25";
+#PACE: Start of PACE Prohibit Constraints
 
-NET "spi_sclk"			loc="P34";
-NET "spi_mosi"			loc="P35";
-
-NET "spi_miso<0>"		loc="P44";
-NET "spi_miso<1>"		loc="P43";
-NET "spi_miso<2>"		loc="P38";
-NET "spi_miso<3>"		loc="P37";
+#PACE: End of Constraints generated by PACE
diff --git a/address_decoder._u_ b/address_decoder._u_
new file mode 100644
index 0000000..e69de29
diff --git a/address_decoder.lfp b/address_decoder.lfp
new file mode 100644
index 0000000..273ab0b
--- /dev/null
+++ b/address_decoder.lfp
@@ -0,0 +1,15 @@
+# begin LFP file C:\sources\AppleIISd\address_decoder.lfp
+designfile address_decoder.ngd
+INST "address_decoder" COLOR=15  ;
+NET "OE" COLOR=6  ;
+NET "IO_STB" COLOR=6  ;
+NET "IO_SEL" COLOR=6  ;
+NET "extclk" COLOR=6  ;
+NET "A10_B" COLOR=6  ;
+NET "A10" COLOR=6  ;
+NET "A9_B" COLOR=6  ;
+NET "A9" COLOR=6  ;
+NET "A8_B" COLOR=6  ;
+NET "A8" COLOR=6  ;
+INST "XLXI_16" COLOR=7  ;
+INST "XLXI_16/U0" COLOR=7  ;
diff --git a/address_decoder.sch b/address_decoder.sch
new file mode 100644
index 0000000..2d2da0a
--- /dev/null
+++ b/address_decoder.sch
@@ -0,0 +1,240 @@
+VERSION 6
+BEGIN SCHEMATIC
+    BEGIN ATTR DeviceFamilyName "xc9500xl"
+        DELETE all:0
+        EDITNAME all:0
+        EDITTRAIT all:0
+    END ATTR
+    BEGIN NETLIST
+        SIGNAL NIO_STB
+        SIGNAL XLXN_4
+        SIGNAL A10
+        SIGNAL A9
+        SIGNAL A8
+        SIGNAL XLXN_10
+        SIGNAL XLXN_11
+        SIGNAL NOE
+        SIGNAL CLK
+        SIGNAL XLXN_14
+        SIGNAL A10_B
+        SIGNAL A9_B
+        SIGNAL A8_B
+        SIGNAL NIO_SEL
+        SIGNAL XLXN_19
+        PORT Input NIO_STB
+        PORT Input A10
+        PORT Input A9
+        PORT Input A8
+        PORT Output NOE
+        PORT Input CLK
+        PORT Output A10_B
+        PORT Output A9_B
+        PORT Output A8_B
+        PORT Input NIO_SEL
+        BEGIN BLOCKDEF fdrs
+            TIMESTAMP 2001 3 9 11 23 0
+            LINE N 0 -128 64 -128 
+            LINE N 0 -256 64 -256 
+            LINE N 384 -256 320 -256 
+            LINE N 0 -32 64 -32 
+            LINE N 0 -352 64 -352 
+            RECTANGLE N 64 -320 320 -64 
+            LINE N 192 -64 192 -32 
+            LINE N 192 -32 64 -32 
+            LINE N 64 -112 80 -128 
+            LINE N 80 -128 64 -144 
+            LINE N 192 -320 192 -352 
+            LINE N 192 -352 64 -352 
+        END BLOCKDEF
+        BEGIN BLOCKDEF inv
+            TIMESTAMP 2001 3 9 11 23 50
+            LINE N 0 -32 64 -32 
+            LINE N 224 -32 160 -32 
+            LINE N 64 -64 128 -32 
+            LINE N 128 -32 64 0 
+            LINE N 64 0 64 -64 
+            CIRCLE N 128 -48 160 -16 
+        END BLOCKDEF
+        BEGIN BLOCKDEF nand2
+            TIMESTAMP 2001 3 9 11 23 50
+            LINE N 0 -64 64 -64 
+            LINE N 0 -128 64 -128 
+            LINE N 256 -96 216 -96 
+            CIRCLE N 192 -108 216 -84 
+            LINE N 64 -48 64 -144 
+            LINE N 64 -144 144 -144 
+            LINE N 144 -48 64 -48 
+            ARC N 96 -144 192 -48 144 -48 144 -144 
+        END BLOCKDEF
+        BEGIN BLOCKDEF vcc
+            TIMESTAMP 2001 3 9 11 23 11
+            LINE N 96 -64 32 -64 
+            LINE N 64 0 64 -32 
+            LINE N 64 -32 64 -64 
+        END BLOCKDEF
+        BEGIN BLOCKDEF and2
+            TIMESTAMP 2001 5 11 10 41 37
+            LINE N 0 -64 64 -64 
+            LINE N 0 -128 64 -128 
+            LINE N 256 -96 192 -96 
+            ARC N 96 -144 192 -48 144 -48 144 -144 
+            LINE N 144 -48 64 -48 
+            LINE N 64 -144 144 -144 
+            LINE N 64 -48 64 -144 
+        END BLOCKDEF
+        BEGIN BLOCKDEF and4b1
+            TIMESTAMP 2001 5 11 10 43 32
+            LINE N 0 -64 40 -64 
+            CIRCLE N 40 -76 64 -52 
+            LINE N 0 -128 64 -128 
+            LINE N 0 -192 64 -192 
+            LINE N 0 -256 64 -256 
+            LINE N 256 -160 192 -160 
+            LINE N 64 -64 64 -256 
+            LINE N 144 -112 64 -112 
+            ARC N 96 -208 192 -112 144 -112 144 -208 
+            LINE N 64 -208 144 -208 
+        END BLOCKDEF
+        BEGIN BLOCK XLXI_13 nand2
+            PIN I0 NIO_SEL
+            PIN I1 NIO_STB
+            PIN O XLXN_4
+        END BLOCK
+        BEGIN BLOCK XLXI_14 nand2
+            PIN I0 XLXN_11
+            PIN I1 XLXN_4
+            PIN O NOE
+        END BLOCK
+        BEGIN BLOCK XLXI_16 fdrs
+            PIN C CLK
+            PIN D XLXN_14
+            PIN R XLXN_10
+            PIN S XLXN_19
+            PIN Q XLXN_11
+        END BLOCK
+        BEGIN BLOCK XLXI_17 vcc
+            PIN P XLXN_14
+        END BLOCK
+        BEGIN BLOCK XLXI_18 and2
+            PIN I0 A10
+            PIN I1 NIO_SEL
+            PIN O A10_B
+        END BLOCK
+        BEGIN BLOCK XLXI_19 and2
+            PIN I0 A9
+            PIN I1 NIO_SEL
+            PIN O A9_B
+        END BLOCK
+        BEGIN BLOCK XLXI_20 and2
+            PIN I0 A8
+            PIN I1 NIO_SEL
+            PIN O A8_B
+        END BLOCK
+        BEGIN BLOCK XLXI_22 inv
+            PIN I NIO_SEL
+            PIN O XLXN_19
+        END BLOCK
+        BEGIN BLOCK XLXI_23 and4b1
+            PIN I0 NIO_STB
+            PIN I1 A10
+            PIN I2 A9
+            PIN I3 A8
+            PIN O XLXN_10
+        END BLOCK
+    END NETLIST
+    BEGIN SHEET 1 3520 2720
+        IOMARKER 320 496 NIO_STB R180 28
+        IOMARKER 320 560 NIO_SEL R180 28
+        BEGIN BRANCH NIO_STB
+            WIRE 320 496 368 496
+            WIRE 368 496 368 640
+            WIRE 368 640 608 640
+            WIRE 368 496 1120 496
+        END BRANCH
+        BEGIN BRANCH XLXN_4
+            WIRE 1376 528 1744 528
+        END BRANCH
+        BEGIN BRANCH A10
+            WIRE 320 704 592 704
+            WIRE 592 704 608 704
+            WIRE 592 704 592 1168
+            WIRE 592 1168 1088 1168
+        END BRANCH
+        BEGIN BRANCH A9
+            WIRE 320 768 528 768
+            WIRE 528 768 608 768
+            WIRE 528 768 528 1312
+            WIRE 528 1312 1088 1312
+        END BRANCH
+        BEGIN BRANCH A8
+            WIRE 320 832 480 832
+            WIRE 480 832 608 832
+            WIRE 480 832 480 1456
+            WIRE 480 1456 1088 1456
+        END BRANCH
+        IOMARKER 320 704 A10 R180 28
+        IOMARKER 320 768 A9 R180 28
+        IOMARKER 320 832 A8 R180 28
+        BEGIN BRANCH NOE
+            WIRE 2000 560 2032 560
+        END BRANCH
+        BEGIN BRANCH CLK
+            WIRE 320 928 1392 928
+        END BRANCH
+        IOMARKER 320 928 CLK R180 28
+        INSTANCE XLXI_18 1088 1232 R0
+        INSTANCE XLXI_19 1088 1376 R0
+        INSTANCE XLXI_20 1088 1520 R0
+        BEGIN BRANCH A10_B
+            WIRE 1344 1136 1744 1136
+        END BRANCH
+        BEGIN BRANCH A9_B
+            WIRE 1344 1280 1744 1280
+        END BRANCH
+        BEGIN BRANCH A8_B
+            WIRE 1344 1424 1744 1424
+        END BRANCH
+        INSTANCE XLXI_17 976 800 R0
+        BEGIN BRANCH XLXN_14
+            WIRE 1040 800 1392 800
+        END BRANCH
+        INSTANCE XLXI_13 1120 624 R0
+        BEGIN BRANCH XLXN_11
+            WIRE 1728 592 1744 592
+            WIRE 1728 592 1728 656
+            WIRE 1728 656 1840 656
+            WIRE 1840 656 1840 800
+            WIRE 1776 800 1840 800
+        END BRANCH
+        IOMARKER 1744 1136 A10_B R0 28
+        IOMARKER 1744 1280 A9_B R0 28
+        IOMARKER 1744 1424 A8_B R0 28
+        IOMARKER 2032 560 NOE R0 28
+        INSTANCE XLXI_14 1744 656 R0
+        INSTANCE XLXI_16 1392 1056 R0
+        BEGIN BRANCH XLXN_10
+            WIRE 864 736 880 736
+            WIRE 880 736 880 1024
+            WIRE 880 1024 1392 1024
+        END BRANCH
+        BEGIN BRANCH NIO_SEL
+            WIRE 320 560 944 560
+            WIRE 944 560 1088 560
+            WIRE 1088 560 1120 560
+            WIRE 1088 560 1088 704
+            WIRE 1088 704 1120 704
+            WIRE 944 560 944 1104
+            WIRE 944 1104 1088 1104
+            WIRE 944 1104 944 1248
+            WIRE 944 1248 944 1392
+            WIRE 944 1392 1088 1392
+            WIRE 944 1248 1088 1248
+        END BRANCH
+        BEGIN BRANCH XLXN_19
+            WIRE 1344 704 1360 704
+            WIRE 1360 704 1392 704
+        END BRANCH
+        INSTANCE XLXI_22 1120 736 R0
+        INSTANCE XLXI_23 608 576 M180
+    END SHEET
+END SCHEMATIC
diff --git a/address_decoder.ucf b/address_decoder.ucf
new file mode 100644
index 0000000..a6d30f8
--- /dev/null
+++ b/address_decoder.ucf
@@ -0,0 +1,19 @@
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "A10"  LOC = "P37"  ;
+NET "A10_B"  LOC = "P38"  ;
+NET "A8"  LOC = "P27"  ;
+NET "A8_B"  LOC = "P29"  ;
+NET "A9"  LOC = "P33"  ;
+NET "A9_B"  LOC = "P36"  ;
+NET "extclk"  LOC = "p6"  ;
+NET "IO_SEL"  LOC = "P39"  ;
+NET "IO_STB"  LOC = "P40"  ;
+NET "OE"  LOC = "P1"  ;
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
diff --git a/address_decoder.vhf b/address_decoder.vhf
new file mode 100644
index 0000000..a83b4cf
--- /dev/null
+++ b/address_decoder.vhf
@@ -0,0 +1,288 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2003 Xilinx, Inc.
+-- All Right Reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 6.3.03i
+--  \   \         Application : 
+--  /   /         Filename : address_decoder.vhf
+-- /___/   /\     Timestamp : 05/11/2017 02:05:37
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: 
+--Design Name: FD_MXILINX_address_decoder
+--
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+-- synopsys translate_off
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+-- synopsys translate_on
+
+entity FD_MXILINX_address_decoder is
+   port ( C : in    std_logic; 
+          D : in    std_logic; 
+          Q : out   std_logic);
+end FD_MXILINX_address_decoder;
+
+architecture BEHAVIORAL of FD_MXILINX_address_decoder is
+   attribute BOX_TYPE   : string ;
+   signal XLXN_4 : std_logic;
+   component GND
+      port ( G : out   std_logic);
+   end component;
+   attribute BOX_TYPE of GND : component is "BLACK_BOX";
+   
+   component FDCP
+      port ( C   : in    std_logic; 
+             CLR : in    std_logic; 
+             D   : in    std_logic; 
+             PRE : in    std_logic; 
+             Q   : out   std_logic);
+   end component;
+   attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
+   
+begin
+   I_36_43 : GND
+      port map (G=>XLXN_4);
+   
+   U0 : FDCP
+      port map (C=>C,      
+                CLR=>XLXN_4,      
+                D=>D,      
+                PRE=>XLXN_4,      
+                Q=>Q);
+   
+end BEHAVIORAL;
+
+
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2003 Xilinx, Inc.
+-- All Right Reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 6.3.03i
+--  \   \         Application : 
+--  /   /         Filename : address_decoder.vhf
+-- /___/   /\     Timestamp : 05/11/2017 02:05:37
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: 
+--Design Name: FDRS_MXILINX_address_decoder
+--
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+-- synopsys translate_off
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+-- synopsys translate_on
+
+entity FDRS_MXILINX_address_decoder is
+   port ( C : in    std_logic; 
+          D : in    std_logic; 
+          R : in    std_logic; 
+          S : in    std_logic; 
+          Q : out   std_logic);
+end FDRS_MXILINX_address_decoder;
+
+architecture BEHAVIORAL of FDRS_MXILINX_address_decoder is
+   attribute BOX_TYPE   : string ;
+   attribute HU_SET     : string ;
+   signal XLXN_6 : std_logic;
+   signal XLXN_7 : std_logic;
+   signal XLXN_8 : std_logic;
+   component AND2B1
+      port ( I0 : in    std_logic; 
+             I1 : in    std_logic; 
+             O  : out   std_logic);
+   end component;
+   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
+   
+   component OR2
+      port ( I0 : in    std_logic; 
+             I1 : in    std_logic; 
+             O  : out   std_logic);
+   end component;
+   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
+   
+   component FD_MXILINX_address_decoder
+      port ( C : in    std_logic; 
+             D : in    std_logic; 
+             Q : out   std_logic);
+   end component;
+   
+   attribute HU_SET of U0 : label is "U0_0";
+begin
+   I_36_112 : AND2B1
+      port map (I0=>R,      
+                I1=>S,      
+                O=>XLXN_6);
+   
+   I_36_113 : AND2B1
+      port map (I0=>R,      
+                I1=>D,      
+                O=>XLXN_8);
+   
+   I_36_120 : OR2
+      port map (I0=>XLXN_6,      
+                I1=>XLXN_8,      
+                O=>XLXN_7);
+   
+   U0 : FD_MXILINX_address_decoder
+      port map (C=>C,      
+                D=>XLXN_7,      
+                Q=>Q);
+   
+end BEHAVIORAL;
+
+
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2003 Xilinx, Inc.
+-- All Right Reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 6.3.03i
+--  \   \         Application : 
+--  /   /         Filename : address_decoder.vhf
+-- /___/   /\     Timestamp : 05/11/2017 02:05:37
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: 
+--Design Name: address_decoder
+--
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+-- synopsys translate_off
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+-- synopsys translate_on
+
+entity address_decoder is
+   port ( A8      : in    std_logic; 
+          A9      : in    std_logic; 
+          A10     : in    std_logic; 
+          CLK     : in    std_logic; 
+          NIO_SEL : in    std_logic; 
+          NIO_STB : in    std_logic; 
+          A8_B    : out   std_logic; 
+          A9_B    : out   std_logic; 
+          A10_B   : out   std_logic; 
+          NOE     : out   std_logic);
+end address_decoder;
+
+architecture BEHAVIORAL of address_decoder is
+   attribute BOX_TYPE   : string ;
+   attribute HU_SET     : string ;
+   signal XLXN_4  : std_logic;
+   signal XLXN_10 : std_logic;
+   signal XLXN_11 : std_logic;
+   signal XLXN_14 : std_logic;
+   signal XLXN_19 : std_logic;
+   component NAND2
+      port ( I0 : in    std_logic; 
+             I1 : in    std_logic; 
+             O  : out   std_logic);
+   end component;
+   attribute BOX_TYPE of NAND2 : component is "BLACK_BOX";
+   
+   component FDRS_MXILINX_address_decoder
+      port ( C : in    std_logic; 
+             D : in    std_logic; 
+             R : in    std_logic; 
+             S : in    std_logic; 
+             Q : out   std_logic);
+   end component;
+   
+   component VCC
+      port ( P : out   std_logic);
+   end component;
+   attribute BOX_TYPE of VCC : component is "BLACK_BOX";
+   
+   component AND2
+      port ( I0 : in    std_logic; 
+             I1 : in    std_logic; 
+             O  : out   std_logic);
+   end component;
+   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
+   
+   component INV
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   attribute BOX_TYPE of INV : component is "BLACK_BOX";
+   
+   component AND4B1
+      port ( I0 : in    std_logic; 
+             I1 : in    std_logic; 
+             I2 : in    std_logic; 
+             I3 : in    std_logic; 
+             O  : out   std_logic);
+   end component;
+   attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
+   
+   attribute HU_SET of XLXI_16 : label is "XLXI_16_1";
+begin
+   XLXI_13 : NAND2
+      port map (I0=>NIO_SEL,      
+                I1=>NIO_STB,      
+                O=>XLXN_4);
+   
+   XLXI_14 : NAND2
+      port map (I0=>XLXN_11,      
+                I1=>XLXN_4,      
+                O=>NOE);
+   
+   XLXI_16 : FDRS_MXILINX_address_decoder
+      port map (C=>CLK,      
+                D=>XLXN_14,      
+                R=>XLXN_10,      
+                S=>XLXN_19,      
+                Q=>XLXN_11);
+   
+   XLXI_17 : VCC
+      port map (P=>XLXN_14);
+   
+   XLXI_18 : AND2
+      port map (I0=>A10,      
+                I1=>NIO_SEL,      
+                O=>A10_B);
+   
+   XLXI_19 : AND2
+      port map (I0=>A9,      
+                I1=>NIO_SEL,      
+                O=>A9_B);
+   
+   XLXI_20 : AND2
+      port map (I0=>A8,      
+                I1=>NIO_SEL,      
+                O=>A8_B);
+   
+   XLXI_22 : INV
+      port map (I=>NIO_SEL,      
+                O=>XLXN_19);
+   
+   XLXI_23 : AND4B1
+      port map (I0=>NIO_STB,      
+                I1=>A10,      
+                I2=>A9,      
+                I3=>A8,      
+                O=>XLXN_10);
+   
+end BEHAVIORAL;
+
+
diff --git a/address_decoder_html/fit/applet.js b/address_decoder_html/fit/applet.js
new file mode 100644
index 0000000..d255dd2
--- /dev/null
+++ b/address_decoder_html/fit/applet.js
@@ -0,0 +1,128 @@
+    var tmpStr = "";
+    var waitWin;
+
+    function openWait() {
+     waitWin = window.open("wait.htm", "wait",
+                          "toolbar=no,location=no,"+
+                             "directories=no,status=no,menubar=no,scrollbars=no,"+
+                             "resizable=no,width=300,height=50" );
+    }
+
+    function closeWait() { if (waitWin) waitWin.close(); }
+
+    function setMsg(msg){
+
+       parent.leftnav.setAppletMsg( msg );
+       // now send it reload forces
+       // call to applet paint
+        location.reload();
+    }
+
+    function getMsg(){
+
+        return( parent.leftnav.getAppletMsg() );
+    }
+
+    function resetMsg(){ parent.leftnav.setAppletMsg(""); }
+
+    function printAppletPkg() {
+        if( isNS() ){
+             setMsg("cmd printPkg ");
+         }
+         else{
+             document.ChipViewerApplet.PrintPkg();
+         }
+    }
+
+    function showAppletGraphicMC(mc) {
+        if( isNS() ){
+             setMsg("cmd showMac " + mc);
+         }
+         else{
+             document.ChipViewerApplet.ShowMac(mc);
+         }
+    }
+
+    function ShowMC() { showAppletGraphicMC(tmpStr); }
+
+    function showAppletGraphicFB(fb) {
+         if( isNS() ){
+            setMsg("cmd showFB " + fb);
+         }
+         else{
+             document.ChipViewerApplet.ShowFB(fb);
+         }
+    }
+
+    function showAppletGraphicPin(pin) { 
+         if( isNS() ){ 
+            setMsg("cmd showPin " + pin); 
+         } 
+         else{ 
+             document.ChipViewerApplet.ShowPin(pin); 
+         } 
+    } 
+
+    function ShowFB() { showAppletGraphicFB(tmpStr); }
+
+    function isNS() {
+      return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) < 5) ) ? true : false;
+    }
+
+    function isIE(){
+        var agt=navigator.userAgent.toLowerCase();
+        return( ( (agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1) ) ? true: false );
+    }
+
+    function waitUntilOK() {
+      if (!waitWin) openWait();
+      if (isNS()) {
+        if (document.ChipViewerApplet.isActive()) closeWait();
+        else  settimeout("waitUntilOK()",100);
+      }
+      else {
+        if (document.ChipViewerApplet.readyState == 4) closeWait();
+        else  settimeout("waitUntilOK()",100);
+      }
+    }
+
+
+    // check that the applet if file has been generated
+    // this can only be done if the applets been loaded.
+    function fileExists(fileName){
+
+        if( document.ChipViewerApplet.readyState != 4 ) {
+            window.alert("Navigation disabled until the applet is loaded." );
+        }
+        if( isIE() ){
+            if( parent.leftnav.getAppletPermission() == 1 ){
+                if( document.ChipViewerApplet.TestFileExists(fileName) == 1 ){
+                    window.alert("file exist tests true" );
+                    return( true );
+                }
+            }
+            else{
+                window.alert("file exist returns true no permission" );
+                return( true );
+            }
+        }
+        else{
+            return( true );
+        }
+        window.alert("file exist returns false" );
+        return( false );
+    }
+
+
+
+    function setPermission(){
+
+        if( isIE() ){
+            if( document.ChipViewerApplet.granted() ){
+                parent.leftnav.setAppletPermission();     
+            }
+        } 
+        else{ 
+            return( true );
+        }
+    }
diff --git a/address_decoder_html/fit/appletref.htm b/address_decoder_html/fit/appletref.htm
new file mode 100644
index 0000000..968eb0a
--- /dev/null
+++ b/address_decoder_html/fit/appletref.htm
@@ -0,0 +1,15 @@
+<html>
+  <head>
+    <title></title>
+  </head>
+  <frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" col="*">
+    <frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
+    <frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
+      <frame name="leftnav" src="leftnav.htm" noresize marginwidth="0" marginheight="0">
+      <frame name="content" src="summary.htm">
+    </frameset>
+    <frame name="applets" src="applet.htm" scrolling="no"> 
+    <frame name="eqns" src="eqns.htm" scrolling="no">
+  </frameset>
+</html>
+
diff --git a/address_decoder_html/fit/asciidoc.htm b/address_decoder_html/fit/asciidoc.htm
new file mode 100644
index 0000000..3455598
--- /dev/null
+++ b/address_decoder_html/fit/asciidoc.htm
@@ -0,0 +1,71 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Text Report</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=375>
+<meta name=layout-width content=798>
+<meta name=date content="05 1, 2002 4:24:59 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Text Report</h1>
+
+<p class="whs1">Selecting Text 
+ Report from the left-hand frame will give you a printable text version 
+ of the fitter report. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->It 
+ contains sections similar to those of the XML report (a summary section, 
+ errors and warnings, mapped logic, function blocks, function block details, 
+ a text-graphical display of the pinout, and a summary of compiler options), 
+ but it is not easily navigable. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->It 
+ is best to use the text report only when you need to print out a hard 
+ copy of the fitter results.</p>
+
+</body>
+
+</html>
diff --git a/address_decoder_html/fit/backtop.jpg b/address_decoder_html/fit/backtop.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..c53782595cd8d780d63aaf797d83054476260daa
GIT binary patch
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diff --git a/address_decoder_html/fit/beginstraight.gif b/address_decoder_html/fit/beginstraight.gif
new file mode 100644
index 0000000000000000000000000000000000000000..1a75177f946392f768da0d5b1ca358c2c38df643
GIT binary patch
literal 352
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literal 0
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diff --git a/address_decoder_html/fit/blank.gif b/address_decoder_html/fit/blank.gif
new file mode 100644
index 0000000000000000000000000000000000000000..1d11fa9ada9e93505b3d736acb204083f45d5fbf
GIT binary patch
literal 43
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literal 0
HcmV?d00001

diff --git a/address_decoder_html/fit/blank.htm b/address_decoder_html/fit/blank.htm
new file mode 100644
index 0000000..18ecdcb
--- /dev/null
+++ b/address_decoder_html/fit/blank.htm
@@ -0,0 +1 @@
+<html></html>
diff --git a/address_decoder_html/fit/briefview.jpg b/address_decoder_html/fit/briefview.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..30069539ceb57d01838d5a0bd53e105ca9e41fb3
GIT binary patch
literal 1254
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literal 0
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diff --git a/address_decoder_html/fit/check.htm b/address_decoder_html/fit/check.htm
new file mode 100644
index 0000000..4dc9562
--- /dev/null
+++ b/address_decoder_html/fit/check.htm
@@ -0,0 +1,10 @@
+<html>
+  <head>
+   <script src="XilinxD.js"> </script>
+   <script src="applet.js"> </script>
+   <script src="plugin.js"> </script>
+
+  </head> 
+  <body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" > 
+  </body> 
+</html> 
diff --git a/address_decoder_html/fit/checkNS4.htm b/address_decoder_html/fit/checkNS4.htm
new file mode 100644
index 0000000..349d05d
--- /dev/null
+++ b/address_decoder_html/fit/checkNS4.htm
@@ -0,0 +1,10 @@
+<html>
+  <head>
+   <script src="xilinxD.js"> </script>
+   <script src="applet.js"> </script>
+   <script src="ns4plugin.js"> </script>
+
+  </head> 
+  <body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" > 
+  </body> 
+</html> 
diff --git a/address_decoder_html/fit/contact.gif b/address_decoder_html/fit/contact.gif
new file mode 100644
index 0000000000000000000000000000000000000000..418b2820765f334b571a94f4033883c8c159d292
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/address_decoder_html/fit/coolrunnerII_logo.jpg b/address_decoder_html/fit/coolrunnerII_logo.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..1b57ddc26165593562ab7d5d7c873cd7133ddac7
GIT binary patch
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z!Ua`18I_*f=_fwepUelwLk9sUd*(>$@vE*VSH`_am9r~OLr6U3yAPd+dj~f<Cs${I
zZwfDwja$*a(BbQVRgkevy1w`k4Mu{#B_~ISF%$=GR*WkEB8^SNTqP9%lV3s2^ixz@
z`EdSeJpxOCWv_?iiz?$PK<G2Zc0iu}u4h!Qz_H!#;YV1pG#+pp$u$b)IKBg+N7Mr^
z;ygziE+gVlOf71|Nzl7U@{dUj_l>c9@nUvyQ_7yWDiA!xk(hrNsPUrHeIP~`VH}yj
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literal 0
HcmV?d00001

diff --git a/address_decoder_html/fit/eqns.js b/address_decoder_html/fit/eqns.js
new file mode 100644
index 0000000..3d35fc4
--- /dev/null
+++ b/address_decoder_html/fit/eqns.js
@@ -0,0 +1,902 @@
+var eqnType = 0;
+var spcStr = "&nbsp;";
+var nlStr = "<br>";
+var tabStr = spcStr + spcStr + spcStr + spcStr + spcStr; 
+var nlTabStr = nlStr + tabStr;
+var rClrS = "<font color='blue'>";
+var rClrE = "</font>";
+var cClrS = "<font color='green'>";
+var cClrE = "</font>";
+
+var abelOper = new Array();
+abelOper["GND"] = new Array("Gnd");
+abelOper["VCC"] = new Array("Vcc");
+abelOper["NOT"] = new Array(rClrS + "!" + rClrE);
+abelOper["AND"] = new Array(rClrS + "*" + rClrE);
+abelOper["OR"]  = new Array(rClrS + "#" + rClrE);
+abelOper["XOR"] = new Array(rClrS + "$" + rClrE);
+abelOper["EQUAL_COLON"] = new Array(":= ");
+abelOper["EQUAL"] = new Array("= ");
+abelOper["ASSIGN"] = new Array("");
+abelOper["OPEN_NEGATE"] = new Array("(");
+abelOper["CLOSE_NEGATE"] = new Array(")");
+abelOper["OPEN_PTERM"] = new Array("");
+abelOper["CLOSE_PTERM"] = new Array("");
+abelOper["OPEN_BRACE"] = new Array("<");
+abelOper["CLOSE_BRACE"] = new Array(">");
+abelOper["INVALID_OPEN_BRACE"] = new Array("<");
+abelOper["INVALID_CLOSE_BRACE"] = new Array(">");
+
+abelOper["ENDLN"] = new Array(";");
+abelOper["COMMENT"] = new Array("//");
+abelOper["IMPORT"] = new Array(";Imported pterms ");
+abelOper["GCK_COM"] = new Array("GCK");
+abelOper["GTS_COM"] = new Array("GTS");
+abelOper["GSR_COM"] = new Array("GSR");
+abelOper["START_EQN"] = new Array("");
+abelOper["END_EQN"] = new Array("");
+
+abelOper["_I"] = new Array(".I");
+abelOper["_T"] = new Array(".T");
+abelOper["_D"] = new Array(".D");
+abelOper["_C"] = new Array(".CLK");
+abelOper["_LH"] = new Array(".LH");
+abelOper["_CLR"] = new Array(".AR");
+abelOper["_PRE"] = new Array(".AP");
+abelOper["_CE"] = new Array(".CE");
+abelOper["_OE"] = new Array(".OE");
+
+abelOper["OE_START"] = new Array(" <= ");
+abelOper["OE_WHEN"] = new Array(" when ");
+abelOper["OE_EQUAL"] = new Array(" = ");
+abelOper["OE_ELSE"] = new Array(" else ");
+abelOper["B0"] = new Array("'0'");
+abelOper["B1"] = new Array("'1'");
+abelOper["BZ"] = new Array("'Z'");
+
+abelOper["FD"] = new Array(".D");
+abelOper["FT"] = new Array(".T");
+abelOper["FDD"] = new Array(".D");
+abelOper["FTD"] = new Array(".T");
+abelOper["LD"] = new Array(".LH");
+abelOper["Q"] = new Array(".Q");
+
+var vhdlOper = new Array();
+vhdlOper["GND"] = new Array("'0'");
+vhdlOper["VCC"] = new Array("'1'");
+vhdlOper["NOT"] = new Array(rClrS + "NOT " + rClrE);
+vhdlOper["AND"] = new Array(rClrS + "AND" + rClrE);
+vhdlOper["OR"]  = new Array(rClrS + "OR" + rClrE);
+vhdlOper["XOR"] = new Array(rClrS + "XOR" + rClrE);
+vhdlOper["EQUAL_COLON"] = new Array("<= ");
+vhdlOper["EQUAL"] = new Array("<= ");
+vhdlOper["ASSIGN"] = new Array("");
+vhdlOper["OPEN_NEGATE"] = new Array("(");
+vhdlOper["CLOSE_NEGATE"] = new Array(")");
+vhdlOper["OPEN_PTERM"] = new Array("(");
+vhdlOper["CLOSE_PTERM"] = new Array(")");
+vhdlOper["OPEN_BRACE"] = new Array("(");
+vhdlOper["CLOSE_BRACE"] = new Array(")");
+vhdlOper["INVALID_OPEN_BRACE"] = new Array("<");
+vhdlOper["INVALID_CLOSE_BRACE"] = new Array(">");
+
+vhdlOper["ENDLN"] = new Array(";");
+vhdlOper["COMMENT"] = new Array("--");
+vhdlOper["IMPORT"] = new Array("");
+vhdlOper["GCK_COM"] = new Array("GCK");
+vhdlOper["GTS_COM"] = new Array("GTS");
+vhdlOper["GSR_COM"] = new Array("GSR");
+vhdlOper["START_EQN"] = new Array(rClrS + "port map" + rClrE + " (");
+vhdlOper["END_EQN"] = new Array(")");
+
+vhdlOper["_I"] = new Array("_I");
+vhdlOper["_T"] = new Array("_T");
+vhdlOper["_D"] = new Array("_D");
+vhdlOper["_C"] = new Array("_C");
+vhdlOper["_LH"] = new Array("_C");
+vhdlOper["_CLR"] = new Array("_CLR");
+vhdlOper["_PRE"] = new Array("_PRE");
+vhdlOper["_CE"] = new Array("_CE");
+vhdlOper["_OE"] = new Array("_OE");
+
+vhdlOper["OE_START"] = new Array(" <= ");
+vhdlOper["OE_WHEN"] = new Array(" when ");
+vhdlOper["OE_EQUAL"] = new Array(" = ");
+vhdlOper["OE_ELSE"] = new Array(" else ");
+vhdlOper["B0"] = new Array("'0'");
+vhdlOper["B1"] = new Array("'1'");
+vhdlOper["BZ"] = new Array("'Z'");
+
+vhdlOper["FD"] = new Array("FDCPE");
+vhdlOper["FT"] = new Array("FTCPE");
+vhdlOper["FDD"] = new Array("FDDCPE");
+vhdlOper["FTD"] = new Array("FTDCPE");
+vhdlOper["LD"] = new Array("LDCP");
+vhdlOper["Q"] = new Array("");
+
+var verOper = new Array();
+verOper["GND"] = new Array("1'b0");
+verOper["VCC"] = new Array("1'b1");
+verOper["NOT"] = new Array(rClrS + "!" + rClrE);
+verOper["AND"] = new Array(rClrS + "&&" + rClrE);
+verOper["OR"]  = new Array(rClrS + "||" + rClrE);
+verOper["XOR"] = new Array(rClrS + "XOR" + rClrE);
+verOper["EQUAL_COLON"] = new Array("= ");
+verOper["EQUAL"] = new Array("= ");
+verOper["ASSIGN"] = new Array("assign ");
+verOper["OPEN_NEGATE"] = new Array("(");
+verOper["CLOSE_NEGATE"] = new Array(")");
+verOper["OPEN_PTERM"] = new Array("(");
+verOper["CLOSE_PTERM"] = new Array(")");
+verOper["OPEN_BRACE"] = new Array("[");
+verOper["CLOSE_BRACE"] = new Array("]");
+verOper["INVALID_OPEN_BRACE"] = new Array("<");
+verOper["INVALID_CLOSE_BRACE"] = new Array(">");
+
+verOper["ENDLN"] = new Array(";");
+verOper["COMMENT"] = new Array("//");
+verOper["IMPORT"] = new Array("");
+verOper["GCK_COM"] = new Array("GCK");
+verOper["GTS_COM"] = new Array("GTS");
+verOper["GSR_COM"] = new Array("GSR");
+verOper["START_EQN"] = new Array(" (");
+verOper["END_EQN"] = new Array(")");
+
+verOper["_I"] = new Array("_I");
+verOper["_T"] = new Array("_T");
+verOper["_D"] = new Array("_D");
+verOper["_C"] = new Array("_C");
+verOper["_LH"] = new Array("_C");
+verOper["_CLR"] = new Array("_CLR");
+verOper["_PRE"] = new Array("_PRE");
+verOper["_CE"] = new Array("_CE");
+verOper["_OE"] = new Array("_OE");
+
+verOper["OE_START"] = new Array(" = ");
+verOper["OE_WHEN"] = new Array(" ? ");
+verOper["OE_EQUAL"] = new Array("");
+verOper["OE_ELSE"] = new Array(" : ");
+verOper["B0"] = new Array("1'b0");
+verOper["B1"] = new Array("1'b1");
+verOper["BZ"] = new Array("1'bz");
+
+verOper["FD"] = new Array("FDCPE");
+verOper["FT"] = new Array("FTCPE");
+verOper["FDD"] = new Array("FDDCPE");
+verOper["FTD"] = new Array("FTDCPE");
+verOper["LD"] = new Array("LDCP");
+verOper["Q"] = new Array("");
+
+var operator = abelOper;
+
+var pterms = new Array();
+var d1 = new Array();
+var d2 = new Array();
+var clk = new Array();
+var set = new Array();
+var rst = new Array();
+var trst = new Array();
+var d1imp = new Array();
+var d2imp = new Array();
+var clkimp = new Array();
+var setimp = new Array();
+var rstimp = new Array();
+var trstimp = new Array();
+var gblclk = new Array();
+var gblset = new Array();
+var gblrst = new Array();
+var gbltrst = new Array();
+var ce = new Array();
+var ceimp = new Array();
+var prld = new Array();
+var specSig = new Array();
+var clkNegs = new Array();
+var setNegs = new Array();
+var rstNegs = new Array();
+var trstNegs = new Array();
+var ceNegs = new Array();
+var fbnand = new Array();
+var inreg = new Array();
+
+var dOneLit = true;
+
+function setOper(type) {
+  if      (type == "1") { operator = vhdlOper; eqnType = 1; }
+  else if (type == "2") { operator = verOper;  eqnType = 2; }
+  else                  { operator = abelOper; eqnType = 0; }
+}
+
+function isXC95() {
+  if (device.indexOf("95") != -1) return true;
+  return false;
+}
+
+function is9500() {
+  if ((device.indexOf("95") != -1) &&
+      (device.indexOf("XL") == -1) &&
+      (device.indexOf("XV") == -1)) return true;
+  return false;
+}
+
+function retSigType(s) {
+  var sigType = sigTypes[s];
+  var str = operator["Q"];
+  if (sigType == "D") str = operator["FD"];
+  else if (sigType == "T") str = operator["FT"];
+  else if (sigType.indexOf("LATCH") != -1) str = operator["LD"];
+  else if (sigType.indexOf("DDEFF") != -1) str = operator["FDD"];
+  else if (sigType.indexOf("DEFF") != -1) str =  operator["FD"];
+  else if (sigType.indexOf("DDFF") != -1) str =  operator["FDD"];
+  else if (sigType.indexOf("TDFF") != -1) str =  operator["FTD"];
+  else if (sigType.indexOf("DFF") != -1) str =   operator["FD"];
+  else if (sigType.indexOf("TFF") != -1) str =   operator["FT"];
+  return str;
+}
+
+function retSigIndex(signal) {
+  for (s=0; s<signals.length; s++) { if (signals[s] == signal) return s; }
+  return -1;
+}
+
+function retSigName(signal) {
+  var str = "";
+  if (specSig[signal]) str += specSig[signal];
+  else str += signal;
+
+  var idx1 = str.indexOf(operator["INVALID_OPEN_BRACE"]);
+  var idx2 = str.indexOf(operator["INVALID_CLOSE_BRACE"]);
+  if ((idx1 != -1) && (idx2 != -1))
+    str = str.substring(0,idx1) + operator["OPEN_BRACE"] +
+          str.substring(idx1+1,idx2) + operator["CLOSE_BRACE"] + 
+          str.substring(idx2+1,str.length);
+  return str;
+}
+
+function removePar(signal) {
+  var str = signal;
+
+  var idx = str.indexOf(operator["OPEN_BRACE"]);
+  if (idx != -1)
+    str = str.substring(0,idx) +
+          str.substring(idx+1,str.indexOf(operator["CLOSE_BRACE"]));
+
+  return str;
+}
+
+
+function isOneLiteral(str) {
+  if ((str.indexOf(operator["AND"]) != -1) ||
+      (str.indexOf(operator["OR"]) != -1) ||
+      (str.indexOf(operator["XOR"]) != -1)) return false;
+  return true;
+}
+
+function updateName(signal, index) {
+  var str;
+
+  var idx = signal.indexOf(operator["OPEN_BRACE"]);
+  if (idx != -1)
+    str = signal.substring(0,idx) +
+          index + signal.substring(idx);
+  else str = signal + index;
+
+  return str;
+}
+
+function retPterm(pt) {
+  var str = "";
+  if (!pterms[pt]) {
+    if (specSig[pt]) pt = specSig[pt];
+    return pt;
+  }
+
+  if (pterms[pt].length > 1) str += operator["OPEN_PTERM"];
+  for (p=0; p<pterms[pt].length; p++) {
+    var sig = pterms[pt][p];
+    if (sig.indexOf("xPUP_0") != -1) continue;
+    if (p>0) str += " " + operator["AND"] + " ";
+    var neg = 0;
+    if (sig.indexOf("/") != -1) {
+      sig = sig.substring(1, sig.length);
+      str += operator["NOT"];
+      neg = 1;
+    }
+
+    str += retSigName(sig);
+  }
+  if (pterms[pt].length > 1) str += operator["CLOSE_PTERM"];
+
+  return str;
+}
+
+function retFBMC(str) {
+  return str.substring(0,str.length-2);
+}
+
+function retD1D2(signal) {
+  var str = "";
+
+  dOneLit = true;
+  if (d1[signal]) {
+    var currImp = "";
+    for (i=0; i<d1[signal].length; i++) {
+      if (!eqnType && d1imp[signal] && (d1imp[signal][i] == "1")) {
+        if (currImp != retFBMC(d1[signal][i]))  {
+          currImp = retFBMC(d1[signal][i]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+      str += retPterm(d1[signal][i]);
+    }
+
+    if (d2[signal]) str += nlTabStr + operator["XOR"]+ spcStr;
+  }
+
+  if (d2[signal]) {
+    var currImp = "";
+    for (i=0; i<d2[signal].length; i++) {
+      if (!eqnType && d2imp[signal] && (d2imp[signal][i] == "1")) {
+        if (currImp != retFBMC(d2[signal][i]))  {
+          currImp = retFBMC(d2[signal][i]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+      str += retPterm(d2[signal][i]);
+    }
+  }
+
+  if (str == "GND") str = operator["GND"];
+  else if (str == "VCC") str = operator["VCC"];
+  else if (!isOneLiteral(str)) {
+    dOneLit = false;
+
+    var type = retSigType(retSigIndex(signal));
+    if ((type == operator["FD"]) ||
+        (type == operator["FDD"])) type = operator["_D"];
+    else if ((type == operator["FT"]) ||
+             (type == operator["FTD"])) type = operator["_T"];
+    else if (type == operator["LD"] && eqnType) type = "_D";
+
+    var tmpStr = updateName(retSigName(signal), type);
+    tmpStr += spcStr + operator["EQUAL_COLON"];
+    var idx = retSigIndex(signal);
+    if (eqnType && sigNegs[idx] == "ON") tmpStr += operator["NOT"] + operator["OPEN_NEGATE"];
+    str = tmpStr + str;
+    if (eqnType && sigNegs[idx] == "ON") str += operator["CLOSE_NEGATE"];
+    str += operator["ENDLN"];
+
+  }
+
+  return str;
+}
+
+function retClk(signal) {
+  var str = "";
+
+  if (clk[signal]) {
+    if (clk[signal].length == 1) {
+      var pterm = retPterm(clk[signal][0]);
+      if (clkNegs[signal]) {
+        str += operator["NOT"];
+        if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"];
+      }
+      str += pterm;
+      if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"];
+    }
+    else {
+      if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      var currImp = "";
+      for (i=0; i<clk[signal].length; i++) {
+        if (!eqnType && clkimp[signal] && (clkimp[signal][i] == "1")) {
+          if (currImp != retFBMC(clk[signal][i]))  {
+            currImp = retFBMC(clk[signal][i]);
+            str += nlStr + operator["IMPORT"] + currImp;
+          }
+        }
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(clk[signal][i]);
+      }
+      if (clkNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"];
+    }
+  }
+  else if (gblclk[signal]) {
+    if (gblclk[signal].length == 1) {
+      var pterm = retPterm(gblclk[signal][0]);
+      if (clkNegs[signal]) {
+        str += operator["NOT"];
+        if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"];
+      }
+      str += pterm;
+      if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"];
+    }
+    else {
+      if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<gblclk[signal].length; i++) {
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(gblclk[signal][i]);
+      }
+      if (clkNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"] + tabStr + cClrS +
+             operator["COMMENT"] + spcStr + operator["GCK_COM"] + cClrE;
+    }
+  }
+  else if (eqnType) str += operator["B0"];
+
+  return str;
+}
+
+function retRst(signal) {
+  var str = "";
+
+  if (rst[signal]) {
+    if (rst[signal].length == 1) {
+      var currImp;
+      if (!eqnType && rstimp[signal] && (rstimp[signal][0] == "1")) {
+        if (currImp != retFBMC(rst[signal][0]))  {
+          currImp = retFBMC(rst[signal][0]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (rstNegs[signal]) str += operator["NOT"];
+      str += retPterm(rst[signal][0]);
+    }
+    else {
+      var currImp = "";
+      if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<rst[signal].length; i++) {
+        if (!eqnType && rstimp[signal] && (rstimp[signal][i] == "1")) {
+          if (currImp != retFBMC(rst[signal][i]))  {
+            currImp = retFBMC(rst[signal][i]);
+            str += nlStr + operator["IMPORT"] + currImp;
+          }
+        }
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(rst[signal][i]);
+      }
+      if (rstNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"];
+    }
+  }
+  else if (gblrst[signal]) {
+    if (gblrst[signal].length == 1) {
+      if (rstNegs[signal]) str += operator["NOT"];
+      str += retPterm(gblrst[signal][0]);
+    }
+    else {
+      if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<gblrst[signal].length; i++) {
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(gblrst[signal][i]);
+      }
+      if (rstNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"] + tabStr + cClrS +
+             operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE;
+    }
+  }
+  else if (eqnType) str += operator["B0"];
+
+  return str;
+}
+
+function retSet(signal) {
+  var str = "";
+
+  if (set[signal]) {
+    if (set[signal].length == 1) {
+      var currImp = "";
+      if (!eqnType && setimp[signal] && (setimp[signal][0] == "1")) {
+        if (currImp != retFBMC(set[signal][0]))  {
+          currImp = retFBMC(set[signal][0]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (setNegs[signal]) str += operator["NOT"];
+      str += retPterm(set[signal][0]);
+    }
+    else {
+      var currImp = "";
+      if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<set[signal].length; i++) {
+        if (!eqnType && setimp[signal] && (setimp[signal][i] == "1")) {
+          if (currImp != retFBMC(set[signal][i]))  {
+            currImp = retFBMC(set[signal][i]);
+            str += nlStr + operator["IMPORT"] + currImp;
+          }
+        }
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(set[signal][i]);
+      }
+      if (setNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"];
+    }
+  }
+  else if (gblset[signal]) {
+    if (gblset[signal].length == 1) {
+      if (setNegs[signal]) str += operator["NOT"];
+      str += retPterm(gblset[signal][0]);
+    }
+    else {
+      if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<gblset[signal].length; i++) {
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(gblset[signal][i]);
+      }
+      if (setNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"] + tabStr + cClrS +
+             operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE;
+    }
+  }
+  else if (eqnType) str += operator["B0"];
+
+  return str;
+}
+
+function retCE(signal) {
+  var str = "";
+
+  if (ce[signal]) {
+    if (ce[signal].length == 1) {
+      var currImp = "";
+      if (!eqnType && ceimp[signal] && (ceimp[signal][0] == "1")) {
+        if (currImp != retFBMC(ce[signal][0]))  {
+          currImp = retFBMC(ce[signal][0]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (ceNegs[signal]) str += operator["NOT"];
+      str += retPterm(ce[signal][0]);
+    }
+    else {
+      var currImp = "";
+      if (ceNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<ce[signal].length; i++) {
+        if (!eqnType && ceimp[signal] && (ceimp[signal][i] == "1")) {
+          if (currImp != retFBMC(ce[signal][i]))  {
+            currImp = retFBMC(ce[signal][i]);
+            str += nlStr + operator["IMPORT"] + currImp;
+          }
+        }
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(ce[signal][i]);
+      }
+      if (ceNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"];
+    }
+  }
+  else if (eqnType) str += operator["B1"];
+
+  return str;
+}
+
+function retTrst(signal) {
+  var str = "";
+  if (trst[signal]) {
+    if (trstNegs[signal])
+      str += operator["NOT"] + operator["OPEN_NEGATE"];
+    for (i=0; i<trst[signal].length; i++) {
+      var currImp = "";
+      if (!eqnType && trstimp[signal] && (trstimp[signal][0] == "1")) {
+        if (currImp != retFBMC(trst[signal][0]))  {
+          currImp = retFBMC(trst[signal][0]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+      str += retPterm(trst[signal][i]);
+    }
+    if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; 
+  }
+  else if (gbltrst[signal]) {
+    if (trstNegs[signal])
+      str += operator["NOT"] + operator["OPEN_NEGATE"];
+    for (i=0; i<gbltrst[signal].length; i++) {
+      if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+      str += retPterm(gbltrst[signal][i]);
+    }
+    if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; 
+  }
+
+  str += operator["ENDLN"];
+  return str;
+}
+
+function retEqn(signal) {
+  var str = inregStr = "";
+  var iStr = qStr = "";
+  var dStr = dEqn = "";
+  var cStr = cEqn = "";
+  var clrStr = clrEqn = "";
+  var preStr = preEqn = "";
+  var ceStr = ceEqn = "";
+  var oeStr = oeEqn = "";
+  var sigName = retSigName(signal);
+
+  var type = retSigType(retSigIndex(signal));
+
+  if (gbltrst[signal] || trst[signal]) iStr = operator["_I"];
+  if (eqnType) qStr = updateName(sigName, iStr);
+
+  if (inreg[signal]) {
+    if (!eqnType)
+      inregStr = operator["COMMENT"] + " Direct Input Register" + nlStr;
+    dStr = retSigName(inreg[signal][0]);
+  }
+  else dStr = retD1D2(signal);
+  if (eqnType && !dOneLit) {
+    dEqn = dStr;
+    dStr = dStr.substring(0,dStr.indexOf(operator["EQUAL_COLON"]));
+  }
+  else if (!eqnType) {
+    if (!dOneLit) dStr = dStr.substring(dStr.indexOf(operator["EQUAL_COLON"])+2);
+    if (sigNegs[retSigIndex(signal)] == "ON") dEqn += operator["NOT"];
+    dEqn += sigName;
+    if ((type == operator["FT"]) ||
+        (type == operator["FTD"])) dEqn += operator["_T"];
+    else if ((type == operator["FD"]) ||
+             (type == operator["FTD"])||
+             (type == operator["LD"])) dEqn += operator["_D"];
+    dEqn += " ";
+    if ((type != operator["Q"]) && (type != operator["LD"]))
+      dEqn += operator["EQUAL_COLON"];
+    else  dEqn += operator["EQUAL"];
+    dEqn += dStr;
+    if (dOneLit) dEqn += operator["ENDLN"];
+  }
+
+  cStr = retClk(signal);
+  if (eqnType && !isOneLiteral(cStr)){
+    cEqn = cStr;
+    if (cEqn.indexOf(operator["ENDLN"]) == -1)
+      cEqn += operator["ENDLN"];
+    cStr = updateName(sigName, operator["_C"]);
+  }
+  else if (!eqnType && cStr) {
+    cEqn += cStr;
+    cStr = tabStr + sigName;
+    if (type == operator["LD"]) cStr += operator["_LH"];
+    else                        cStr += operator["_C"];
+    if (cEqn.indexOf(operator["ENDLN"]) == -1)
+      cEqn += operator["ENDLN"];
+    if (gblclk[signal]) cEqn += tabStr + operator["COMMENT"] + " " + operator["GCK_COM"];
+  }
+
+  clrStr = retRst(signal);
+  if (eqnType && !isOneLiteral(clrStr)){
+    clrEqn = clrStr;
+    if (cEqn.indexOf(operator["ENDLN"]) == -1)
+      clrEqn += operator["ENDLN"];
+    clrStr = updateName(sigName, operator["_CLR"]);
+  }
+  else if (!eqnType && clrStr) {
+    clrEqn += clrStr;
+    clrStr = tabStr + sigName + operator["_CLR"];
+    if (clrEqn.indexOf(operator["ENDLN"]) == -1)
+      clrEqn += operator["ENDLN"];
+    if (gblrst[signal]) clrEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"];
+  }
+
+  preStr = retSet(signal);
+  if (eqnType && !isOneLiteral(preStr)){
+    preEqn = preStr;
+    if (cEqn.indexOf(operator["ENDLN"]) == -1)
+      preEqn += operator["ENDLN"];
+    preStr = updateName(sigName, operator["_PRE"]);
+  }
+  else if (!eqnType && preStr) {
+    preEqn += preStr;
+    preStr = tabStr + sigName + operator["_PRE"];
+    if (preEqn.indexOf(operator["ENDLN"]) == -1)
+      preEqn += operator["ENDLN"];
+    if (gblset[signal]) preEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"];
+  }
+
+  if (!is9500()) {
+    ceStr = retCE(signal); 
+    if (eqnType && !isOneLiteral(ceStr)){
+      ceEqn = ceStr;
+      if (cEqn.indexOf(operator["ENDLN"]) == -1)
+        ceEqn += operator["ENDLN"];
+      ceStr = updateName(sigName, operator["_CE"]);
+    }
+    else if (!eqnType && ceStr) {
+      ceEqn += ceStr;
+      ceStr = tabStr + sigName + operator["_CE"];
+      if (ceEqn.indexOf(operator["ENDLN"]) == -1)
+        ceEqn += operator["ENDLN"];
+    }
+  }
+
+  if (eqnType && trst[signal]) oeEqn = retTrst(signal)
+  else if (!eqnType && (trst[signal] || gbltrst[signal])) oeEqn = retTrst(signal);
+
+
+  var newline = false;
+  if (type == "") {
+    str += operator["ASSIGN"] + qStr + " " + operator["EQUAL"];
+    if (dOneLit) str += dStr;
+    else         str += dEqn.substring(dEqn.indexOf(operator["EQUAL"])+2);
+    if (oeEqn != "") {
+      var oeStr = updateName(sigName, operator["_OE"]);
+      if (eqnType == 1) {
+        str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr +
+               operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] +
+               operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"];
+      }
+      else if (eqnType == 2) {
+        str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] +
+               oeStr + operator["OE_WHEN"] + qStr +
+               operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"];
+      }
+      str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
+    }
+  }
+  else {
+    if (eqnType == 1) {
+      str += type + "_" + removePar(retSigName(signal)) +
+             ": " + type + " " + operator["START_EQN"] +
+             qStr + ", " + dStr + ", " + cStr + ", " +
+             clrStr + ", " + preStr;
+      if (!is9500() && (type != operator["LD"])) str += ", " + ceStr;
+      str += operator["END_EQN"] + operator["ENDLN"];
+      newline = true;
+    }
+    else if (eqnType == 2) {
+      str += type + " " +
+             type + "_" + removePar(retSigName(signal)) +
+             operator["START_EQN"] +
+             qStr + ", " + dStr + ", " + cStr + ", " +
+             clrStr + ", " + preStr;
+      if (!is9500() && (type != operator["LD"])) str += ", " + ceStr;
+      str += operator["END_EQN"] + operator["ENDLN"];
+      newline = true;
+    }
+
+    if (dEqn != "") {
+      if (newline) str += nlStr;
+      if (inregStr) str += inregStr;
+      str += operator["ASSIGN"] + dEqn;
+    }
+
+    if (cEqn != "") {
+      if (newline || !eqnType) str += nlStr;
+      str += operator["ASSIGN"] + cStr + " " + operator["EQUAL"] + " " + cEqn;
+    }
+
+    if (clrEqn != "")  {
+      if (newline || !eqnType) str += nlStr;
+      str += operator["ASSIGN"] + clrStr + " " + operator["EQUAL"] + " " + clrEqn;
+    }
+
+
+    if (preEqn != "")  {
+      if (newline || !eqnType) str += nlStr;
+      str += operator["ASSIGN"] + preStr + " " + operator["EQUAL"] + " " + preEqn;
+    }
+
+    if (ceEqn != "")  {
+      if (newline || !eqnType) str += nlStr;
+      str += operator["ASSIGN"] + ceStr + " " + operator["EQUAL"] + " " + ceEqn;
+    }
+
+    if (oeEqn != "") {
+      if (eqnType == 1) {
+        var oeStr = updateName(sigName, operator["_OE"]);
+        str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr +
+               operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] +
+               operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"];
+        str += nlStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
+      }
+      else if (eqnType == 2) {
+        var oeStr = updateName(sigName, operator["_OE"]);
+        str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + oeStr + operator["OE_WHEN"] + qStr +
+               operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"];
+        str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
+      }
+      else {
+        var oeStr = sigName + operator["_OE"];
+        if (gbltrst[signal])
+          oeEqn += tabStr + operator["COMMENT"] + " " + operator["GTS_COM"];
+        str += nlStr + tabStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
+      }
+    }
+  }
+
+  return str;
+}
+
+function retFamily() {
+  var family = "xc9500";
+  if (device.indexOf("XC2C") != -1) {
+    if (device.indexOf("S") != -1)  family = "cr2s";
+    else                            family = "xbr";
+  }
+  else if (device.indexOf("XCR3") != -1) family = "xpla3";
+  else {
+    if (device.indexOf("XL") != -1)  family = "xc9500xl";
+    if (device.indexOf("XV") != -1)  family = "xc9500xv";
+  }
+
+  return family;
+}
+
+function retDesign() { return design; }
+
+function getPterm(pt, type) { 
+  if (type) return type + " = " + retPterm(pt);
+  return "PT" + pt.substring(pt.indexOf('_')+1,pt.length) + " = " + retPterm(pt);
+}
+
+function getPRLDName(prld) {
+  if (eqnType != 0) return prld;
+  else if (prld == "VCC") return "S";
+  return "R";
+}
+
+function retFbnand(signal) {
+  var str = operator["COMMENT"] + spcStr + "Foldback NAND";
+  str += nlStr + retSigName(signal) + spcStr + operator["EQUAL"] + spcStr;
+  for (i=0; i<fbnand[signal].length; i++) {
+    if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+    str += retPterm(fbnand[signal][i]);
+  }
+
+  return str;
+}
+
+function getEqn(signal) { return retEqn(signal); }
+
+function retUimPterm(pt) {
+  var str = "";
+  if (!uimPterms[pt]) return pt;
+  for (p=0; p<uimPterms[pt].length; p++) {
+    if (p>0) str += spcStr + operator["AND"] + spcStr;
+    var sig = uimPterms[pt][p];
+    if (sig.indexOf("/") != -1) sig = sig.substring(1, sig.length);
+
+    str += retSigName(sig);
+  }
+  return str;
+}
+
+function retUimEqn(signal) {
+  var str = operator["COMMENT"] + spcStr + "FC Node" + nlStr;
+  var neg = 0;
+  if (uimSigNegs[s] == "ON") str += operator["NOT"];
+  str += retSigName(signal) + spcStr + operator["EQUAL"];
+  str += retUimPterm(signal) + ";";
+
+  return str;
+}
+
+function retLegend(url) {
+  var str = "";
+  if (!eqnType && !isXC95()) {
+    str = "Legend: " + "&lt;" + "signame" + "&gt;" + ".COMB = combinational node mapped to ";
+    str += "the same physical macrocell as the FastInput \"signal\" (not logically related)";
+  }
+  else if (eqnType) {
+    str = "Register Legend:";
+    if (is9500()) {
+      str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE);";
+      str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE);";
+      str += nlTabStr + "LDCP  (Q,D,G,CLR,PRE);";
+    }
+    else if (retFamily() == "xbr") {
+      str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "FDDCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "FTDCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "LDCP  (Q,D,G,CLR,PRE);";
+    }
+    else {
+      str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "LDCP  (Q,D,G,CLR,PRE);";
+    }
+  }
+  return str;
+}
+
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+</head>
+<body onload="javascript:init()">
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diff --git a/address_decoder_html/fit/equationsdoc.htm b/address_decoder_html/fit/equationsdoc.htm
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+++ b/address_decoder_html/fit/equationsdoc.htm
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+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Equations</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
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+
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+<h1>Equations</h1>
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+function init() {
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diff --git a/address_decoder_html/fit/errorsdoc.htm b/address_decoder_html/fit/errorsdoc.htm
new file mode 100644
index 0000000..460449a
--- /dev/null
+++ b/address_decoder_html/fit/errorsdoc.htm
@@ -0,0 +1,91 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Errors</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=715>
+<meta name=layout-width content=798>
+<meta name=date content="05 1, 2002 4:22:26 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs2 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs3 {font-family: arial, sans-serif; font-size: 10pt;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
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+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Errors/Warnings</h1>
+
+<p class="whs1">The Errors/Warnings 
+ section of the report lists all of the error, warning, and information 
+ messages generated by the fitter. By default, this section will display 
+ the number of each kind of message you have and the full text of the messages, 
+ but checkboxes at the top of the screen allow you to filter message details 
+ as you choose. </p>
+
+<p class="whs2">Checking all 
+ the boxes will give you a display like this:</p>
+
+<p><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='xml6.jpg' x-maintain-ratio='TRUE' width='540' height='254' border='0'>");}
+else
+{ document.write("<img src='xml6.jpg' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 254px; float: none;' width='540' height='254' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs3">Deselecting 
+ the Warning box in this particular example would result in this less detailed 
+ display:</p>
+
+<p><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='xml7.jpg' x-maintain-ratio='TRUE' width='576' height='226' border='0'>");}
+else
+{ document.write("<img src='xml7.jpg' x-maintain-ratio='TRUE' style='border: none; width: 576px; height: 226px; float: none;' width='576' height='226' border='0'>");}
+//--></SCRIPT></p>
+
+</body>
+
+</html>
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diff --git a/address_decoder_html/fit/fbs.js b/address_decoder_html/fit/fbs.js
new file mode 100644
index 0000000..8e97ea6
--- /dev/null
+++ b/address_decoder_html/fit/fbs.js
@@ -0,0 +1,9 @@
+function showFBApplet(fb) { parent.leftnav.showAppletFB(fb); }
+function showFB(fb) { parent.leftnav.showFB(fb); }
+function showMC(mc) { parent.leftnav.showAppletMC(mc); }
+function showPT(pterm, type) { parent.leftnav.showPterm(pterm, type); }
+function showPin(pin) { parent.leftnav.showAppletPin(pin); }
+function showEqn(sig) { parent.leftnav.showEqn(sig); }
+function showFBDetail(fb) { parent.leftnav.showFB(fb); }
+function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); }
+function showTop() { parent.leftnav.showTop(); }
diff --git a/address_decoder_html/fit/fbs_FBdoc.htm b/address_decoder_html/fit/fbs_FBdoc.htm
new file mode 100644
index 0000000..5d529aa
--- /dev/null
+++ b/address_decoder_html/fit/fbs_FBdoc.htm
@@ -0,0 +1,307 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Function Block Specifics</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=3556>
+<meta name=layout-width content=670>
+<meta name=date content="05 24, 2002 6:03:49 PM">
+
+
+
+<style>
+<!--
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+p.whs31 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs32 {font-family: arial, sans-serif; font-size: 10pt;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
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+	origHeight = innerHeight;
+	onresize = reDo;
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+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Function Block Specifics</h1>
+
+<p class="whs1">To access specific 
+ details for a particular function block, click on that function block 
+ in either the <a href="maplogicdoc.htm">Mapped Logic</a>, <a href="mapinputdoc.htm">Mapped 
+ Inputs</a>, or <a href="fbsdoc.htm" style="font-family: arial, sans-serif; font-size: 10pt;">Function 
+ Blocks</a> sections of the fitter report. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ function block details page displays a table of details about the particular 
+ function block you selected, a view button you can click to show a graphical 
+ display of the function block, and a pulldown menu you can use to select 
+ other function blocks to see.</p>
+
+<p class="whs2">The Table</p>
+
+<p class="whs3">The View</p>
+
+<p><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='xml5.jpg' x-maintain-ratio='TRUE' width='648' height='397' border='0'>");}
+else
+{ document.write("<img src='xml5.jpg' x-maintain-ratio='TRUE' style='border: none; width: 648px; height: 397px; float: none;' width='648' height='397' border='0'>");}
+//--></SCRIPT></p>
+
+<h4 class="whs4"><a name=table></a>The Table</h4>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The table 
+ at the top of the function block details page provides the following information 
+ about the function block:</FONT></span> 
+
+<ul type="disc" class="whs5">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ signal name </FONT></span></li>
+</ul>
+
+<p class="whs6"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Clicking on 
+ a signal name will open a new window with the equations for that signal. 
+ </FONT></span></p>
+
+<ul type="disc" class="whs7">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ total product terms used </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->A 
+ list of product terms</FONT></span></li>
+</ul>
+
+<p class="whs8"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Clicking on 
+ a <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->product 
+ term will open a new window with the equations for that term. </FONT></span></p>
+
+<ul type="disc" class="whs9">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ macrocell number in which the function block is located</FONT></span></li>
+</ul>
+
+<p class="whs10"><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><span 
+ style="font-weight: bold;"><B>Note:</B></span> Clicking on the underscored macrocell 
+ number will provide a graphical display of the macrocell that looks like 
+ this:</FONT></span></p>
+
+<p class="whs11"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
+else
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
+//--></SCRIPT>.</p>
+
+<ul type="disc" class="whs12">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ power mode</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pin number</FONT></span></li>
+</ul>
+
+<ul type="disc" class="whs13">
+	
+	<li class=kadov-p><p class="whs14"><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><span 
+ style="font-weight: bold;"><B>N</B></span>ote:</FONT></span><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> 
+ Clicking on the underscored pin number will provide the pin layout diagram 
+ for the highlighted pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling 
+ your mouse over the colored pin will pop up a tooltip with the signal 
+ name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the 
+ I/O style, the slew rate, and/or any constraints assigned to the pin:</FONT></span></p></li>
+</ul>
+
+<p class="whs15"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
+else
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
+//--></SCRIPT></p>
+
+<ul type="disc" class="whs16">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pin type</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pin use </FONT></span></li>
+</ul>
+
+<p class="whs17"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Moving your 
+ mouse cursor over an &quot;I&quot; in the Pin Use column will display 
+ that input signal as a tooltip.</FONT></span></p>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Below the 
+ resource table you will find a list of signals used by logic in the function 
+ block you are viewing. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ list displays output signals as links. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Clicking 
+ on an output signal link will open a new window showing the equations 
+ for that signal.</FONT></span> 
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp; 
+ 
+
+<p class="whs18"><span style="font-family: arial, sans-serif;
+											font-size: 10pt;
+											font-weight: bold;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"> <FONT SIZE=2 style="font-size:10pt;"><!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->There 
+ is also a <SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' width='68' height='28' border='0'>");}
+else
+{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' style='border: none; width: 68px; height: 28px; float: none;' width='68' height='28' border='0'>");}
+//--></SCRIPT> button below the table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Click 
+ this button to open a new window describing all of the acronyms used in 
+ the function block table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can select either brief descriptions or more detailed descriptions by 
+ clicking the &quot;Verbose&quot; button at the top of the window.</FONT></span> 
+ </p>
+
+<h4 class="whs19"><a name=view></a>The View</h4>
+
+<p class="whs20">When you click 
+ on the <SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' width='61' height='53' border='0'>");}
+else
+{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' style='border: none; width: 61px; height: 53px; float: none;' width='61' height='53' border='0'>");}
+//--></SCRIPT>button above the table, a new window will open with 
+ a graphical display of the function block you are examining. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ pins are all color-coded: input pins are green, output pins are blue, 
+ and clocks are magenta:</p>
+
+<p class="whs21"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='fb1.gif' x-maintain-ratio='TRUE' width='482' height='378' border='0'>");}
+else
+{ document.write("<img src='fb1.gif' x-maintain-ratio='TRUE' style='border: none; width: 482px; height: 378px; float: none;' width='482' height='378' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs22">Right-click 
+ anywhere within the window to pull up a menu that allows you to zoom in 
+ or out for easier viewing. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
+
+<p class="whs23">This menu also 
+ allows you choose to see all of the input connections, all of the output 
+ connections, or both at once. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Like 
+ the pins, the signals are color-coded: inputs are red, outputs are yellow, 
+ and macrocell connections are aqua:</p>
+
+<p class="whs24"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='fb.gif' x-maintain-ratio='TRUE' width='497' height='377' border='0'>");}
+else
+{ document.write("<img src='fb.gif' x-maintain-ratio='TRUE' style='border: none; width: 497px; height: 377px; float: none;' width='497' height='377' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs25">To examine 
+ the signals of single pins, simply click the pin whose signals you wish 
+ to see. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->To 
+ examine multiple pins without having to see everything at once, hold down 
+ the control key while you click the pins you want to view. </p>
+
+<p class="whs26">To view the 
+ signals for individual macrocells:</p>
+
+<ul type="disc" class="whs27">
+	
+	<li class=kadov-p><p class="whs28">Click 
+ the inside edge of the macrocell to display its macrocell connections 
+ and inputs. </p></li>
+	
+	<li class=kadov-p><p class="whs29">Click 
+ the outer edge to display its output signals</p></li>
+	
+	<li class=kadov-p><p class="whs30">Click 
+ in the center to display everything</p></li>
+	
+	<li class=kadov-p><p class="whs31">Double 
+ click in the center to open a new window with a detailed macrocell diagram</p></li>
+</ul>
+
+<p class="whs32">&nbsp;</p>
+
+</body>
+
+</html>
diff --git a/address_decoder_html/fit/fbsdoc.htm b/address_decoder_html/fit/fbsdoc.htm
new file mode 100644
index 0000000..04a25ff
--- /dev/null
+++ b/address_decoder_html/fit/fbsdoc.htm
@@ -0,0 +1,103 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Function Blocks</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=405>
+<meta name=layout-width content=615>
+<meta name=date content="05 24, 2002 5:49:51 PM">
+
+
+
+<style>
+<!--
+ul.whs1 {list-style: disc;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Function Blocks</h1>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The Function 
+ Blocks page provides a summary of all function blocks' resources. Clicking 
+ on one of the function blocks in the summary table will display the <a href="fbs_FBdoc.htm">specific details</a> for that function block. <!--kadov_tag{{<spaces>}}-->&nbsp;</FONT></span><!--kadov_tag{{</spaces>}}-->
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp; 
+ 
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The summary table 
+ contains the following: <!--kadov_tag{{<spaces>}}-->&nbsp;</FONT></span><!--kadov_tag{{</spaces>}}-->
+
+<ul type="disc" class="whs1">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ function block</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of macrocell used </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of function block inputs used </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of product terms used</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pins used</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ local control terms used</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of foldback NANDs used (CoolRunner only)</FONT></span></li>
+</ul>
+
+</body>
+
+</html>
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diff --git a/address_decoder_html/fit/genmsg.htm b/address_decoder_html/fit/genmsg.htm
new file mode 100644
index 0000000..0146e6d
--- /dev/null
+++ b/address_decoder_html/fit/genmsg.htm
@@ -0,0 +1,17 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
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+<body>
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+This file is currently being generated. Please recheck the link after some
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+</dl>
+
+</body>
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diff --git a/address_decoder_html/fit/home.gif b/address_decoder_html/fit/home.gif
new file mode 100644
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GIT binary patch
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diff --git a/address_decoder_html/fit/index.htm b/address_decoder_html/fit/index.htm
new file mode 100644
index 0000000..831ba39
--- /dev/null
+++ b/address_decoder_html/fit/index.htm
@@ -0,0 +1,15 @@
+<html>
+  <head>
+    <title></title>
+  </head>
+  <frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" cols="*">
+    <frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
+    <frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
+      <frame name="leftnav" src="leftnav.htm" noresize marginwidth="0" marginheight="0">
+      <frame name="content" src="summary.htm">
+    </frameset>
+    <frame name="applets" src="applet.htm" scrolling="no"> 
+    <frame name="eqns" src="eqns.htm" scrolling="no">
+  </frameset>
+</html>
+
diff --git a/address_decoder_html/fit/leftnav.js b/address_decoder_html/fit/leftnav.js
new file mode 100644
index 0000000..b06978e
--- /dev/null
+++ b/address_decoder_html/fit/leftnav.js
@@ -0,0 +1,176 @@
+var noAppletOnClicked = 1;
+var appletMsg = "";
+var waitWin;
+var oldIn =  oldOut = oldGbl = oldIsp = oldVcc = oldGnd = oldProhibit = oldUnuse = oldNc = 1;
+var oldInfo = oldWarn = oldError = 1;
+var verbose = 0;
+var dispPage, mapLogPage, mapInPage, unLogPage, unInPage;
+var javaPermission = 0;
+var abelEqn = vhdlEqn = verEqn = "";
+
+function IsNS() {
+  return ((navigator.appName.indexOf("Netscape") >= 0) &&
+          (parseFloat(navigator.appVersion) >= 4)) ? true : false;
+}
+
+function openWait() {
+  waitWin = window.open("wait.htm", "wait",
+                        "toolbar=no,location=no,"+
+                        "directories=no,status=no,menubar=no,scrollbars=no,"+
+                        "resizable=no,width=300,height=50" );
+}
+
+function closeWait() { if (waitWin) waitWin.close(); }
+
+function popHTML(name, str) {
+  document.options.htmlStr.value = str;
+  if (name.indexOf(":") > -1)
+    name = name.substring(0,name.indexOf(":")) + "_COLON_" +
+           name.substring(name.indexOf(":")+1,name.length);
+  if (name.indexOf(".") > -1)
+    name = name.substring(0,name.indexOf(".")) + "_DOT_" +
+           name.substring(name.indexOf(".")+1,name.length);
+  var win = window.open("result.htm", "win_"+name,
+                        "toolbar=no,location=no,"+
+                        "directories=no,status=no,menubar=no,scrollbars=yes,"+
+                        "resizable=yes,width=300,height=200" );
+  win.focus();
+}
+
+function setAppletPermission() { appletPermission = 1; }
+function getAppletPermission() { return( appletPermission); }
+function getAppletMsg() { return(appletMsg); }
+function setAppletMsg(msg) { appletMsg = msg; }
+
+
+function showHTML(page, html) {
+
+      dispPage = html;
+      document.options.currPage.value = page;
+      parent.content.location.href = html;
+}
+
+function showTop() { showHTML(document.options.currPage.value, dispPage); }
+
+function setVerbose(value) { verbose = value; }
+
+function showLegend(url, w, h) {
+  if (verbose == 1) {
+    url = url.substring(0,name.indexOf(".htm")) + "V.htm";
+  }
+  var win = window.open(url, 'win',
+              'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h);
+  win.focus();
+}
+
+function showSummary()    { showHTML("summary", "summary.htm"); }
+function showOptions()    { showHTML("options", "options.htm"); }
+function showFBSum()      { showHTML("fbs", "fbs.htm"); }
+function showFB(fb)       { showHTML("fbs_FB", "fbs_"+fb+".htm"); }
+function showPinOut()     { showHTML("pins", "pins.htm"); }
+function showError()      { showHTML("errors", "errs.htm"); }
+
+function showEqnAll()     {
+  openWait();
+  parent.eqns.setOper(currEqnType);
+  if (currEqnType == defEqnType) showHTML("equations", "defeqns.htm");
+  else if (currEqnType == 0) {
+    if (abelEqn == "") abelEqn = parent.eqns.getEqnList();
+    document.options.htmlStr.value = abelEqn;
+    showHTML("equations", "equations.htm");
+  }
+  else if (currEqnType == 1) {
+      if (vhdlEqn == "") vhdlEqn = parent.eqns.getEqnList();
+      document.options.htmlStr.value = vhdlEqn;
+      showHTML("equations", "equations.htm");
+  }
+  else {
+      if (verEqn == "") verEqn = parent.eqns.getEqnList();
+      document.options.htmlStr.value = verEqn;
+      showHTML("equations", "equations.htm");
+  }
+  closeWait();
+}
+
+function showEqn(sig)     {
+  popHTML(sig, parent.eqns.getEqn(sig));
+}
+
+function showPterm(pterm, type) {
+  popHTML(pterm, parent.eqns.getPterm(pterm, type));
+}
+
+function showAscii() { showHTML("ascii", "ascii.htm"); }
+function showTiming() { showHTML("time", "time.htm"); }
+
+function showHelp() { 
+  var helpDoc = document.options.currPage.value + "doc.htm";
+  popWin(helpDoc);
+}
+
+function getMapParam(type) {
+  var paramStr = "";
+  switch(type) {
+    case 1: paramStr  += "10"; break;
+    case 2: paramStr  += "01"; break;
+    case 3: paramStr  += "11"; break;
+    case 4: paramStr  += "02"; break;
+    case 5: paramStr  += "12"; break;
+    default: paramStr += "00";
+  }
+
+  return paramStr;
+}
+
+function showMappedLogics(type) {
+  showHTML("maplogic", "maplogic_" + getMapParam(type) + ".htm");
+}
+
+function showMappedInputs(type) {
+  showHTML("mapinput", "mapinput_" + getMapParam(type) + ".htm");
+}
+
+function showUnMappedLogics(type) {
+  showHTML("unmaplogic", "unmaplogic_" + getMapParam(type) + ".htm");
+}
+
+function showUnMappedInputs(type) {
+  showHTML("unmapinput", "unmapinput_" + getMapParam(type) + ".htm");
+}
+
+function doEqnFormat() {
+  var type = document.options.eqnType.options[document.options.eqnType.options.selectedIndex].value;
+  currEqnType = type;
+  parent.eqns.setOper(currEqnType);
+  if (document.options.currPage.value == "equations") showEqnAll();
+}
+
+function showNoAppletAlert() {
+  window.alert("No Applet supported for this session!!!");
+}
+
+function showAppletMC(mc) {
+  if (parent.applets) parent.applets.showAppletGraphicMC(mc);
+  else showNoAppletAlert();
+}
+
+function showAppletFB(fb) {
+  if (parent.applets) parent.applets.showAppletGraphicFB(fb);
+  else showNoAppletAlert();
+}
+
+function showAppletPin(pin)  {
+  if (parent.applets) parent.applets.showAppletGraphicPin(pin);
+  else showNoAppletAlert();
+}
+
+function printAppletPkg() {
+  if (parent.applets) parent.applets.printAppletPkg();
+  else showNoAppletAlert();
+}
+
+function popWin(url) {
+  var win = window.open(url, 'win',
+              'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600');
+  win.focus();
+}
diff --git a/address_decoder_html/fit/legend.gif b/address_decoder_html/fit/legend.gif
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diff --git a/address_decoder_html/fit/logic_legXC95.htm b/address_decoder_html/fit/logic_legXC95.htm
new file mode 100644
index 0000000..e253a0b
--- /dev/null
+++ b/address_decoder_html/fit/logic_legXC95.htm
@@ -0,0 +1,2 @@
+<html><body><pre>
+</pre></body></html>
diff --git a/address_decoder_html/fit/logic_legXbr.htm b/address_decoder_html/fit/logic_legXbr.htm
new file mode 100644
index 0000000..9883d2d
--- /dev/null
+++ b/address_decoder_html/fit/logic_legXbr.htm
@@ -0,0 +1,15 @@
+<html><body><pre>
+I/O Style - OD    - OpenDrain
+          - PU    - Pullup
+          - KPR   - Keeper
+          - S     - SchmittTrigger
+          - DG    - DataGate
+Reg Use   - LATCH - Transparent latch
+          - DFF   - D-flip-flop
+          - DEFF  - D-flip-flop with clock enable
+          - TFF   - T-flip-flop
+          - TDFF  - Dual-edge-triggered T-flip-flop
+          - DDFF  - Dual-edge-triggered flip-flop
+          - DDEFF - Dual-edge-triggered flip-flop with clock enable
+          /S (after any above flop/latch type) indicates initial state is Set
+</pre></body></html>
diff --git a/address_decoder_html/fit/logic_legXpla3.htm b/address_decoder_html/fit/logic_legXpla3.htm
new file mode 100644
index 0000000..c0e6f4a
--- /dev/null
+++ b/address_decoder_html/fit/logic_legXpla3.htm
@@ -0,0 +1,3 @@
+<html><body><pre>
+Legend: PU  - Pull Up
+</pre></body></html>
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diff --git a/address_decoder_html/fit/mapinputdoc.htm b/address_decoder_html/fit/mapinputdoc.htm
new file mode 100644
index 0000000..9f7a3c9
--- /dev/null
+++ b/address_decoder_html/fit/mapinputdoc.htm
@@ -0,0 +1,158 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Mapped Inputs</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=1376>
+<meta name=layout-width content=615>
+<meta name=date content="05 24, 2002 5:49:24 PM">
+
+
+
+<style>
+<!--
+ul.whs1 {list-style: disc;}
+p.whs2 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs3 {list-style: disc;}
+ul.whs4 {list-style: disc;}
+p.whs5 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs6 {margin-left: 80px;}
+p.whs7 {margin-left: 80px; font-weight: bold; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs8 {margin-left: 80px; font-weight: bold; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs9 {list-style: disc;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Mapped Inputs</h1>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Like the 
+ <a href="maplogicdoc.htm">Mapped Logic</a> section, the Mapped Inputs 
+ section of the report displays a table detailing the resources allocated 
+ by the fitter to mapped inputs. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Again, 
+ the table can be sorted by Signal Name, Function Block, or Pin Number 
+ by clicking on the appropriate table headings. <!--kadov_tag{{<spaces>}}-->&nbsp;</FONT></span><!--kadov_tag{{</spaces>}}-->
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp; 
+ 
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The inputs table 
+ contains the following: </FONT></span>
+
+<ul type="disc" class="whs1">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ input signal name </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ function block number</FONT></span></li>
+</ul>
+
+<p class="whs2"><span style="font-weight: bold;"><B>Note:</B></span> 
+ Clicking on the function block will provide a detailed table of all the 
+ block's resources and a graphical display of the function block diagram 
+ (see <a href="fbs_FBdoc.htm">Function Block Specifics</a> for more details).</p>
+
+<ul type="disc" class="whs3">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ macrocell number</FONT></span></li>
+</ul>
+
+<ul type="disc" class="whs4">
+	
+	<li class=kadov-p><p class="whs5"><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><span style="font-weight: bold;"><B>N</B></span>ote:</FONT></span> 
+ Clicking on the underscored macrocell number will provide a graphical 
+ display of the macrocell that looks like this:</FONT></span></p></li>
+	
+	<li class=kadov-p
+		class=kadov-p><!--kadov_tag{{<implicit_p>}}--><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
+else
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
+//--></SCRIPT>.The pin number</FONT></span></li>
+</ul>
+
+<p class="whs6"><span style="font-weight: bold;"><B>Note:</B></span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Clicking on 
+ the underscored pin number will provide the pin layout diagram for the 
+ highlighted pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling 
+ your mouse over the colored pin will pop up a tooltip with the signal 
+ name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the 
+ I/O style, the slew rate, and/or any constraints assigned to the pin:</FONT></span></p>
+
+<p class="whs7"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
+else
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs8">&nbsp;</p>
+
+<ul type="disc" class="whs9">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pin type</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pin use </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ I/O standard</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ I/O style</FONT></span></li>
+</ul>
+
+</body>
+
+</html>
diff --git a/address_decoder_html/fit/maplogic.js b/address_decoder_html/fit/maplogic.js
new file mode 100644
index 0000000..e40c8f2
--- /dev/null
+++ b/address_decoder_html/fit/maplogic.js
@@ -0,0 +1,23 @@
+function showFB(fb) { parent.leftnav.showFB(fb); }
+function showMC(mc) { parent.leftnav.showAppletMC(mc); }
+function showEqn(sig) { parent.leftnav.showEqn(sig); }
+function showPin(pin) { parent.leftnav.showAppletPin(pin); }
+function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); }
+function showTop() { parent.leftnav.showTop(); }
+
+function Sort(x) {
+  switch (x) {
+    case 0: parent.leftnav.showMappedLogics(0); break;
+    case 1: parent.leftnav.showMappedLogics(2); break;
+    case 2: parent.leftnav.showMappedLogics(4); break;
+    case 10: parent.leftnav.showMappedInputs(0); break;
+    case 11: parent.leftnav.showMappedInputs(2); break;
+    case 12: parent.leftnav.showMappedInputs(4); break;
+    case 20: parent.leftnav.showUnMappedLogics(0); break;
+    case 21: parent.leftnav.showUnMappedLogics(2); break;
+    case 22: parent.leftnav.showUnMappedLogics(4); break;
+    case 30: parent.leftnav.showUnMappedInputs(0); break;
+    case 31: parent.leftnav.showUnMappedInputs(2); break;
+    case 32: parent.leftnav.showUnMappedInputs(4); break;
+  }
+}
diff --git a/address_decoder_html/fit/maplogicdoc.htm b/address_decoder_html/fit/maplogicdoc.htm
new file mode 100644
index 0000000..efed6ca
--- /dev/null
+++ b/address_decoder_html/fit/maplogicdoc.htm
@@ -0,0 +1,185 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Mapped Logic</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=1506>
+<meta name=layout-width content=639>
+<meta name=date content="05 24, 2002 5:49:09 PM">
+
+
+
+<style>
+<!--
+ul.whs1 {list-style: disc;}
+p.whs2 {margin-left: 80px;}
+ul.whs3 {list-style: disc;}
+p.whs4 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs5 {list-style: disc;}
+p.whs6 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs7 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs8 {list-style: disc;}
+p.whs9 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs10 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs11 {list-style: disc;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Mapped Logic</h1>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The Mapped 
+ Logic section provides a table listing resources allocated by the fitter 
+ to mapped logic. The page will appear in your browser sorted by Signal 
+ Name, but you can choose to sort it by Signal Name, Function Block, and 
+ Pin Number by clicking on the appropriate table headers. </FONT></span>
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp; 
+ 
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The Mapped Logic 
+ table contains the following: </FONT></span>
+
+<ul type="disc" class="whs1">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ output signal name </FONT></span></li>
+</ul>
+
+<p class="whs2"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Clicking on 
+ the signal name will open a new window with the equations for that signal. 
+ </FONT></span></p>
+
+<ul type="disc" class="whs3">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ total number of product terms </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of signals used </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ function block number </FONT></span></li>
+</ul>
+
+<p class="whs4"><span style="font-weight: bold;"><B>Note:</B></span> 
+ Clicking on the function block will provide a detailed table of all the 
+ block's resources and a graphical display of the function block diagram 
+ (see <a href="fbs_FBdoc.htm">Function Block Specifics</a> for more details). 
+ </p>
+
+<ul type="disc" class="whs5">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ macrocell number</FONT></span></li>
+</ul>
+
+<p class="whs6"><span style="font-weight: bold;"><B>Note:</B></span> 
+ Clicking on the underscored macrocell number will provide a graphical 
+ display of the macrocell that looks like this:</p>
+
+<p class="whs7"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
+else
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
+//--></SCRIPT>.</p>
+
+<ul type="disc" class="whs8">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ slew rate</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pin number</FONT></span></li>
+</ul>
+
+<p class="whs9"><span style="font-weight: bold;"><B>Note:</B></span> 
+ Clicking on the underscored pin number will provide the pin layout diagram 
+ for the highlighted pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling 
+ your mouse over the colored pin will pop up a tooltip with the signal 
+ name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the 
+ I/O style, the slew rate, and/or any constraints assigned to the pin:</p>
+
+<p class="whs10"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
+else
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
+//--></SCRIPT></p>
+
+<ul type="disc" class="whs11">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pin type</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pin use</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ input register use</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ I/O standard</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ I/O style</FONT></span></li>
+</ul>
+
+</body>
+
+</html>
diff --git a/address_decoder_html/fit/newappletref.htm b/address_decoder_html/fit/newappletref.htm
new file mode 100644
index 0000000..186e949
--- /dev/null
+++ b/address_decoder_html/fit/newappletref.htm
@@ -0,0 +1,15 @@
+<html>
+  <head>
+    <title></title>
+  </head>
+  <frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" cols="*">
+    <frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
+    <frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
+      <frame name="leftnav" noresize src="leftnav.htm" marginwidth="0" marginheight="0">
+      <frame name="content" src="summary.htm">
+    </frameset>
+    <frame name="applets" src="newapplet.htm" scrolling="no"> 
+    <frame name="eqns" src="eqns.htm" scrolling="no">
+  </frameset>
+</html>
+
diff --git a/address_decoder_html/fit/next.jpg b/address_decoder_html/fit/next.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..b8bbb999ee5f7042c9dcbad4dacf3659aa2ee7a8
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diff --git a/address_decoder_html/fit/ns4plugin.js b/address_decoder_html/fit/ns4plugin.js
new file mode 100644
index 0000000..0292ee1
--- /dev/null
+++ b/address_decoder_html/fit/ns4plugin.js
@@ -0,0 +1,55 @@
+
+function checkJre(){
+
+var agt=navigator.userAgent.toLowerCase();
+var is_major = parseInt(navigator.appVersion);
+
+
+var is_nav = ((agt.indexOf('mozilla')!=-1) && (agt.indexOf('spoofer')== -1)
+&& (agt.indexOf('compatible') == -1) && (agt.indexOf('opera')== -1)
+&& (agt.indexOf('webtv')==-1) && (agt.indexOf('hotjava')== -1));
+var is_nav4up = (is_nav && (is_major >= 4)); 
+
+var pluginDetected = false;
+
+// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up'
+if(is_nav4up) {
+
+  // Refresh 'navigator.plugins' to get newly installed plugins.
+  // Use 'navigator.plugins.refresh(false)' to refresh plugins 
+  // without refreshing open documents (browser windows)
+  if(navigator.plugins) { 
+    navigator.plugins.refresh(false);
+  }
+
+  // check for Java plugin in installed plugins
+  if(navigator.mimeTypes) {
+    // window.alert( navigator.mimeTypes.length); 
+    for (i=0; i <  navigator.mimeTypes.length; i++) {
+      // window.alert( navigator.mimeTypes[i].type); 
+      if( (navigator.mimeTypes[ i].type != null)
+        &&(navigator.mimeTypes[ i].type.indexOf(
+        "application/x-java-applet;jpi-version=1.4") != -1) ) {
+        //window.alert("Found"); 
+        pluginDetected = true; 
+       break;
+      }
+
+    }
+  }
+
+} 
+
+if (pluginDetected) {
+  // show applet page
+  document.location.href="appletref.htm";
+
+} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" + 
+                   "if you choose not to install the plugin  the reports graphical applets will not be available.")) {
+  document.location.href=XilinxD;
+} else {
+  document.location.href="appletref.htm";
+}
+
+}
+
diff --git a/address_decoder_html/fit/optionsdoc.htm b/address_decoder_html/fit/optionsdoc.htm
new file mode 100644
index 0000000..f1ee543
--- /dev/null
+++ b/address_decoder_html/fit/optionsdoc.htm
@@ -0,0 +1,760 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Compiler Options</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=3977>
+<meta name=layout-width content=615>
+<meta name=date content="05 24, 2002 5:09:37 PM">
+
+
+
+<style>
+<!--
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+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Compiler Options</h1>
+
+<p class="whs1">The Compiler 
+ Options page provides all the fitter options settings for the device family 
+ the fitter has selected.</p>
+
+<h1 class="whs2">Fitter Options</h1>
+
+<p class="whs3"><a href="#Basic Tab"
+								style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Basic Tab</a></FONT></span></p>
+
+<p class="whs4"><a href="#XPLA Advanced Options"
+								style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">XPLA3 Advanced 
+ Options</a></FONT></span></p>
+
+<p class="whs5"><a href="#CoolRunner-II Advanced Options"
+								style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">CoolRunner-II 
+ Advanced Options</a></FONT></span></p>
+
+<p class="whs6"><a href="#XC9500/XL/XV Advanced Options"
+								style="font-family: arial, sans-serif; font-size: 10pt;">XC9500/XL/XV 
+ Advanced Options</a></p>
+
+<h2 class="whs7"><a name="Basic Tab"></a>Basic 
+ Tab</h2>
+
+<p class=whs1
+	style="font-family: arial, sans-serif; font-size: 10pt;">The CPLD devices 
+ have the following fitter <span style="font-weight: bold;"><B><b>Implementation 
+ Options </B></span><span style="font-weight: bold;"><B>available</B></span></b> in 
+ the <span style="font-weight: bold;"><B>Basic</B></span> tab:</p>
+
+<ul>
+	
+	<li class=kadov-h4><h4 class="whs8">Use 
+ Multi-Level Logic Optimization</h4></li>
+</ul>
+
+<p class="whs9">This option simplifies the total number 
+ of logic expressions in a design, and then collapses the logic in order 
+ to meet user objectives such as density, speed and timing constraints. 
+ This optimization targets CPLD architecture, making it possible to collapse 
+ to the macrocell limits, reduce levels of logic, and minimize the total 
+ number of p-terms.</p>
+
+<p class="whs10">Multi-level Logic Optimization optimizes 
+ all combinatorial logic arcs spanning from an input pad or register output 
+ to an output pad or register input.</p>
+
+<p class="whs11">Multi-level Logic Optimization operates 
+ on combinatorial logic according to the following rules.</p>
+
+<p class="whs12">If timing constraints are set, the program 
+ optimizes for speed to meet timing constraints.</p>
+
+<p class="whs13">If timing constraints are not set, the 
+ program optimizes either for speed or density, depending on the user setting 
+ for the <span style="font-weight: bold;"><B>Use Timing Optimization</B></span> 
+ option.</p>
+
+<ul>
+	
+	<ul class=whs1
+		style="list-style: disc;"
+		type=disc>
+		
+		<ul class=whs2
+			style="list-style: circle;"
+			type=circle>
+			
+			<li class=kadov-p><p class="whs14">If 
+ <span style="font-weight: bold;"><B>Use Timing Optimization</B></span> is turned 
+ on, the combinatorial logic will be mapped for speed.</p></li>
+			
+			<li class=kadov-p-Cwhs3><p class=whs3
+										style="font-family: arial; font-size: 10pt;">If 
+ <span style="font-weight: bold;"><B>Use Timing Optimization</B></span> is turned 
+ off, the combinatorial logic will be mapped for density. The goal of optimization 
+ will then be to reduce the total number of p-terms.</p></li>
+		</ul>
+	</ul>
+</ul>
+
+<p class="whs15"><font style="font-family: arial; font-size: 10pt;"
+									face=arial
+									size=2><span style="font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Logic 
+ marked with the </FONT></span><span style="font-weight: bold;"><B><b style="font-size: 10pt;">NOREDUCE</b></B></span><span 
+ style="font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> property will not be extracted or optimized.</FONT></span></font></p>
+
+<p class=whs3
+	style="font-family: arial, sans-serif;
+			font-size: 10pt;
+			font-weight: bold;
+			margin-left: 40px;"><span style="font-family: arial; font-weight: normal;">By 
+ default, this option is on.</span> </p>
+
+<ul>
+	
+	<li class=kadov-p-Cwhs3><p class=whs3
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b style="font-weight: bold;"><span 
+ style="font-weight: bold;"><B>Use Timing Constraints -- </B></span><span style="font-weight: normal;">This 
+ option instructs the fitter use Timing Constraints when fitting the design. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->If this 
+ box is not checked, the fitter will ignore timing constraints, if necessary.</span></b></p></li>
+	
+	<li class=kadov-p-Cwhs3><p class=whs3
+								style="font-family: arial, sans-serif; font-size: 10pt;"><b 
+ style="font-weight: bold;"><span style="font-weight: bold;"><B>Enable WYSIWYG 
+ Mode -- (CoolRunner only) </B></span><span style="font-weight: normal;">T</span></b>he 
+ goal of the WYSIWYG options is to have a netlist reflect the user's specifications, 
+ as much as possible. All the nodes declared in the HDL design are preserved. 
+ By default, this property is set to Off (Checkbox is not checked) When 
+ this property is On (checkbox is checked), XST:</p></li>
+	
+	<ul>
+		
+		<li style="list-style: circle;"
+			type=circle
+			class=kadov-p-Cwhs3><p class=whs3
+									style="font-family: arial, sans-serif; font-size: 10pt;">Preserves 
+ all the user internal signals (nodes)</p></li>
+		
+		<li style="list-style: circle;"
+			type=circle
+			class=kadov-p-Cwhs3><p class=whs3
+									style="font-family: arial, sans-serif; font-size: 10pt;">Creates 
+ source_node constraints in NGC file for all these nodes.</p></li>
+		
+		<li style="list-style: circle;"
+			type=circle
+			class=kadov-p-Cwhs3><p class=whs3
+									style="font-family: arial, sans-serif; font-size: 10pt;">Skips 
+ the design optimization (collapse, factorization). Only the Boolean equation 
+ minimization is performed.</p></li>
+	</ul>
+	
+	<li class=kadov-p-Cwhs3><p class=whs3
+								style="font-family: arial, sans-serif; font-size: 10pt;"><b><span 
+ style="font-weight: bold;"><B>Optimization Style</B></span></b>-- The Optimization 
+ Method allows you to select from one of two basic optimization strategies: 
+ <span style="font-weight: bold;"><B><b>Density</b></B></span> or <span style="font-weight: bold;"><B><b>Speed</b></B></span>. 
+ <span style="font-weight: bold;"><B><b>Density</b></B></span> focuses on solely 
+ on density, and <span style="font-weight: bold;"><B><b>Speed</b></B></span> focuses 
+ solely on speed.</p></li>
+	
+	<li class=kadov-p><p class="whs16"><span 
+ style="font-weight: bold;"><B>Location Constraints</B></span> -- The Try selection 
+ will attempt to fit the design with the pin assignments specified in the 
+ design source. If the design cannot be fit with these pin assignments, 
+ the fitter will remove the location constraints and attempt to fit the 
+ design with no location constraints. A warning message will tell the user 
+ if the location constraints have been removed.</p></li>
+	
+	<ul class=whs5
+		style="list-style: circle;"
+		type=circle>
+		
+		<li class=kadov-p><p class="whs17">The 
+ <span style="font-weight: bold;"><B><b>Try</b></B></span> selection will attempt 
+ to fit the design with the pin assignments specified in the design source. 
+ If the design cannot be fit with these pin assignments, the fitter will 
+ ignore the pin assignments.</p></li>
+	</ul>
+	
+	<li style="list-style: circle;"
+		type=circle
+		class=kadov-p-Cwhs6><p class=whs6
+								style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ <span style="font-weight: bold;"><B>On </B></span>selection will attempt to fit 
+ the design with the pin assignments specified in the design source. If 
+ the design cannot be fit with these pin assignments, the fitter will notify 
+ the user that the device could not fit. It will not unlock the pins under 
+ this option.</p></li>
+	
+	<li style="list-style: circle;"
+		type=circle
+		class=kadov-p-Cwhs7><p class=whs7
+								style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ <span style="font-weight: bold;"><B>Off</B></span> selection will attempt to 
+ fit the design and will ignore the pin assignments specified in the design 
+ source. If the design can be fit with no pre-assigned pins, the fitter 
+ will assign pins, which can be viewed in the fitter report (filename.fit). 
+ The user should take these pin assignments and incorporate them back into 
+ the design source file. The user will be notified whether the fitting 
+ operation was successful.</p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b><span style="font-weight: bold;"><B>Output 
+ Slew Rate -- </B></span></b><span style="font-weight: normal;">Use this option 
+ to control the default output slew rate. You can control the transition 
+ time of device output pins by setting the slew rate to Slow or Fast. Limiting 
+ the slew rate (Slow) reduces output switching surges in the device. The 
+ default is Fast.</span></p></li>
+</ul>
+
+<p class="whs18"><span style="font-weight: bold;"><B>Note</B></span>: 
+ Any explicit slew rate control properties in the design or constraints 
+ file take precedence over this Output Slew Rate setting. </p>
+
+<ul>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b style="font-weight: bold;"><span 
+ style="font-weight: bold;"><B>FF Initial State -- </B></span><span style="font-weight: normal;">Sets 
+ the initial state for all Flip-Flops. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ options are Low, High and FPGA.</span></b></p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b><span style="font-weight: bold;"><B>Collapsing 
+ P-Term Limit -- </B></span></b><span style="font-weight: normal;">This option 
+ controls the degree to which the fitter flattens a design netlist. A logic 
+ gate can collapse forward into a subsequent gate only if the number of 
+ product terms in the resulting logic function does not exceed the p-term 
+ limit. If the path delay of a logic function is not acceptable, increase 
+ the p-term limit to allow the larger functions to be further flattened. 
+ Choose a number from 3 to 48.</span> </p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b><span style="font-weight: bold;"><B>Collapsing 
+ Input Limit -- </B></span></b><span style="font-weight: normal;">This is a 
+ secondary option for controlling the degree to which the fitter flattens 
+ a design netlist. A logic gate can collapse forward into a subsequent 
+ gate only if the number of inputs in the resulting logic function does 
+ not exceed the input limit. If the design fails to fit the target device 
+ because flattening uses up too many of the function block inputs, decrease 
+ the input limit to prevent flattening of certain high fan-in functions. 
+ </span><!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p></li>
+</ul>
+
+<h2 class="whs19"><b><span 
+ style="font-weight: bold;"><B><a name="XPLA Advanced Options"></a>XPLA Advanced 
+ Options</B></span></b></h2>
+
+<p class="whs20"><b><span style="font-weight: normal;">The 
+ following options are available under XPLA </span><span style="font-weight: bold;"><B>Implementation 
+ Options</B></span><span style="font-weight: normal;">, </span><span style="font-weight: bold;"><B>Advanced</B></span><span 
+ style="font-weight: normal;"> tab.</span></b></p>
+
+<ul>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;">Enable Fast 
+ Input Registers -<span style="font-weight: normal;">- Enables the use 
+ of the Fast Input path in XPLA3 devices.</span></p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;">Enable Use 
+ of Foldback NANDs -- <span style="font-weight: normal;">When selected, 
+ the software will use foldback NANDs. This increases the capability to 
+ fit a design, sometimes at the expense of speed.</span></p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-weight: bold;"><B>Reserve JTAG Pins for ISP -- </B></span>Checking 
+ this box will instruct the fitter to reserve JTAG pins.</p></li>
+</ul>
+
+<h2 class="whs21"><a name="CoolRunner-II Advanced Options"></a>CoolRunner-II 
+ Advanced Options</h2>
+
+<p class="whs22">The following 
+ options are found under the Advanced tab for CoolRunner-II devices.</p>
+
+<ul type="disc" class="whs23">
+	
+	<li class=kadov-h4><h4 class="whs24">Use 
+ Global Clock(s) -- <span style="font-weight: normal;">Select this option 
+ to allow the fitter to assign input pins used as clocks to dedicated global 
+ clock (GCK) pins of the device. If this option is disabled, only pins 
+ identified with the BUFG=CLK property in the design (or UCF file) will 
+ be assigned to GCK device pins. By default, this option is on.</span> 
+ </h4></li>
+	
+	<li class=kadov-p><p class="whs25"><span 
+ style="font-weight: bold;"><B>Use Global Output Enable(s)</B></span> -- Select 
+ this option to allow the fitter to assign input pins used as output enable 
+ control to dedicated global OE (GTS) pins of the device. If this option 
+ is disabled, only pins identified with the BUFG=OE property in the design 
+ (or UCF file) will be assigned to GTS device pins. By default, this option 
+ is on. </p></li>
+	
+	<li class=kadov-p><p class="whs26"><span 
+ style="font-weight: bold;"><B>Use Global Set/Reset</B></span> -- Select this 
+ option to allow the fitter to assign input pins used as register asynchronous 
+ reset or preset control to the dedicated global set/reset (GSR) pin of 
+ the device. If this option is disabled, only a pin identified with the 
+ BUFG=SR property in the design (or UCF file) will be assigned to the GSR 
+ device pin. By default, this option is on.</p></li>
+	
+	<li class=kadov-p><p class="whs27"><span 
+ style="font-weight: bold;"><B>Enable Fast Input Registers</B></span> -- Enables 
+ fast input registers.</p></li>
+	
+	<li class=kadov-p><p class="whs28"><span 
+ style="font-weight: bold;"><B>Ignore DATA_GATE Attributes</B></span> -- Data 
+ Gate is a power saving property that can be used in CoolRunner-II designs. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->This option 
+ allows you to turn Data Gate off in case you want the fitter to ignore 
+ data gate.</p></li>
+	
+	<li class=kadov-p><p class="whs29"><span 
+ style="font-weight: bold;"><B>Tristate Outputs Termination Node</B></span> -- 
+ The Tristate Output Termination Mode globally sets all tristate outputs 
+ to the specified termination mode. By default, this field is set to Pullup.. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The options 
+ are Pullup, Keeper and Float.</p></li>
+	
+	<li class=kadov-p><p class="whs30"><span 
+ style="font-weight: bold;"><B>Create Programmable Ground Pins on Unused I/O</B></span> 
+ -- The Create Programmable GND Pins on Unused I/O property controls the 
+ option to indicate that you want all unused I/O pads to be configured 
+ as ground pins. This can reduce ground bounce. By default, this option 
+ is set to ground. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ options are Ground, Pullup, Keeper and Float.</p></li>
+	
+	<li class=kadov-p>
+	<p class="whs31"><span style="font-weight: bold;"><B>Default 
+ Output Voltage Standard</B></span> -- set a default voltage standard for CoolRunner-II 
+ device pins.</p>
+	
+	<p class="whs32">IOSTANDARD 
+ names supported by CoolRunner-II are:</p>
+	
+	<!--(Table)=====================================================-->
+	<table x-use-null-cells width="84.797%" cellspacing="0" class="whs33">
+	<col class="whs34">
+	<col class="whs35">
+	<col class="whs36">
+	<col class="whs37">
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs38">
+	<p class="whs39">I/O Standard</td>
+	<td width="16.192%" class="whs40">
+	<p align="center" class="whs41">VCC<span style="vertical-align: Sub;">IO</span></td>
+	<td width="22.217%" class="whs42">
+	<p align="center" class="whs43">Input V<span style="vertical-align: Sub;">REF</span></td>
+	<td width="41.383%" class="whs44">
+	<p align="center" class="whs45">Board Termination Voltage (V<span style="vertical-align: Sub;">TT</span>)</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs46">
+	<p class="whs47">LVTTL </td>
+	<td width="16.192%" class="whs48">
+	<p align="center" class="whs49">3.3V</td>
+	<td width="22.217%" class="whs50">
+	<p align="center" class="whs51">N/A</td>
+	<td width="41.383%" class="whs52">
+	<p align="center" class="whs53">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs54">
+	<p class="whs55">LVCMOS33</td>
+	<td width="16.192%" class="whs56">
+	<p align="center" class="whs57">3.3V</td>
+	<td width="22.217%" class="whs58">
+	<p align="center" class="whs59">N/A</td>
+	<td width="41.383%" class="whs60">
+	<p align="center" class="whs61">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs62">
+	<p class="whs63">LVCMOS25</td>
+	<td width="16.192%" class="whs64">
+	<p align="center" class="whs65">2.5V</td>
+	<td width="22.217%" class="whs66">
+	<p align="center" class="whs67">N/A</td>
+	<td width="41.383%" class="whs68">
+	<p align="center" class="whs69">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs70">
+	<p class="whs71">LVCMOS18</td>
+	<td width="16.192%" class="whs72">
+	<p align="center" class="whs73">1.8V</td>
+	<td width="22.217%" class="whs74">
+	<p align="center" class="whs75">N/A</td>
+	<td width="41.383%" class="whs76">
+	<p align="center" class="whs77">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs78">
+	<p class="whs79">LVCMOS15</td>
+	<td width="16.192%" class="whs80">
+	<p align="center" class="whs81">1.5V</td>
+	<td width="22.217%" class="whs82">
+	<p align="center" class="whs83">N/A</td>
+	<td width="41.383%" class="whs84">
+	<p align="center" class="whs85">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs86">
+	<p class="whs87">HSTL_I</td>
+	<td width="16.192%" class="whs88">
+	<p align="center" class="whs89">1.5V</td>
+	<td width="22.217%" class="whs90">
+	<p align="center" class="whs91">0.75V</td>
+	<td width="41.383%" class="whs92">
+	<p align="center" class="whs93">0.75V</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs94">
+	<p class="whs95">SSTL2_I</td>
+	<td width="16.192%" class="whs96">
+	<p align="center" class="whs97">2.5V</td>
+	<td width="22.217%" class="whs98">
+	<p align="center" class="whs99">1.25V</td>
+	<td width="41.383%" class="whs100">
+	<p align="center" class="whs101">1.25V</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs102">
+	<p class="whs103">SSTL3_I</td>
+	<td width="16.192%" class="whs104">
+	<p align="center" class="whs105">3.3V</td>
+	<td width="22.217%" class="whs106">
+	<p align="center" class="whs107">1.5V</td>
+	<td width="41.383%" class="whs108">
+	<p align="center" class="whs109">1.5V</td></tr>
+	</table>
+	
+	<p class="whs110">The software 
+ automatically groups outputs with similar IOSTANDARD settings into the 
+ same bank when no location constraints are specified. </p>
+	</li>
+</ul>
+
+<h2 class="whs111"><a name="XC9500/XL/XV Advanced Options"></a>XC9500/XL/XV 
+ Advanced Options</h2>
+
+<p class="whs112">The following 
+ options are found under the Advanced tab for XC9500/XL/XV. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Note 
+ that additional options for XC9500 only are also described below.</p>
+
+<ul type="disc" class="whs113">
+	
+	<li class=kadov-h4><h4 class="whs114">Use 
+ Global Clock(s) -- <span style="font-weight: normal;">Select this option 
+ to allow the fitter to assign input pins used as clocks to dedicated global 
+ clock (GCK) pins of the device. If this option is disabled, only pins 
+ identified with the BUFG=CLK property in the design (or UCF file) will 
+ be assigned to GCK device pins. By default, this option is on.</span> 
+ </h4></li>
+	
+	<li class=kadov-p><p class="whs115"><span 
+ style="font-weight: bold;"><B>Use Global Output Enable(s)</B></span> -- Select 
+ this option to allow the fitter to assign input pins used as output enable 
+ control to dedicated global OE (GTS) pins of the device. If this option 
+ is disabled, only pins identified with the BUFG=OE property in the design 
+ (or UCF file) will be assigned to GTS device pins. By default, this option 
+ is on. </p></li>
+	
+	<li class=kadov-p><p class="whs116"><span 
+ style="font-weight: bold;"><B>Use Global Set/Reset</B></span> -- Select this 
+ option to allow the fitter to assign input pins used as register asynchronous 
+ reset or preset control to the dedicated global set/reset (GSR) pin of 
+ the device. If this option is disabled, only a pin identified with the 
+ BUFG=SR property in the design (or UCF file) will be assigned to the GSR 
+ device pin. By default, this option is on.</p></li>
+	
+	<li class=kadov-p><p class="whs117"><span 
+ style="font-weight: bold;"><B>Create Programmable Ground Pins on Unused I/O</B></span> 
+ -- Select this option to indicate that you want all unused I/O pads to 
+ be configured as ground pins. This can reduce ground bounce. By default, 
+ this option is off.</p></li>
+	
+	<li class=kadov-p><p class="whs118"><span 
+ style="font-weight: bold;"><B>Macrocell Power Setting</B></span> -- Use this 
+ option to control device power consumption. Select Low or Standard to 
+ set the default power mode for the macrocells used to implement the design. 
+ Select Timing Driven to automatically reduce power on paths covered by 
+ timing specifications that can meet speed requirements while operating 
+ in low power. The default is Standard, which results in highest speed.</p></li>
+</ul>
+
+<p class="whs119">Note: Any explicit power control (PWR_MODE) 
+ properties in the design or constraints file take precedence over this 
+ Macrocell Power Setting. </p>
+
+<ul type="disc" class="whs120">
+	
+	<li class=kadov-p><p class="whs121"><span 
+ style="font-weight: bold;"><B>Enable FASTConnect/UIM Optimization (XC9500 
+ only)</B></span> -- Enables optimization of the FASTConnect/UIM for XC9500 
+ devices.</p></li>
+	
+	<li class=kadov-h4><h4 class="whs122">Use 
+ Local Feedback (XC9500 only)</h4></li>
+</ul>
+
+<p class="whs123">Select this option to enable the software 
+ to use local macrocell feedback whenever possible. The local feedback 
+ path, running from each macrocell output to an input of the same function 
+ block, has shorter propagation delay than the global feedback path. The 
+ fitter always tries to use local macrocell feedback (if possible) to satisfy 
+ timing constraints. This option allows the fitter to use local feedback 
+ to generally improve timing on remaining paths. Using local feedback can 
+ speed up your design but could also make it difficult to maintain the 
+ same timing after a design change. By default, this option is on.</p>
+
+
+<!--(HR)============================================================-->
+<hr class=whs4
+	style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
+	align=center>
+
+
+<p class="whs124"><b><span style="font-weight: bold;"><B>Note: 
+ </B></span></b>To force the fitter to use local feedback, manually map both 
+ the source and load functions into the same function block using the property 
+ <span style="font-weight: bold;"><B><b>LOC=FB</b></B></span><span style="font-style: italic;"><I><i>nn</i></I></span>, 
+ then apply a timespec across the path.&nbsp;</p>
+
+
+<!--(HR)============================================================-->
+<hr class=whs5
+	style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
+	align=center>
+
+
+<p class="whs125"><span><FONT SIZE=2 style="font-size:10pt;"><b style="font-weight: bold;">Note: 
+ </b></FONT></span>The XC9536 device does not have local feedback.</p>
+
+
+<!--(HR)============================================================-->
+<hr class=whs6
+	style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
+	align=center>
+
+
+<ul type="disc" class="whs126">
+	
+	<li class=kadov-h4><h4 class="whs127">Use 
+ Pin Feedback (XC9500 only)</h4></li>
+</ul>
+
+<p class="whs128">Select this option to enable the software 
+ to use I/O pin feedback whenever possible. The pin feedback path has slightly 
+ shorter propagation delay than the global feedback path. If this option 
+ is enabled, the software uses the pin feedback path instead of the global 
+ feedback path for macrocell signals that do not drive 3-state outputs 
+ or slew-rate-limited outputs, and where the associated I/O pin is not 
+ used as input-only. By default, this option is on.</p>
+
+</body>
+
+</html>
diff --git a/address_decoder_html/fit/paths.js b/address_decoder_html/fit/paths.js
new file mode 100644
index 0000000..22107b3
--- /dev/null
+++ b/address_decoder_html/fit/paths.js
@@ -0,0 +1,37 @@
+rootURL = "http://www.xilinx.com/";
+prodURL = "xlnx/xil_prodcat_product.jsp?title=";
+cpldURL = "CPLD+Products";
+xbrURL = "coolrunner2_page";
+xpla3URL = "xpla3_page";
+xc9500URL = "xc9500_page";
+xc9500xlURL = "xc9500xl_page";
+xc9500xvURL = "xc9500xv_page";
+marketURL= "esp";
+supportURL = "http://www.support.xilinx.com/";
+educationURL = "support/education-home.htm";
+buyURL = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront";
+contactURL = "company/contact.htm";
+searchURL = "company/search.htm";
+
+docURL = rootURL + "xlnx/xweb/xil_publications_display.jsp?" +
+         "iLanguageID=1" +
+         "&category=/Data+Sheets/CPLD+Device+Families/";
+doc95URL = docURL + "XC9500";
+doc95xlURL = docURL + "XC9500XL";
+doc95xvURL = docURL + "XC9500XV";
+docXpla3URL = docURL + "CoolRunner+XPLA3";
+docXbrURL = docURL + "CoolRunner-II";
+docCr2sURL = docURL + "CoolRunner-IIS";
+
+var messages = new Array();
+messages["fastinreg"] = "Direct Input Register";
+messages["inreg"] = "Direct Input Register";
+messages["fbnand"] = "Foldback NAND";
+messages["fcnode"] = "FC node";
+messages["LATCH"] = "Transparent latch";
+messages["DFF"] = "D-flip-flop";
+messages["DEFF"] = "D-flip-flop with clock enable";
+messages["TFF"] = "T-flip-flop";
+messages["TDFF"] = "Dual-edge-triggered T-flip-flop";
+messages["DDFF"] = "Dual-edge-triggered flip-flop";
+messages["DDEFF"] = "Dual-edge-triggered flip-flop with clock enable";
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diff --git a/address_decoder_html/fit/pin_legXC95.htm b/address_decoder_html/fit/pin_legXC95.htm
new file mode 100644
index 0000000..db88bcb
--- /dev/null
+++ b/address_decoder_html/fit/pin_legXC95.htm
@@ -0,0 +1,13 @@
+<html><body><pre>
+Legend :  NC  = Not Connected, unbonded pin
+         PGND = Unused I/O configured as additional Ground pin
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+         PE   = Port Enable pin
+  PROHIBITED  = User reserved pin
+</pre></body></html>
diff --git a/address_decoder_html/fit/pin_legXbr.htm b/address_decoder_html/fit/pin_legXbr.htm
new file mode 100644
index 0000000..c70585b
--- /dev/null
+++ b/address_decoder_html/fit/pin_legXbr.htm
@@ -0,0 +1,20 @@
+<html><body><pre>
+Legend :  NC  = Not Connected, unbonded pin
+        PGND  = Unused I/O configured as additional Ground pin
+         KPR  = Unused I/O with weak keeper (leave unconnected)
+         WPU  = Unused I/O with weak pull up (leave unconnected)
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+      VCCAUX  = Power supply for JTAG pins
+   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
+   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
+   VCCIO-1.8  = I/O supply voltage for LVCMOS18
+   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
+        VREF  = Reference voltage for indicated input standard
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+</pre></body></html>
diff --git a/address_decoder_html/fit/pin_legXpla3.htm b/address_decoder_html/fit/pin_legXpla3.htm
new file mode 100644
index 0000000..8dad55d
--- /dev/null
+++ b/address_decoder_html/fit/pin_legXpla3.htm
@@ -0,0 +1,13 @@
+<html><body><pre>
+Legend :  NC  = Not Connected, unbonded pin
+          PE  = Port Enable pin
+         WPU  = Unused with Internal Weak Pull Up
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+</pre></body></html>
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diff --git a/address_decoder_html/fit/pins.js b/address_decoder_html/fit/pins.js
new file mode 100644
index 0000000..591e563
--- /dev/null
+++ b/address_decoder_html/fit/pins.js
@@ -0,0 +1,62 @@
+var specSig = new Array();
+var pins = new Array();
+var pinsAssign = new Array();
+var prohibit = new Array();
+var unusedStr = "WPU";
+var gndStr = "GND";
+var vccStr = "VCC";
+var tdiStr = "TDI";
+var tdoStr = "TDO";
+var tmsStr = "TMS";
+var tckStr = "TCK";
+
+function showPin(pin) { parent.leftnav.showAppletPin(pin); }
+
+function printPage() { window.print();  parent.leftnav.printAppletPkg(); }
+
+function showEqn(signal) { parent.leftnav.showEqn(signal); }
+
+function updatePin(type) {
+  with (document.options) {
+    switch (type) {
+    case 0:
+      if (inp.checked) parent.leftnav.document.options.inOn.value = 1;
+      else             parent.leftnav.document.options.inOn.value = 0;
+      break;
+
+    case 1:
+      if (out.checked) parent.leftnav.document.options.outOn.value = 1;
+      else             parent.leftnav.document.options.outOn.value = 0;
+      break;
+
+    case 2:
+      if (glb.checked) parent.leftnav.document.options.glbOn.value = 1;
+      else             parent.leftnav.document.options.glbOn.value = 0;
+      break;
+
+    case 3:
+      if (isp.checked) parent.leftnav.document.options.ispOn.value = 1;
+      else             parent.leftnav.document.options.ispOn.value = 0;
+      break;
+
+    case 4:
+      if (vcc.checked) parent.leftnav.document.options.vccOn.value = 1;
+      else             parent.leftnav.document.options.vccOn.value = 0;
+      break;
+
+    case 5:
+      if (gnd.checked) parent.leftnav.document.options.gndOn.value = 1;
+      else             parent.leftnav.document.options.gndOn.value = 0;
+      break;
+
+    case 6:
+      if (unuse.checked) parent.leftnav.document.options.unuseOn.value = 1;
+      else               parent.leftnav.document.options.unuseOn.value = 0;
+      break;
+    }
+  }
+
+  parent.leftnav.showPinOut();
+}
+
+function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); }
diff --git a/address_decoder_html/fit/pinsdoc.htm b/address_decoder_html/fit/pinsdoc.htm
new file mode 100644
index 0000000..9da2708
--- /dev/null
+++ b/address_decoder_html/fit/pinsdoc.htm
@@ -0,0 +1,265 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Pin List</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=1449>
+<meta name=layout-width content=615>
+<meta name=date content="05 24, 2002 6:19:23 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs2 {font-family: arial, sans-serif; font-size: 10pt; margin-left: 80px;}
+p.whs3 {font-weight: bold; font-family: arial, sans-serif; font-size: 10pt; margin-left: 0px;}
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+p.whs12 {font-family: arial, sans-serif; font-weight: bold; font-size: 11pt;}
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+td.whs15 {padding-right: 10px; padding-left: 10px; border-left-style: Solid; border-left-color: #000000; border-left-width: 1px; border-right-style: Solid; border-right-color: #000000; border-right-width: 1px; border-bottom-width: 1px; border-bottom-color: #000000; border-bottom-style: Solid;}
+p.whs16 {font-family: arial, sans-serif; font-size: 10pt;}
+td.whs17 {padding-right: 10px; padding-left: 10px; border-right-style: Solid; border-right-color: #000000; border-right-width: 1px; border-bottom-width: 1px; border-bottom-color: #000000; border-bottom-style: Solid;}
+p.whs18 {font-family: arial, sans-serif; font-size: 10pt;}
+td.whs19 {border-left-width: 1px; border-left-color: #000000; border-left-style: Solid; border-right-width: 1px; border-right-color: #000000; border-right-style: Solid; border-bottom-style: Solid; border-bottom-color: #000000; border-bottom-width: 1px; padding-right: 10px; padding-left: 10px;}
+p.whs20 {font-family: arial, sans-serif; font-size: 10pt;}
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+p.whs50 {font-family: arial, sans-serif; font-size: 10pt;}
+td.whs51 {border-left-width: 1px; border-left-color: #000000; border-left-style: Solid; border-right-width: 1px; border-right-color: #000000; border-right-style: Solid; border-bottom-style: Solid; border-bottom-color: #000000; border-bottom-width: 1px; padding-right: 10px; padding-left: 10px;}
+p.whs52 {font-family: arial, sans-serif; font-size: 10pt;}
+td.whs53 {border-right-width: 1px; border-right-color: #000000; border-right-style: Solid; border-bottom-style: Solid; border-bottom-color: #000000; border-bottom-width: 1px; padding-right: 10px; padding-left: 10px;}
+p.whs54 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs55 {font-family: arial, sans-serif; font-size: 10pt; margin-left: 0px; font-weight: normal;}
+
+--></style><script>
+<!--
+if (navigator.appName == "Netscape")
+{
+  var strNSS = "<style>";
+  strNSS += "p.whs3 {margin-left:1; }";
+  strNSS += "p.whs4 {margin-left:1; }";
+  strNSS += "p.whs5 {margin-left:1; }";
+  strNSS += "p.whs6 {margin-left:1; }";
+  strNSS += "p.whs7 {margin-left:1; }";
+  strNSS += "p.whs55 {margin-left:1; }";
+  strNSS +="</style>";
+  document.write(strNSS);
+}
+//-->
+</script><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Pin List</h1>
+
+<p class="whs1">The Pin List 
+ page lists each pin of your design with its pin type and associated signal. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Check boxes 
+ at the top of the table allow you to select and deselect which pin types 
+ you want displayed in the table (the default view will display all of 
+ them).</p>
+
+<p class="whs2"><span style="font-weight: bold;"><B>Note:</B></span> 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->There is 
+ a <SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' width='68' height='28' border='0'>");}
+else
+{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' style='border: none; width: 68px; height: 28px; float: none;' width='68' height='28' border='0'>");}
+//--></SCRIPT> button below the table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Click 
+ this button to open a new window describing all of the acronyms used in 
+ the function block table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can select either brief descriptions or more detailed descriptions by 
+ clicking the &quot;Verbose&quot; button at the top of the window. </p>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Clicking 
+ on the underscored pin numbers in the first column of the table will open 
+ a new window displaying the pin layout diagram for the selected pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling 
+ your mouse over the colored pin will pop up a tooltip with the signal 
+ name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the 
+ I/O style, the slew rate, and/or any constraints assigned to the pin: 
+ </FONT></span>
+
+<p class="whs3"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
+else
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs4">Clicking any underscored signal in the 
+ third column of the table will open a new window displaying the equations 
+ for that particular signal.</p>
+
+<p class="whs5">Clicking on the <SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' width='61' height='53' border='0'>");}
+else
+{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' style='border: none; width: 61px; height: 53px; float: none;' width='61' height='53' border='0'>");}
+//--></SCRIPT>button 
+ at the top of the screen will open a new window with a graphical, top 
+ view of all of the pins: <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
+
+<p class="whs6"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pindiagram.gif' x-maintain-ratio='TRUE' width='312' height='318' border='0'>");}
+else
+{ document.write("<img src='pindiagram.gif' x-maintain-ratio='TRUE' style='border: none; width: 312px; height: 318px; float: none;' width='312' height='318' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs7">They are color-coded as follows:</p>
+
+<!--(Table)=========================================================-->
+<table x-use-null-cells width="63.089%" cellspacing="0" class="whs8">
+<col class="whs9">
+<col class="whs10">
+
+<tr valign=top>
+<td colspan="1" rowspan="1" width="43.569%" class="whs11">
+<p class="whs12">Color</td>
+<td colspan="1" rowspan="1" width="56.431%" class="whs13">
+<p class="whs14">Signal</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs15">
+<p class="whs16">Green</td>
+<td width="56.431%" class="whs17">
+<p class="whs18">Input</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs19">
+<p class="whs20">Aqua</td>
+<td width="56.431%" class="whs21">
+<p class="whs22">Bidirectional</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs23">
+<p class="whs24">Blue</td>
+<td width="56.431%" class="whs25">
+<p class="whs26">Output</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs27">
+<p class="whs28">Magenta</td>
+<td width="56.431%" class="whs29">
+<p class="whs30">Clock</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs31">
+<p class="whs32">Red</td>
+<td width="56.431%" class="whs33">
+<p class="whs34">VCC</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs35">
+<p class="whs36">Black</td>
+<td width="56.431%" class="whs37">
+<p class="whs38">GND</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs39">
+<p class="whs40">Yellow</td>
+<td width="56.431%" class="whs41">
+<p class="whs42">TDO</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs43">
+<p class="whs44">Gray</td>
+<td width="56.431%" class="whs45">
+<p class="whs46">TDI</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs47">
+<p class="whs48">White</td>
+<td width="56.431%" class="whs49">
+<p class="whs50">Unused Pin</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs51">
+<p class="whs52">Black Outline</td>
+<td width="56.431%" class="whs53">
+<p class="whs54">No available 
+ Pad</td></tr>
+</table>
+
+<p class="whs55">As with the single pin display, rolling 
+ your mouse over any colored pin will pop up a tooltip with the signal 
+ name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the 
+ I/O style, the slew rate, and/or any constraints assigned to the pin.</p>
+
+</body>
+
+</html>
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diff --git a/address_decoder_html/fit/plugin.js b/address_decoder_html/fit/plugin.js
new file mode 100644
index 0000000..cc34368
--- /dev/null
+++ b/address_decoder_html/fit/plugin.js
@@ -0,0 +1,96 @@
+
+function checkJre(){
+
+var agt=navigator.userAgent.toLowerCase();
+var is_major = parseInt(navigator.appVersion);
+
+
+var is_nav = ((agt.indexOf('mozilla')!=-1) && (agt.indexOf('spoofer')== -1)
+&& (agt.indexOf('compatible') == -1) && (agt.indexOf('opera')== -1)
+&& (agt.indexOf('webtv')==-1) && (agt.indexOf('hotjava')== -1));
+var is_nav4up = (is_nav && (is_major >= 4)); 
+
+var is_ie = ((agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1)); 
+var is_ie5 = (is_ie && (is_major == 4) && (agt.indexOf("msie 5.0")!= -1) );
+var is_ie5_5 = (is_ie && (is_major == 4) && (agt.indexOf("msie 5.5") != -1));
+var is_ie6 = (is_ie && (is_major == 4) && (agt.indexOf("msie 6.0") != -1));
+
+var is_ie5up = (is_ie && (is_major == 4) && ( (agt.indexOf("msie 5.0")!=-1) || (agt.indexOf("msie 5.5")!=-1) || (agt.indexOf("msie 6.0")!=-1) ) );
+
+var pluginDetected = false;
+var activeXDisabled = false;
+
+// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up'
+if(is_nav4up) {
+
+  // Refresh 'navigator.mimeTypes' to get newly installed mimeTypes.
+  // Use 'navigator.mimeTypes.refresh(false)' to refresh mimeTypes 
+  // without refreshing open documents (browser windows)
+
+  // check for Java plugin in installed mimeTypes
+  if(navigator.mimeTypes ) {
+    //window.alert( "length");
+    //window.alert( navigator.mimeTypes.length);
+    for (i=0; i <  navigator.mimeTypes.length; i++) {
+      //window.alert(navigator.mimeTypes[i].type);
+      if( (navigator.mimeTypes[ i].type != null)
+        &&(navigator.mimeTypes[ i].type.indexOf(
+        "application/x-java-applet;jpi-version=1.4") != -1) ) {
+
+        pluginDetected = true; 
+       break;
+      }
+
+    }
+  }
+
+} else if (is_ie5up) {
+  var javaVersion;
+  var shell;
+  try {
+    // Create WSH(WindowsScriptHost) shell, available on Windows only
+    shell = new ActiveXObject("WScript.Shell");
+
+    if (shell != null) {
+    // Read JRE version from Window Registry
+      try {
+        javaVersion = shell.regRead
+        ("HKEY_LOCAL_MACHINE\\Software\\JavaSoft\\Java Runtime Environment\\CurrentVersion");
+      } catch(e) {
+      // handle exceptions raised by 'shell.regRead(...)' here
+      // so that the outer try-catch block would receive only
+      // exceptions raised by 'shell = new ActiveXObject(...)'
+      }
+    } 
+  } catch(e) {
+   window.alert(" Creating ActiveX controls thru script is disabled \n in InternetExplorer security options \n To enable it: \n a. Go to the 'Tools -->; Internet Options' menu\n b. Select the 'Security' tab\n c. Select zone (Internet/Intranet)\n d. Click the 'Custom Level..' button which will display the\n 'Security Settings' window.\n e. Enable the option 'Initialize and script ActiveX controls\n not marked as safe' ");
+
+    activeXDisabled = true;
+  } 
+
+  // Check whether we got required (1.4+) Java Plugin
+  if ( (javaVersion != null) && (javaVersion.indexOf("1.4") != -1) ) {
+    pluginDetected = true;
+  }
+
+}
+
+
+if (pluginDetected) {
+
+  // show applet page
+  document.location.href="newappletref.htm";
+
+} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" +
+                   "if you choose not to install the plugin  the reports graphical applets will not be available.")) {
+
+  // show install page
+  document.location.href=XilinxD;
+
+} else {
+  // show error page
+  document.location.href="newappletref.htm";
+}
+
+}
+
diff --git a/address_decoder_html/fit/prev.jpg b/address_decoder_html/fit/prev.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..eb2928581f4bcea54b1064517f7a86135afdf365
GIT binary patch
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diff --git a/address_decoder_html/fit/print.jpg b/address_decoder_html/fit/print.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..b558dece2ea9343c1fe7d777550fc0d8ca8e01ac
GIT binary patch
literal 1683
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diff --git a/address_decoder_html/fit/products.gif b/address_decoder_html/fit/products.gif
new file mode 100644
index 0000000000000000000000000000000000000000..768040424da06354f7c2ef4e69841ba8ec949646
GIT binary patch
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literal 0
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diff --git a/address_decoder_html/fit/purchase.gif b/address_decoder_html/fit/purchase.gif
new file mode 100644
index 0000000000000000000000000000000000000000..177f4ba1b2de5508ac69ac2007dce51858c544ae
GIT binary patch
literal 642
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literal 0
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diff --git a/address_decoder_html/fit/report.htm b/address_decoder_html/fit/report.htm
new file mode 100644
index 0000000..eceb1bb
--- /dev/null
+++ b/address_decoder_html/fit/report.htm
@@ -0,0 +1,27 @@
+<html>
+  <head>
+    <script>
+      function isNS4() {
+      return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) < 5) ) ? true : false;
+      }
+      function isNS7() {
+      return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) >= 5) ) ? true : false;
+      }
+
+      function init(){
+        if( isNS4() ){ 
+          document.location.href="checkNS4.htm";
+        }
+        else if( isNS7() ){
+          document.location.href="check.htm";
+        }
+        else{
+          document.location.href="appletref.htm";
+        }
+      } 
+    </script
+  </head>
+  <body onload="javascript:init()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0">
+  </body>
+
+</html>
diff --git a/address_decoder_html/fit/result.htm b/address_decoder_html/fit/result.htm
new file mode 100644
index 0000000..a63a253
--- /dev/null
+++ b/address_decoder_html/fit/result.htm
@@ -0,0 +1,14 @@
+<html>
+<head>
+  <script>
+    function init() {
+      document.open();
+      document.write(window.opener.document.options.htmlStr.value);
+      document.write("<form><center><input type='button' value='close' onclick='window.close()'></center></form>");
+      document.close();
+    }
+  </script>
+</head>
+<body onload="javascript:init()">
+</body>
+</html>
diff --git a/address_decoder_html/fit/search.gif b/address_decoder_html/fit/search.gif
new file mode 100644
index 0000000000000000000000000000000000000000..714dc20092cf8efa2994765f2d5366c977ae5eb8
GIT binary patch
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literal 0
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diff --git a/address_decoder_html/fit/spacer.gif b/address_decoder_html/fit/spacer.gif
new file mode 100644
index 0000000000000000000000000000000000000000..0eba1992bddd4939c4992c10ea8f5be13da9fee7
GIT binary patch
literal 233
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literal 0
HcmV?d00001

diff --git a/address_decoder_html/fit/style.css b/address_decoder_html/fit/style.css
new file mode 100644
index 0000000..5f32596
--- /dev/null
+++ b/address_decoder_html/fit/style.css
@@ -0,0 +1,19 @@
+<!-- for TOC -->
+.tocRef A:link {font-family:arial black; font-size:14px;}
+.tocRef A:visited {font-family:arial black; font-size:14px;}
+.tocRef A:active {font-family:arial black; font-size:14px;}
+.tocRef A:hover {font-family:arial black; font-size:14px;}
+.tocBgnd {background:#CCCCCC;}
+
+<!-- for page -->
+.pgRef A:link { }
+.pgRef A:visited { }
+.pgRef A:active { }
+.pgRef A:hover { }
+.pgHeader {background:#E7CF5A;}
+.pgBgnd {background:#FFFFFF;}
+
+<!-- for Input ToolTips -->
+#tipBox {position: absolute; width: 150px; z-index: 100;border: 1pt black solid; background: white; visibility: hidden;}
+.tipBoxCursor {cursor:crosshair;}
+
diff --git a/address_decoder_html/fit/summary.js b/address_decoder_html/fit/summary.js
new file mode 100644
index 0000000..6fe7722
--- /dev/null
+++ b/address_decoder_html/fit/summary.js
@@ -0,0 +1,26 @@
+function popWin(url, w, h) {
+  var win = window.open(url, 'win',
+              'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h);
+  win.focus();
+}
+
+function showTop() { parent.leftnav.showTop(); }
+
+function showDoc(device) {
+  var url = docURL;
+  
+  if ((device.indexOf("XC2") != -1) && (device.indexOf("S") != -1))
+    url = docCr2sURL;
+  else if (device.indexOf("XC2") != -1) url = docXbrURL;
+  else if (device.indexOf("XCR3") != -1) url = docXpla3URL;
+  else if (device.indexOf("XV") != -1) url = doc95xvURL;
+  else if (device.indexOf("XL") != -1) url = doc95xlURL;
+  else url = doc95URL;
+
+  popWin(url);
+}
+
+function priceDev(device) {
+  var url = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/1816638537/Catalog";
+  popWin(url);
+}
diff --git a/address_decoder_html/fit/summarydoc.htm b/address_decoder_html/fit/summarydoc.htm
new file mode 100644
index 0000000..71bad37
--- /dev/null
+++ b/address_decoder_html/fit/summarydoc.htm
@@ -0,0 +1,102 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Summary</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=509>
+<meta name=layout-width content=614>
+<meta name=date content="05 24, 2002 11:22:55 AM">
+
+
+
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+<h1>Summary</h1>
+
+<p style="font-size: 10pt;"><span style="font-family: arial, sans-serif;">The 
+ Summary section of the WebFITTER XML report contains several tables summarizing 
+ the fitting results for your design.</span> </p>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The general 
+ Summary table contains the following: </span>
+
+<ul style="list-style: disc;"
+	type=disc>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ design name </span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ fitting status </span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ software version </span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ device used, with a link to a PDF version of the device documentation</span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ time and date of the fitter's completion</span></li>
+</ul>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The Resources 
+ Summary table includes:</span><span style="font-size: 10pt;"> </span>
+
+<ul style="list-style: disc;"
+	type=disc>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ number and percentage of macrocells used </span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ number and percentage of product terms used </span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ number and percentage of registers used</span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ number and percentage of pins used <!--kadov_tag{{<spaces>}}-->&nbsp;</span><!--kadov_tag{{</spaces>}}--></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ number and percentage of function block inputs used</span></li>
+</ul>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The tables 
+ that follow give more detailed summaries (when appropriate, depending 
+ on your design and device) of the pin resources, macrocell resources, 
+ global resources, and block resources utilized by the fitter, as well 
+ as the macrocell power data for the design.</span> 
+
+</body>
+
+</html>
diff --git a/address_decoder_html/fit/support.gif b/address_decoder_html/fit/support.gif
new file mode 100644
index 0000000000000000000000000000000000000000..a154620eb23ea85665f2a9d925132d1cb474dbdb
GIT binary patch
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literal 0
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diff --git a/address_decoder_html/fit/tooltips.js b/address_decoder_html/fit/tooltips.js
new file mode 100644
index 0000000..790ce27
--- /dev/null
+++ b/address_decoder_html/fit/tooltips.js
@@ -0,0 +1,143 @@
+/*  Your are permitted to reuse this code as long as the following copyright
+    notice is not removed:
+
+    This HTML tip handling is copyright 1998 by insideDHTML.com, LLC. More information about this
+    code can be found at Inside Dynamic HTML: HTTP://www.insideDHTML.com
+*/
+
+
+// Support for all collection
+var allSupport = document.all!=null;
+
+function setupEventObject(e) {
+  // Map NS event object to IEs
+  if (e==null) return; // IE returns
+  window.event = e;
+  window.event.fromElement = e.target;
+  window.event.toElement = e.target;
+  window.event.srcElement = e.target;
+  window.event.x = e.x;
+  window.event.y = e.y;
+  // Route the event to the original element
+  // Necessary to make sure _tip is set.
+  window.event.srcElement.handleEvent(e);
+}
+
+function checkName(src) {
+  // Look for tooltip in IE
+  while ((src!=null) && (src._tip==null))
+    src = src.parentElement;
+  return src;
+}
+
+function getElement(elName) {
+  // Get an element from its ID
+  if (allSupport) return document.all[elName];
+  else            return document.layers[elName];
+}
+
+function writeContents(el, tip) {
+  // Replace the contents of the tooltip
+  if (allSupport)
+    el.innerHTML = tip;
+  else {
+    // In NS, insert a table to work around
+    // stylesheet rendering bug.
+    // NS fails to apply style sheets when writing
+    // contents into a positioned element.
+    el.document.open();
+    el.document.write("<TABLE WIDTH=200 BORDER=1 bordercolor=black><TR><TD WIDTH=100% BGCOLOR=yellow>");
+    el.document.write(tip);
+    el.document.write("</TD></TR></TABLE>");
+    el.document.close();
+  }
+}
+
+function getOffset(el, which) {
+  // Function for IE to calculate position
+  // of an element.
+  var amount = el["offset"+which];
+  if (which=="Top") amount+=el.offsetHeight;
+  el = el.offsetParent;
+  while (el!=null) {
+    amount+=el["offset"+which];
+    el = el.offsetParent;
+  }
+  return amount;
+}
+
+
+function setPosition(el) {
+  // Set the position of an element
+
+  src = window.event.srcElement
+  if (allSupport) {
+    el.style.pixelTop = getOffset(src, "Top");
+    el.style.pixelLeft = getOffset(src, "Left");
+  }
+  else {
+    el.top = src.y + 20; //window.event.y + 15
+    el.left = src.x; //window.event.x
+  }
+}
+
+function setVisibility(el, bDisplay) {
+  // Hide or show to tip
+  if (bDisplay) {
+    if (allSupport) el.style.visibility = "visible";
+    else            el.visibility = "show";
+  }
+  else {
+    if (allSupport) el.style.visibility = "hidden";
+    else            el.visibility = "hidden";
+  }
+}
+
+
+function displayContents(tip) {
+  // Display the tooltip.
+  var el = getElement("tipBox");
+  writeContents(el, tip);
+  setPosition(el);
+  setVisibility(el, true);
+}
+
+
+function doMouseOver(e) {
+  // Mouse moves over an element
+  setupEventObject(e);
+  var el, tip;
+  if ((el = checkName(window.event.srcElement))!=null) {
+    if  (!el._display) {
+      displayContents(el._tip);
+      el._display = true;
+    }
+  }
+}
+
+function doMouseOut(e) {
+  // Mouse leaves an element
+  setupEventObject(e);
+  el = checkName(window.event.srcElement);
+  var el, tip;
+  if ((el = checkName(window.event.srcElement))!=null) {
+    if (el._display) {
+      if ((el.contains==null) || (!el.contains(window.event.toElement))) {
+        setVisibility(getElement("tipBox"), false);
+        el._display = false;
+      }
+    }
+  }
+}
+
+function doLoad() {
+  // Do Loading
+  if ((window.document.captureEvents==null) && (!allSupport))
+    return; // Not IE4 or NS4
+  if (window.document.captureEvents!=null)  // NS - capture events
+    window.document.captureEvents(Event.MOUSEOVER | Event.MOUSEOUT)
+  window.document.onmouseover = doMouseOver;
+  window.document.onmouseout = doMouseOut;
+}
+
+window.onload = doLoad;
diff --git a/address_decoder_html/fit/topnav.js b/address_decoder_html/fit/topnav.js
new file mode 100644
index 0000000..0e85b7b
--- /dev/null
+++ b/address_decoder_html/fit/topnav.js
@@ -0,0 +1,28 @@
+function popWin(url) {
+  var win = window.open(url, 'win',
+              'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600');
+  win.focus();
+}
+
+function openTab(type, device) {
+  var url = rootURL;
+  switch (type) {
+    case 0: url = rootURL; break;
+    case 1:
+      if (device.indexOf('XC2') != -1) url += prodURL + xbrURL;
+      else if (device.indexOf('XCR3') != -1) url += prodURL + xpla3URL;
+      else if (device.indexOf('XV') != -1) url += prodURL + xc9500xvURL;
+      else if (device.indexOf('XL') != -1) url += prodURL + xc9500xlURL;
+      else url += prodURL + xc9500URL;
+      break;
+    case 2: url += marketURL; break;
+    case 3: url = supportURL; break;
+    case 4: url += educationURL; break;
+    case 5: url = buyURL; break;
+    case 6: url += contactURL; break;
+    case 7: url += searchURL; break;
+    default: url = rootURL;
+  }
+
+  popWin(url);
+}
diff --git a/address_decoder_html/fit/unmapinputdoc.htm b/address_decoder_html/fit/unmapinputdoc.htm
new file mode 100644
index 0000000..fe242d6
--- /dev/null
+++ b/address_decoder_html/fit/unmapinputdoc.htm
@@ -0,0 +1,65 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>unmapinputdoc</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=353>
+<meta name=layout-width content=615>
+<meta name=date content="11 26, 2002 2:10:18 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Unmapped Inputs</h1>
+
+<p class="whs1">This page shows 
+ input signals which were either not mapped or <span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">not 
+ routed.</FONT></span></p>
+
+</body>
+
+</html>
diff --git a/address_decoder_html/fit/unmaplogicdoc.htm b/address_decoder_html/fit/unmaplogicdoc.htm
new file mode 100644
index 0000000..6371313
--- /dev/null
+++ b/address_decoder_html/fit/unmaplogicdoc.htm
@@ -0,0 +1,68 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>unmaplogicdoc</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=353>
+<meta name=layout-width content=615>
+<meta name=date content="11 26, 2002 2:04:45 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-size: 22pt; font-weight: bold;}
+p.whs2 {font-family: arial, sans-serif; font-size: 10pt; font-weight: normal;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<p class="whs1">Unmapped Logic</p>
+
+<p class="whs2">This page shows those equations whose 
+ logic was either not placed or not <span style="font-family: arial, sans-serif;
+													font-size: 10pt;
+													font-weight: normal;"><FONT SIZE=2 style="font-size:10pt;">completely 
+ placed in the specified device.</FONT></span></p>
+
+</body>
+
+</html>
diff --git a/address_decoder_html/fit/verboseview.jpg b/address_decoder_html/fit/verboseview.jpg
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diff --git a/address_decoder_html/fit/view.gif b/address_decoder_html/fit/view.gif
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diff --git a/address_decoder_html/tim/CVS/Entries b/address_decoder_html/tim/CVS/Entries
new file mode 100644
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--- /dev/null
+++ b/address_decoder_html/tim/CVS/Entries
@@ -0,0 +1,9 @@
+/cpldta_glossary.htm/1.3/Wed Apr  9 21:33:40 2003//Tbuild+G-38+0
+/cpldta_style.css/1.2/Thu Mar 20 05:15:52 2003//Tbuild+G-38+0
+/genreport.htm/1.2/Fri Mar 28 22:16:03 2003//Tbuild+G-38+0
+/leftnav.htm/1.2/Thu Mar 20 05:15:53 2003//Tbuild+G-38+0
+/report.htm/1.3/Fri Mar 28 22:16:03 2003//Tbuild+G-38+0
+/timing_report.htm/1.2/Fri Mar 28 22:16:03 2003//Tbuild+G-38+0
+/toc.css/1.3/Fri May  2 20:51:18 2003//Tbuild+G-38+0
+/topnav.htm/1.4/Fri May  2 20:51:18 2003//Tbuild+G-38+0
+D
diff --git a/address_decoder_html/tim/CVS/Repository b/address_decoder_html/tim/CVS/Repository
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+++ b/address_decoder_html/tim/CVS/Repository
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+env/Jobs/Cpld/CPLDTa/ta/data/tim
diff --git a/address_decoder_html/tim/CVS/Root b/address_decoder_html/tim/CVS/Root
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+:pserver:relman@igor-174:/devl/xcs/repo
diff --git a/address_decoder_html/tim/CVS/Tag b/address_decoder_html/tim/CVS/Tag
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diff --git a/address_decoder_html/tim/cpldta_glossary.htm b/address_decoder_html/tim/cpldta_glossary.htm
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+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>CPLD Timing Analysis Glossary</title>
+
+<!--(Meta)==========================================================-->
+
+<meta http-equiv=Content-Type content="text/html; charset=UTF-8">
+<meta name=Author content=administrator>
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=2677>
+<meta name=layout-width content=716>
+<meta name=date content="04 8, 2003 10:49:54 AM">
+
+
+<!--(Links)=========================================================-->
+
+<link rel=StyleSheet href=xilhtml.css>
+
+
+
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+<h1>Introduction</h1>
+
+<p>This report is the result of a static timing analysis of your design 
+ after it has been fit in the device that you selected. The timing values 
+ given represent the worst-case values over the recommended operating conditions 
+ for the part. </p>
+
+<h1>Overview</h1>
+
+<p>The timing report consists of a series of sections: </p>
+
+<h2>Summary</h2>
+
+<p>This table summarizes the external timing parameters for your device, 
+ including <a href="#tPD"><!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}--></a>, 
+ <a href="#tCO"><!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}--></a>, 
+ <a href="#tSU"><!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--></a>, 
+ <a href="#tCYC"><!--kadov_tag{{<ignored>}}-->tCYC<!--kadov_tag{{</ignored>}}--></a>, 
+ and <a href="#fSYSTEM"><!--kadov_tag{{<ignored>}}-->fSYSTEM<!--kadov_tag{{</ignored>}}--></a>. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->For a more 
+ detailed description of the timing model for your device, please refer 
+ to the application notes linked below.</p>
+
+<h2>Timing Constraints</h2>
+
+<p>This section reports on any timing constraints that you created for 
+ your design. Timing constraints can be entered using the Constraints Editor 
+ tool, or by editing an Implementation Constraints File directly. For more 
+ information on creating timing constraints, see the Constraints Guide. 
+ </p>
+
+<p class=Note><span style="font-weight: bold;">Note</span> that if you 
+ did not define any constraints for your design, then the timing analysis 
+ software will automatically create a default set of constraints for you. 
+ These include pad-to-pad, register-to-register, pad-to-register, and period 
+ constraints. A constraint value of 0 <!--kadov_tag{{<ignored>}}-->ns<!--kadov_tag{{</ignored>}}--> 
+ will be used for all of these automatically generated constraints. As 
+ a result, all paths listed under each constraint will violate the constraint, 
+ and will have a negative value for slack.</p>
+
+<p class=Note><span style="font-weight: bold;">Note</span> also that to 
+ limit the size of the report, each path endpoint involved in a timing 
+ path will only be listed once, under a single constraint. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
+
+<p>For each timing path listed under a constraint, there is a hyperlink 
+ that can be used to open a window listing the individual internal delay 
+ elements traversed in the path. To understand these delay elements, consult 
+ the <a href="#Definitions">Definitions</a> section below, or the following 
+ application notes and white papers: </p>
+
+<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP375: Understanding 
+ the <!--kadov_tag{{<ignored>}}-->CoolRunner-II<!--kadov_tag{{</ignored>}}--> 
+ Timing Model</a> </p>
+
+<p><a href="http://www.xilinx.com/publications/whitepapers/index.htm">WP122: 
+ Using the <!--kadov_tag{{<ignored>}}-->CoolRunner<!--kadov_tag{{</ignored>}}--> 
+ XPLA3 Timing Model</a> </p>
+
+<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP071: Using 
+ the XC9500 Timing Model</a> </p>
+
+<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP111: Using 
+ the XC9500XL Timing Model</a></p>
+
+<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2"><!--kadov_tag{{<ignored>}}-->XAPP<!--kadov_tag{{</ignored>}}--> 
+ 362: Using the XC9500XV Timing Model</a></p>
+
+<p>available in the literature section of <a href="http://www.xilinx.com"><!--kadov_tag{{<ignored>}}-->www.xilinx.com</a>.<!--kadov_tag{{</ignored>}}--> 
+ </p>
+
+<h2>Data Sheet Report</h2>
+
+<p>This section of the report lists the external timing parameters for 
+ your design. This includes; maximum external clock speed for each clock, 
+ setup and hold times for each registered input, clock-to-output pad timing 
+ for each registered output, clock to setup time for each register-to-register 
+ timing path, and pad-to-pad time for each combinatorial path through your 
+ design. </p>
+
+<h2>Going Further</h2>
+
+<p>To do more advanced timing analysis of your design, select the process 
+ <span style="font-weight: bold;">Analyze Post-Fit Static Timing</span> 
+ in <!--kadov_tag{{<ignored>}}-->iSE<!--kadov_tag{{</ignored>}}-->. This 
+ will run <!--kadov_tag{{<ignored>}}-->Xilinx's<!--kadov_tag{{</ignored>}}--> 
+ Timing Analyzer tool interactively. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ Timing Analyzer provides a powerful, flexible, and easy way to perform 
+ static timing analysis on <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}--> 
+ and <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}--> designs. 
+ With Timing Analyzer, analysis can be performed immediately after mapping, 
+ placing or routing an <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}--> 
+ design, and after fitting and routing a <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}--> 
+ design. </p>
+
+<p>Timing Analyzer verifies that the delay along a given path or paths 
+ meets specified timing requirements. It organizes and displays data that 
+ allows you to analyze critical paths in a circuit, the cycle time of the 
+ circuit, the delay along any specified <!--kadov_tag{{<ignored>}}-->path(s<!--kadov_tag{{</ignored>}}-->), 
+ and the path with the greatest delay. It also provides a quick analysis 
+ of the effect different speed grades have on the same design. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
+
+<p>Timing Analyzer performs setup and hold checks (skew analysis). It works 
+ with synchronous systems composed of synchronous elements and combinatorial 
+ logic. In synchronous design, Timing Analyzer takes into account all path 
+ delays, including clock-to-out and setup requirements, while calculating 
+ the worst-case timing of the design. </p>
+
+<p>Timing Analyzer creates timing analysis reports based on existing timing 
+ constraints or user specified paths within the program. Timing reports 
+ have a hierarchical browser to quickly jump to different sections of the 
+ reports. Timing paths in reports can be cross probed to synthesis tools 
+ (Exemplar and <!--kadov_tag{{<ignored>}}-->Synplicity<!--kadov_tag{{</ignored>}}-->) 
+ and <!--kadov_tag{{<ignored>}}-->Floorplanner<!--kadov_tag{{</ignored>}}-->. 
+ </p>
+
+<p>There are several ways to issue commands in Timing Analyzer. Timing 
+ Analyzer can be controlled through <!--kadov_tag{{<ignored>}}-->GUI<!--kadov_tag{{</ignored>}}--> 
+ features (menu commands) or its comprehensive macro command language facility. 
+ You can select from menus, click toolbar buttons, type keyboard commands 
+ in the console window, and run macros. </p>
+
+<h1><a name=Definitions></a>Definitions</h1>
+
+<h2><a name=tPD></a>Pad to Pad (<!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}-->) 
+ </h2>
+
+<p>Reports pad to pad paths that start at input pads and end at output 
+ pads. The maximum external pad to pad delay. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Combinatorial 
+ pad-to-pad paths begin at input pads, propagate through one or more levels 
+ of combinatorial logic and end at output pads. Combinatorial paths also 
+ trace through the enable inputs of 3-state controlled pads. Combinatorial 
+ paths are not traced through clock, and asynchronous set and reset inputs 
+ of registers. These paths are also broken at bidirectional pins</p>
+
+<h2><a name=tCO></a>Clock Pad to Output Pad (<!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}-->) 
+ </h2>
+
+<p>The maximum external clock pad to output pad delay. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Reports 
+ paths that start at input <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->pads 
+ trace through clock inputs of <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->registers 
+ and end at output pads. Paths are not traced through PRE/<!--kadov_tag{{<ignored>}}-->CLR<!--kadov_tag{{</ignored>}}--> 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->inputs 
+ of registers. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can directly specify <!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}--> 
+ for all registered output paths in your design using the Pad-to-Pad <!--kadov_tag{{<ignored>}}-->timespec<!--kadov_tag{{</ignored>}}-->. 
+ Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate 
+ through global clock buffers, and propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}--> 
+ output and any number of levels of combinatorial logic and end at the 
+ output pad. Clock-Pad-to-Pad paths for product term clock paths begin 
+ at input pads, propagate through any number of logic levels feeding into 
+ a clock product term, propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}--> 
+ output and any number of levels of combinatorial logic and end at the 
+ output pad. Clock-Pad-to-Pad paths also trace through the enable inputs 
+ of 3-state controlled pads.</p>
+
+<h2><a name=tSU></a>Setup to Clock at Pad (<!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--> 
+ or <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->) </h2>
+
+<p>Reports external setup time of data <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->to 
+ clock at pad. Data path starts at an input pad and ends at register <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->(Fast 
+ Input Register for <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->) 
+ D/<!--kadov_tag{{<ignored>}}-->T<!--kadov_tag{{</ignored>}}--> <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->input. 
+ Clock path starts at input pad and ends at the register clock input. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Paths 
+ are not traced through registers. Pin-to-pin setup requirement is not 
+ reported or guaranteed for product-term clocks derived from <!--kadov_tag{{<ignored>}}-->macrocell<!--kadov_tag{{</ignored>}}--> 
+ feedback signals. </p>
+
+<p>The minimum required setup time for flip-flops. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can specify the <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--> 
+ (setup-to-clock) for all inputs in your design relative to a global clock 
+ or product term clock. Each <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--> 
+ OFFSET timespec involves an input path and a clock path. Input paths start 
+ at input pads, propagate through input buffers and any number of combinatorial 
+ logic levels before ending at a flip-flop D/T input, including the receiving 
+ flip-flop's tSU. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Input 
+ paths are not traced through flip-flop clock pins, asynchronous set/reset 
+ inputs or bidirectional I/O pins. Global clock paths start at global clock 
+ pads, propagate through global clock buffers and end at the flip-flop 
+ clock pin. Product term clock paths start at input pads, propagate through 
+ a single level of logic implemented in a clock product term and end at 
+ the flip-flop clock pin.</p>
+
+<h2><a name=tCYC></a>Clock to Setup (tCYC) </h2>
+
+<p>Register to register cycle time. Includes source register tCO and destination 
+ register tSU. </p>
+
+<p class=Note><span style="font-weight: bold;">Note</span> that when the 
+ computed Maximum Clock Speed is limited by tCYC, it is computed assuming 
+ that all registers are rising-edge sensitive. </p>
+
+<h2><a name=fSYSTEM></a>fSYSTEM </h2>
+
+<p>Maximum clock operating frequency. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can specify the fSYSTEM (clock frequency or period) for all registered 
+ paths in your design using a Register-to-Register timespec. Register-to-Register 
+ paths begin at flip-flop clock inputs, propagate through the flip-flop 
+ Q output and any number of levels of combinatorial logic and end at the 
+ receiving flip-flop D/T input, including the receiving flip-flop's tSU. 
+ When these flip-flops are clocked by the same clock, the delay on this 
+ path is equivalent to the cycle time of the clock. Registered paths do 
+ not propagate through clock, and asynchronous set and reset inputs of 
+ registers as shown below. These paths are also broken at bidirectional 
+ pins.</p>
+
+<p>&nbsp;</p>
+
+</body>
+
+</html>
diff --git a/address_decoder_html/tim/cpldta_style.css b/address_decoder_html/tim/cpldta_style.css
new file mode 100644
index 0000000..4b82019
--- /dev/null
+++ b/address_decoder_html/tim/cpldta_style.css
@@ -0,0 +1,144 @@
+<!-- $Id: cpldta_style.css,v 1.2 2003/03/20 05:15:52 soeren Exp $  -->
+<!-- Stylesheet for the CPLD HTML Timing Report                  -->
+
+<!-- style for H1 elements  -->
+.cpldta_text_report_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 25pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+<!-- style for H2 elements  -->
+.cpldta_text_section_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 15pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+<!-- style for H3 elements  -->
+.cpldta_text_subsection_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+
+<!-- Following used for the header of the notes and warnings table  -->
+.cpldta_warnings_header {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;
+	background-color: #FFFFCC; }
+
+<!-- style for general text value fields  -->
+.cpldta_text_normal {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+	
+<!-- style for general text label fields  -->
+.cpldta_text_normal_bold {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+
+<!-- Following two styles are used for constraint descriptions  -->
+.cpldta_constraint_description_normal {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+.cpldta_constraint_description_bold {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+
+<!-- Style for the name of a constraint that is met  -->
+.cpldta_constraint_name {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+
+<!-- Style for the name of a constraint that is not met  -->
+.cpldta_constraint_name_error {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;
+	background-color: #FFCCCC; }
+
+<!-- Style for the delay of a constraint that is met  -->
+.cpldta_time_value {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+	
+<!-- Style for the delay of a constraint that is not met  -->
+.cpldta_time_value_error {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;
+	background-color: #FFCCCC; }
+
+<!-- Styles for the header of the delay table for a constraint  -->
+.cpldta_delaytable_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 12pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;
+	background-color: #FFFFCC; }
+.cpldta_constraint_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;
+	background-color: #FFFFCC; }
+.cpldta_time_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;
+	background-color: #FFFFCC; }
+.cpldta_text_caption {
+	font-style: normal;
+	font-weight: Bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+
+<!-- Following styles used for the datasheet section of the report  -->
+.cpldta_datasheet_pathname {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+.cpldta_datasheet_time_value {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+
+
+
+
diff --git a/address_decoder_html/tim/genreport.htm b/address_decoder_html/tim/genreport.htm
new file mode 100644
index 0000000..43aca47
--- /dev/null
+++ b/address_decoder_html/tim/genreport.htm
@@ -0,0 +1,17 @@
+<html>
+<head>
+<title>Reports</title>
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+</head>
+<frameset rows="94,*" cols="*" frameborder="NO" border="0" framespacing="0">;
+  <frame name="topFrame" scrolling="NO" noresize src="topnav.htm" marginwidth="0" marginheight="0">
+  <frameset cols="160,*" frameborder="NO" border="0" framespacing="0" rows="*"> 
+    <frame name="leftFrame" noresize scrolling="NO" src="leftnav.htm" marginwidth="0" marginheight="0">
+    <frame name="mainFrame" src="timing_report.htm" marginwidth="0" marginheight="0">
+  </frameset>
+</frameset>
+<noframes> 
+<body bgcolor="#FFFFFF" text="#000000">
+</body>
+</noframes> 
+</html>
diff --git a/address_decoder_html/tim/leftnav.htm b/address_decoder_html/tim/leftnav.htm
new file mode 100644
index 0000000..e72761d
--- /dev/null
+++ b/address_decoder_html/tim/leftnav.htm
@@ -0,0 +1,37 @@
+<html>
+<head>
+<title>Timing Navigation</title>
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+<link rel="stylesheet" type="text/css" href="../tim/toc.css">
+</head>
+
+<body bgcolor="#CCCCCC" text="#000000" onLoad="parent.frames.mainFrame.location='timing_report.htm'">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">
+  <tr> 
+    <td colspan="3"> 
+      <div align="left"><SPAN class="HEADING">Timing Report</span></div>
+    </td>
+  </tr>
+  <tr>
+    <td width="7">&nbsp;</td>
+    <td colspan="2"><a href="timing_report.htm#TimingReport" target="mainFrame" class="SECONDARY-NAV">Description</a></td>
+  </tr>
+  <tr> 
+    <td width="7">&nbsp;</td>
+    <td colspan="2"><a href="timing_report.htm#Summary" target="mainFrame" class="SECONDARY-NAV">Summary</a></td>
+  </tr>
+  <tr> 
+    <td width="7">&nbsp;</td>
+    <td colspan="2"><a href="timing_report.htm#TimingConstraints" target="mainFrame" class="SECONDARY-NAV">Constraints</a></td>
+  </tr>
+  <tr> 
+    <td width="7">&nbsp;</td>
+    <td colspan="2"><a href="cpldta_glossary.htm" target="mainFrame" class="SECONDARY-NAV">Definitions</a></td>
+  </tr>
+  <tr> 
+    <td width="7">&nbsp;</td>
+    <td colspan="2">&nbsp;</td>
+  </tr>
+</table>
+</body>
+</html>
diff --git a/address_decoder_html/tim/report.htm b/address_decoder_html/tim/report.htm
new file mode 100644
index 0000000..fcd16d4
--- /dev/null
+++ b/address_decoder_html/tim/report.htm
@@ -0,0 +1,14 @@
+<html>
+<head>
+<title>Reports</title>
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+</head>
+<frameset rows="94,*" cols="*" frameborder="NO" border="0" framespacing="0">;
+  <frame name="topFrame" scrolling="NO" noresize src="topnav.htm" marginwidth="0" marginheight="0">
+  <frame name="mainFrame" src="timing_report.htm" marginwidth="0" marginheight="0">
+</frameset>
+<noframes> 
+<body bgcolor="#FFFFFF" text="#000000">
+</body>
+</noframes> 
+</html>
diff --git a/address_decoder_html/tim/timing_report.htm b/address_decoder_html/tim/timing_report.htm
new file mode 100644
index 0000000..8dd7141
--- /dev/null
+++ b/address_decoder_html/tim/timing_report.htm
@@ -0,0 +1,10 @@
+<html><head>
+
+<title>Timing report</title><meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"></head>
+<body bgcolor="#ffffff" text="#000000">
+<p><font face="Arial, Helvetica, sans-serif" size="2">No timing data is available 
+  for your design. </font></p>
+<p><font face="Arial, Helvetica, sans-serif" size="2">Please double click on the 
+  <b>Generate Timing</b> process in the "Process for Current Sources" 
+  window.</font></p>
+</body></html>
\ No newline at end of file
diff --git a/address_decoder_html/tim/toc.css b/address_decoder_html/tim/toc.css
new file mode 100644
index 0000000..29af0e1
--- /dev/null
+++ b/address_decoder_html/tim/toc.css
@@ -0,0 +1,36 @@
+.HEADING { 
+	font-size: 15px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #000000; 
+	text-align: normal; 
+	margin-left: 0px; } 
+.Fitting { 
+	font-size: 11px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #000000; 
+	text-align: normal; 
+	margin-left: 0px; }	
+.SECONDARY-NAV { 
+	font-size: 11px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #FFFFFF; 
+	margin-left: 0px; 
+	text-decoration: none; ; 
+	list-style-type: disc ; 
+	list-style-position: inside } 
+.Timing { 
+	font-size: 11px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #333333; 
+	margin-left: 0px; 
+	text-decoration: none; ; 
+	list-style-type: disc ; 
+	list-style-position: inside } 
+.Timing-Error { 
+	font-size: 11px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #990000; 
+	margin-left: 0px; 
+	text-decoration: none; ; 
+	list-style-type: disc ; 
+	list-style-position: inside } 
diff --git a/address_decoder_html/tim/topnav.htm b/address_decoder_html/tim/topnav.htm
new file mode 100644
index 0000000..00e11b8
--- /dev/null
+++ b/address_decoder_html/tim/topnav.htm
@@ -0,0 +1,31 @@
+<html>
+<head>
+<title>CPLD Reports Banner</title>
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+</head>
+
+<body bgcolor="#FFFFFF" text="#000000">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">
+  <tr> 
+    <td width="607" height="69"><img src="../images/cpldBanner.jpg" width="486" height="69"></td>
+    <td width="251"><img src="../images/logo.jpg"></td>
+    <td bgcolor="#FFFFFF">&nbsp;</td>
+  </tr>
+  <tr> 
+    <td bgcolor="#000000" height="24">
+	  <img src="../images/blackBar.jpg" width="125" height="24">
+	  <img src="../images/fitterRpt.jpg" width="88" height="24" usemap="#fitReport" border="0">
+	  <img src="../images/spacer.jpg" width="32" height="24">
+	  <img src="../images/timingRpt.jpg" width="100" height="24" usemap="#timReport" border="0">
+    <td bgcolor="#000000" height="24">&nbsp;</td>
+    <td bgcolor="#000000">&nbsp;</td>
+  </tr>
+</table>
+<map name="fitReport"> 
+  <area shape="rect" coords="1,1,86,22" href="../fit/report.htm" target="_top">
+</map>
+<map name="timReport">
+  <area shape="rect" coords="1,1,101,24" href="../tim/report.htm" target="_top">
+</map>
+</body>
+</html>
diff --git a/spi65.dhp b/spi65.dhp
index dccbe65..1cadedc 100644
--- a/spi65.dhp
+++ b/spi65.dhp
@@ -1,3 +1,3 @@
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.2e
-$7dx4>763-Xnzd}foo8#5+72(-k0=989971304g<9=<=5;=841c851011?9<;=o415567623:?k0=99:410;13g<9=3:94>855c851?381>?95o415;74=31>;20MmgN`off>GukaEifhm{s89Ahjel\pzn56M@MLKWP@B03JXNMYKK8:AliuOi{}k0IczftxKmwqg<Mg~bxt@nmd`8BljbLlznbi}7;GkoaKgjmk1Meak@bkNjwq><N`fn\lzga:Djh`Ubzoxm6GacmwgaJdm>2FDMIKK8:Nbjbsfolh0@dl}as{Mehc692Fbno}yRvbp`kbf}y37@k|s`efwg=Wijajkh@nmd;8Tdttm]cfi95_asv:?Tsfd`lbih4SQK5154E9';%zej>3:QSM337:K;%=#xgd,33245<[YC=9=<M1/3-rmb*99=:?6]_I7736G7)9'|ch ?>4018WUO1=98I=#?!vif.5436;2Y[E;;?2C3-5+pol$;9><=4SQK5154E9';%zej"13127>UWA??;>O?!1/tk`(71:890_]G9510A5+7)~an&=;=>1:QSM337:K;%=#xgd,025>UWA??;>O?!1/tk`(56:2Y[E;;?2C3-5+pol$9?=?5\PH4647D6&8$}di#<5008WUO1=98I=#?!vif.07753ZZB:8>=B0,2*snc%=9:>6]_I7736G7)9'|ch 6=139PTL028;H:"< yhe/;73=Tm{|no5[ervUafrhzzh0Xb~IimgOmvrc3\yn_yo{elgmpv7c3QCGECV"XE@#4+7'[]_I,= > @Q@ML0<PmhTEi??;Yfn[Hgmg{\n~~g`n028\akXE`dd~[k}shmm7>gkdh1iieoyinpbh`=emak}eb|nl,326`=emak}eb|nl,314`=emak}eb|nl,31<`=emak}eb|nl,35<a=emak}eb|nl,63`>db`h|bcoc-5:`?gcoicd~lb"8e9aamgqafxj` 67a:`jjaCi|`~rn6lfneRbgng`m=1bihkm;hl`hpbb%8:3n6gacmwga(76>k1bbnbzdd/261d<agigyik"176b?lhdd|nn!>86;hl`hpbb%=k0ecmcueg.01g<agigyik"85:8kglNfmoso6}loqgBvfnHjci0naeGkoaJdmk2yhc}kCiogMqh0<{`g{`h64sqk5154ek2y{e;;?2c/254e<{yc=9=<m-03:g>uwa??;>o#>26a8wuo1=98i!<88b:qsm337:k'85o5|ph4647d*<>k0}g9510a)2d<{yc=9=<m-95f?vrcWeelenQ>17626>uslVfdkdmPuoqjckcc?2xi ??969vw`+699=0y~k"1054?pub%8;3;6{|e,3112=r{l':>;94urg.53303|yn!<896:wpa(50>2xi =76:wpa(22>2xi :95:wpa(323|yn!;84urg.<00<}zo&4;sO@q61?EF=:0M6<m51zQf>05=93;8?l>82;0b=16|f:21=6`<9;08 61=;?1v_i4:3;39565f8>81>l7;1:Q2<?34280:?>o?7381e<253Zn19>4>:010e5152;kon;5\19867?7=9:9j<:<52`fee>Uc2<91=7?<3`246?4fm?k0_<655282>454i9ij6?m=5`9P`?34280:?>o?c`81`5c13Z;368=51;307d6dj3;:j?94Se867?7=9:9j<nl5132ag>U603?86<4>32c3`g<6lkin7^j55282>454i9ni6<kn049P5=<2;3;1=>=n13396d44j2Yo68=51;307d75938j>9?4S0:916<62898m<k6:36a14=Tl3?86<4>32c2a<<5<l?27^?7:4195?74;h;nm7?806d8Wa<2;3;1=>=n1dc95<13;2Y:47;<:08276g6mh0:5o><;Rf916<62898m<kn:0;a50=T910>?7?5121`2d1=:m:nm6]k:4195?74;j<j;7<k5878W4>==:0:6<=<c62b>733i;1Xh7;<:08276e08h0999l;;R3;>05=93;8?n9?a;062`6<[m0>?7?5121`35g=:<n2=6]>8;70>4<6;:i<<l4=75d1?Vb==:0:6<=<c62b>7119l1o9>4?:082Vc==:0:6<=<a151>7g><91e8k4n8:M00?6<G8>1<6xI2983>4<629qXi7;<:08276e08h099n99;o3:>4=e:00;6=4::1ym17<63gi1=6A<2;28 4e=82.:?7<>;%36>5=#9o0;7)?j:89L57<73F;=6=5@5082xd3i3:1<7>50zl66?`anolmjk5ac;034>I4:3:0C>;52zL5g<73th=97>50;294~h2:38:7cm51128K64=82.:m7:9;%3g>0b<,;:1?l5@4483?J3628qvC<951z~f30=83:1<7>tn40967=ik3;;<6A<2;28 4g=<?1/=i4:e:&14?5f3F>>6=5@5082xI6?3;pqpl:8;294?6=8rd>>7<j;oa96>I4:3:0(<?5559Lf?6<G<;1=vs@1682x{e;o0;6=4?:1ym17<3>2dh695@3383?!g=;k1/?>4?;%32>02<Go0;7B??:19L01<73F?:6<urO4295~{zutwvLMMt438g44`508hvLMLt0|BCT~I5?3887B<n:3a8K7g=;81D>k4=3:M04?4?3F9?6?=4O2796==H;009?6A<a;0;?J272;90C9?53c9~DE
\ No newline at end of file
+$91x4>763-Xnzd}foo8#5+72(-k0=989971304g<9=<=5;=841c851011?9<;=o415567623:?k0=99:410;13g<9=3:94>855c851?381>?95o415;74=31>;k0=97626711=g<9=32>:;=58:8EweoFhgnn6O}ciMan`es{01I`bmdTxrf=>EHEDC_XHJ8;BPFEQCC02Ida}Gasuc8Akrn|pCeyo4Eovjp|Hfelh0JdbjDdrfjau?3OcgiCobec9EmicHjcFby64FhnfTdroi2Lb`h]jrwgpe>OikeoiBle8:KmwqHfel<0@BOKEE:8Hdh`}hmnn6Bfbscq}Kgjm8;0@dl}as{Ppdrbeld55Berqbc`ue3YkhglijN`of=>Vfzzo_e`k;;Qcqp<=V}hfbjdk}f:QSM337:K;%=#xgd018WUO1=98I=#?!vif.5506;2Y[E;;?2C3-5+pol$;;;<=4SQK5154E9';%zej"10627>UWA??;>O?!1/tk`(76=890_]G9510A5+7)~an&=?<>3:QSM337:K;%=#xgd,31745<[YC=9=<M1/3-rmb*9?8:?6]_I7736G7)9'|ch ?93018WUO1=98I=#?!vif.5266;2Y[E;;?2C3-5+pol$;<=<?4SQK5154E9';%zej"2038WUO1=98I=#?!vif.744<[YC=9=<M1/3-rmb*;=;97^^F6421F4(6&bo!>;>2:QSM337:K;%=#xgd,6157=TX@<><?L>.0,ula+3;880_]G9510A5+7)~an&4??=;RRJ2065J8$:"{fk-915?Vcu~lyi7Yk|tWg`pjttj2^d|KgceMkpp==Rf`~Em`kk;TqfWqgsmdoex~?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED84Xe`\Ma773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee;6okd^ffgg=flmUoin#>76d8eabumzyThhm`ddp27>gcl{oxRjjcnffv(7?9890mij}erq\``ehllx&=5<>3:cg`wct{Vnnobjjr/hk`41<imnyi~}Pddal``t)ban&=:7>7:cg`wct{Vnnobjjr/hk`(7?8:1j`ao4bdjbrliuieo0nhfnvhmqei+69;o0nhfnvhmqei+6:9o0nhfnvhmqei+6:1o0nhfnvhmqei+6>1o0nhfnvhmqei+6??n0nhfnvhmqei+38m1iieoyinpbh(2?k2hndlxfosco)=b<jlbjzda}am/;<==eagnJ~nfn;ckm`@hsa}si7ogadQc`odab<2cnihl4ioaoqac*992i7d`lltff)471j2ceoa{ke,310g=nfjf~hh#>65`8mkek}mo&=:<n;hl`hpbb%:<27d`lltff)1g<agigyik"45c8mkek}mo&4964ochJjack2yhc}kNrbjLfoe<{je{iKgceN`ig>udgyoGeckAul48wlkwdl20}g9510ag>uwa??;>o#>10a8wuo1=98i!<?6c:qsm337:k':>:m4sqk5154e%8<<o6}i7736g+6?<h0}g9510a)6?e3zzb:8>=b,64e>uwa??;>o#8b:qsm337:k'3;h5|te]okbodW8;=8<<4suf\hjankVediaee58qvc*993<7x}j-0333>stm$;:;:5zsd/25=1<}zo&=?;8;tqf)441?2xi ?9569vw`+6>?=0y~k"1614?pub%8=?:6{|e,142>stm$93:6{|e,662>stm$>=96{|e,76?pub%?<0y~k"8448qvc*0?wKL};l;AB{21<A28o1=v]>0;47>4<6;:k;;?4=a863k5b281e?k4=;%1g>6e<uZl1:94>:010e5152;k28<5\1c850?7=9:9j<:<52`;76>Ua2?>1=7?<3`246?4flk<0_<l56582>454i9=96?okf`9Pb?03280:?>o?7381e`0f3Z;i6;:51;307d6di38h>8o4Sg850?7=9:9j<no52e2f2>U6j3<?6<4>32c3gg<69o8<7^h56582>454i9ii6<<?bb9P5g<1<3;1=>=n0e`95addm2Ym6;:51;307d6cj3;nm=;4S0`921<62898m<<>:3c17g=Tn3<?6<4>32c264<5i;>:7^?m:7695?74;h;n57<;b438Wc<1<3;1=>=n1d;961c212Y:n78;:08276g6mh0:;=9i;Rd921<62898m<kn:0;406=T9k0=87?5121b5`g=90h;?6]i:7695?74;h;nm7?6b078W4d=>=0:6<=<c7c4>7b7mh1Xj78;:08276e1i>09h87:;R3a>32=93;8?n9?a;060d4<[o0=87?5121`35g=:<>i86]>b;47>4<6;:i<<l4=57g3?V`=>=0:6<=<c62b>73c181X=o494;39565d?9k1>::i2:Qe>32=93;8?n9?a;0424c<[8h1:94>:010g2b62;k;=l5\f;47>4<6;:i<h<4=a14b?a03290:6?u\11850?7=9:9j<:<52`;74>h183h=7B=6:19L53<73L9h7>51;394~U683<?6<4>32a4`4<5i9;j7c?l:09a6`<7290>6=ua6282?kc=92E8;7>4$0d94>"6=38?7)?8:19'67<73-8:6l5@1583?J7?291D:?4>{|`6f?6=83:1<v`93;debc`ano1ei7<?0:M03?6<G:h1>vs@1d83?xd013:1<7>50zl57?463go1==>4O2594>"6l3?=7)<?:7d8 75=<11D984?;N41>4}zG831=vsrb6c94?6=83:pb;=5239ma?7782E8;7>4$0f913=#:90<<6*=3;6;?J32291D:?4>{|M2=?7|uth=m7>50;294~h1;39;7ck52:M03?6<,891:85@d;28K34=9rwD=44>{|a0`<7290:6=ua62866>hb2=1D?:4?;%a90<=#;10;7)?<:778K47=82E:>7>4O4694>I1:3;pqB8>:0y~f17=83:1<7>tn719=1=im320C>950:&2e?273-9j69<4O4694>I2;3:0C;<51zL24<6stwvqpxI4783>4<629qX==494;39565d?m;1>l>>b:l2g?7<j==1<7>52;2xj35=92dn6<5@3683?!7a291/=84;5:&23?6<,;81<6*=1;`8K42=82E:47>4O7095~{e<:0;6=4?:1ym26<63go1>6A<7;28 45=<;1Dh7>4O7095~{zj=>1<7>50;2xj35=92dn695@3683?!e=<;1/?54?;%30>14<G8;1<6A>2;28K02=82E=>7?t}N42>4}zutwvqMNL{4a922>fkoimqMNM{1CDU}H:00996A=c;0f?J4d2:90C>?5249L77<5i2E8:7<:;N14>7g<G:h1>85@3b81e>I3:38>7B:<:2f8K1>=:<1D844<d:M64?2d3F??69m4O4c90f=H=k0>96sO@
\ No newline at end of file
diff --git a/spi65.npl b/spi65.npl
index 8001aeb..2b350a0 100644
--- a/spi65.npl
+++ b/spi65.npl
@@ -19,6 +19,7 @@ SIMULATORTIME 0
 DEVGENERATEDSIMULATIONMODEL VHDL
 GENERATEDSIMULATIONMODELTIME 0
 SOURCE SPI6502B1.1.vhd
+SOURCE address_decoder.sch
 DEPASSOC spi6502b SPI6502B.ucf
 [STRATEGY-LIST]
 Normal=True
diff --git a/spi6502b.bld b/spi6502b.bld
index 0c7736a..68992fb 100644
--- a/spi6502b.bld
+++ b/spi6502b.bld
@@ -16,7 +16,7 @@ NGDBUILD Design Results Summary:
   Number of errors:     0
   Number of warnings:   0
 
-Total memory usage is 59352 kilobytes
+Total memory usage is 58712 kilobytes
 
 Writing NGD file "spi6502b.ngd" ...
 
diff --git a/spi6502b.gyd b/spi6502b.gyd
index 731f132..bccfda3 100644
--- a/spi6502b.gyd
+++ b/spi6502b.gyd
@@ -2,16 +2,23 @@ Pin Freeze File:  version G.38
 
 9572XL44PC XC9572XL-10-PC44
 Ncs2 S:PIN18
+a10 S:PIN38
+a8 S:PIN36
+a9 S:PIN37
 cpu_Nphi2 S:PIN5
 cpu_Nres S:PIN19
 cpu_a<0> S:PIN22
 cpu_a<1> S:PIN24
 cpu_rnw S:PIN7
-cs1 S:PIN20
 extclk S:PIN6
+nio_sel S:PIN40
+nio_stb S:PIN43
 spi_int S:PIN42
 spi_miso S:PIN44
-cpu_Nirq S:PIN14
+b10 S:PIN27
+b8 S:PIN25
+b9 S:PIN26
+cpu_Nirq S:PIN39
 cpu_d<0> S:PIN2
 cpu_d<1> S:PIN3
 cpu_d<2> S:PIN4
@@ -23,31 +30,32 @@ cpu_d<7> S:PIN13
 spi_mosi S:PIN35
 spi_sclk S:PIN34
 led S:PIN29
+ng S:PIN20
+noe S:PIN14
 spi_Nsel S:PIN28
 
 
 ;The remaining section of the .gyd file is for documentation purposes only.
 ;It shows where your internal equations were placed in the last successful fit.
 
-PARTITION FB1_2 spidataout<2> spidataout<1> spidataout<0> int_dout<0>
-		 int_dout<1> tmo int_dout<2> slaveinten
-		 frx ece divisor<2> divisor<1>
-		 divisor<0> int_dout<3> cpol int_dout<4>
-		 cpha
-PARTITION FB2_1 EXP6_ int_mosi shifting2 shiftdone
-		 shiftcnt<0> $OpTx$INV$22__$INT spidatain<7> spidatain<6>
-		 spidatain<5> spidatain<4> spidatain<3> spidatain<2>
-		 spidatain<1> spidatain<0> shiftcnt<3> shiftcnt<2>
-		 shiftcnt<1> start_shifting/start_shifting_RSTF__$INT
+PARTITION FB1_1 spidataout<3> spidataout<2> spidataout<1> spidataout<0>
+		 int_dout<0> int_dout<1> tmo int_dout<2>
+		 slaveinten frx ece divisor<2>
+		 divisor<1> divisor<0> int_dout<3> cpol
+		 int_dout<4> cpha
+PARTITION FB2_1 EXP6_ int_mosi shifting2 tc
+		 shiftcnt<0> $OpTx$INV$24__$INT spidatain<7> spidatain<6>
+		 cpu_Nirq_OBUFE spidatain<5> spidatain<4> spidatain<3>
+		 spidatain<2>
+PARTITION FB2_18 start_shifting/start_shifting_RSTF__$INT
 PARTITION FB3_2 int_dout<5>
 PARTITION FB3_5 int_dout<6>
-PARTITION FB3_8 int_dout<7> cpu_Nirq_OBUFE
-
-PARTITION FB4_1 cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST tc start_shifting spidataout<7>
-		 spidataout<6> spidataout<5> spidataout<4> spidataout<3>
-		 ier
-PARTITION FB4_11 slavesel
-PARTITION FB4_14 led_OBUF
-PARTITION FB4_16 EXP7_ int_sclk
-
+PARTITION FB3_8 int_dout<7> noe_OBUF
+PARTITION FB3_15 ng_OBUF
+PARTITION FB3_17 add_dec/XLXN_11 cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
+PARTITION FB4_1 shiftdone b8_OBUF start_shifting spidataout<7>
+		 b9_OBUF spidataout<6> spidataout<5> b10_OBUF
+		 spidataout<4> spidatain<1> slavesel spidatain<0>
+		 shiftcnt<3> led_OBUF shiftcnt<2> shiftcnt<1>
+		 int_sclk ier
 
diff --git a/spi6502b.jed b/spi6502b.jed
index eb99912..8252845 100644
--- a/spi6502b.jed
+++ b/spi6502b.jed
@@ -1,5 +1,5 @@
 Programmer Jedec Bit Map
-Date Extracted: Sat May 06 17:48:01 2017
+Date Extracted: Thu May 11 02:09:28 2017
 
 QF46656*
 QP44*
@@ -42,39 +42,39 @@ N PPMAP 21 6*
 N PPMAP 24 7*
 N PPMAP 26 8*
 N PPMAP 27 9*
-L0000000 00000000 00000000 00000000 00000000*
-L0000032 00000000 00000000 00000000 00000000*
-L0000064 00000000 00000000 00000000 00000000*
-L0000096 01111100 00000000 00000000 01100000*
-L0000128 00000000 00000000 00000000 00000000*
+L0000000 00000000 10000000 00000000 00000000*
+L0000032 10000000 10000000 00000000 00000000*
+L0000064 00000000 10000000 00000000 00000000*
+L0000096 00000000 10000000 00000000 00000000*
+L0000128 00000000 10000000 00000000 00000100*
 L0000160 00000000 00000000 00000000 00000000*
-L0000192 00000000 00000000 00000000 00000000*
-L0000224 00000000 00000000 00000000 00010000*
-L0000256 10011000 00000000 00000000 01100000*
-L0000288 000000 000000 000000 000000*
-L0000312 000000 000000 000000 000000*
-L0000336 000000 000000 000000 100000*
-L0000360 000000 000000 000000 000000*
-L0000384 101101 000000 000000 011000*
+L0000192 00000000 00000000 00000000 00000100*
+L0000224 00000000 10000000 00000000 00000000*
+L0000256 00000000 00000000 00000000 00000000*
+L0000288 000000 100000 000000 000000*
+L0000312 000000 000001 000000 000000*
+L0000336 000000 100000 000000 000000*
+L0000360 000000 100000 000000 000000*
+L0000384 000000 000000 000000 000000*
 L0000408 000000 000000 000000 000000*
 L0000432 00000000 00000000 00000000 00000000*
 L0000464 00000000 00000000 00000000 00000000*
-L0000496 00000000 00000000 00000000 00000000*
-L0000528 00000000 00000000 00000000 00000000*
+L0000496 10000000 00000000 00000000 00000000*
+L0000528 00000000 01000000 00000000 00000000*
 L0000560 00000000 00000000 00000000 00000000*
-L0000592 01100100 00000000 11100000 00000000*
-L0000624 01100100 00000000 11100000 00000000*
-L0000656 01100100 00000000 11100000 00000000*
-L0000688 01100100 00000000 10000000 00000000*
-L0000720 010001 000000 000000 000000*
-L0000744 010010 000000 000000 000000*
-L0000768 010010 000000 000000 000000*
-L0000792 010010 000000 000000 000000*
-L0000816 010000 000000 000000 000000*
+L0000592 00000000 00000000 11100000 00000000*
+L0000624 00000000 00000000 11100000 00000000*
+L0000656 00000000 00000000 11100000 00000000*
+L0000688 00000000 00000000 10000000 00000000*
+L0000720 000000 000000 000000 000000*
+L0000744 000000 000000 000000 000000*
+L0000768 000000 000000 000000 000000*
+L0000792 000000 000000 000000 000000*
+L0000816 000000 000000 000000 000000*
 L0000840 000000 000000 000000 000000*
 L0000864 00000000 00000000 00000000 00000000*
-L0000896 00000000 10000000 00000000 00000000*
-L0000928 00000000 00000000 00000000 00000000*
+L0000896 00000000 00000000 00000000 00000000*
+L0000928 00000010 00000000 00000000 00000000*
 L0000960 00000000 00000000 00000000 00000000*
 L0000992 00000000 00000000 00000000 00000000*
 L0001024 00000000 00000000 00000000 00000000*
@@ -87,12 +87,12 @@ L0001200 000000 000000 000000 000000*
 L0001224 000000 000000 000000 000000*
 L0001248 000000 000000 000000 000000*
 L0001272 000000 000000 000000 000000*
-L0001296 00000000 00000000 00000000 10000000*
+L0001296 00000000 00000000 00000000 00000000*
 L0001328 00000000 00000000 00000000 00000000*
 L0001360 00000000 00000000 00000000 00000000*
 L0001392 00000000 00000000 00000000 00000000*
 L0001424 00000000 00000000 00000000 00000000*
-L0001456 00000000 00000000 00100000 00000000*
+L0001456 00000000 00000000 00000000 00000000*
 L0001488 00000000 00000000 00000000 00000000*
 L0001520 10000000 00000000 00000000 00000000*
 L0001552 00000000 00000000 00000000 00000000*
@@ -103,7 +103,7 @@ L0001656 000000 000000 000000 000000*
 L0001680 000000 000000 000000 000000*
 L0001704 000000 000000 000000 000000*
 L0001728 00000000 00000000 00000000 00000000*
-L0001760 00000000 00000000 00000000 00000000*
+L0001760 00000000 00000000 00000000 00001000*
 L0001792 00000000 00000000 00000000 00000000*
 L0001824 00000000 00000000 00000000 00000000*
 L0001856 00000000 00000000 00000000 00000000*
@@ -113,28 +113,28 @@ L0001952 00000000 00000000 00000000 00000000*
 L0001984 00000000 00000000 00000000 00000000*
 L0002016 000000 000000 000000 000000*
 L0002040 000000 010000 000000 000000*
-L0002064 000000 000000 000000 100000*
+L0002064 100000 000000 000000 000010*
 L0002088 000000 000000 000000 000000*
-L0002112 000000 000000 000000 100000*
+L0002112 000000 000000 000000 000000*
 L0002136 000000 000000 000000 000000*
 L0002160 00000000 00000000 00000000 00000000*
-L0002192 00000000 00000000 00000000 00000000*
+L0002192 00000000 00000000 00000000 00000100*
 L0002224 00000000 00000000 00000000 00000000*
-L0002256 00000000 00000000 00000000 00000000*
-L0002288 00000000 00000000 00000000 00000000*
-L0002320 00000000 00000000 00000000 00000000*
-L0002352 00000000 00000000 00000000 00000000*
-L0002384 00000000 00000000 10000000 00000000*
+L0002256 00000000 00000000 00000000 00011100*
+L0002288 00000000 00000000 00000000 00000100*
+L0002320 00000000 00000000 10000000 00000000*
+L0002352 00000000 00000000 00000000 00000100*
+L0002384 00000000 00000000 00000000 00000000*
 L0002416 00000000 00000000 00000000 00000000*
 L0002448 000000 000000 000000 000000*
 L0002472 000000 000000 000000 000000*
 L0002496 000000 100000 000000 000000*
-L0002520 000000 000000 000000 000000*
-L0002544 000000 000000 000000 000000*
+L0002520 100000 000000 000000 000000*
+L0002544 000000 000000 000000 000110*
 L0002568 000000 000000 000000 000000*
 L0002592 00000010 00000000 00000000 00000000*
-L0002624 01000011 00000000 00000000 01000000*
-L0002656 00000000 00000000 00000000 00000000*
+L0002624 00000011 00000000 00000000 01000000*
+L0002656 01000000 00000000 00000000 00000000*
 L0002688 00000011 00000000 00000000 00000000*
 L0002720 00000010 10000000 00000000 00000000*
 L0002752 00000011 00000000 00000000 00000000*
@@ -148,119 +148,119 @@ L0002952 000000 000000 000000 000000*
 L0002976 000000 000000 000000 000000*
 L0003000 000000 000000 000000 000000*
 L0003024 00000010 00000000 00000000 00000000*
-L0003056 00000001 00000000 00000000 00000000*
-L0003088 01000001 00000000 00000000 01000000*
+L0003056 01000001 00000000 00000000 00000000*
+L0003088 00000001 00000000 00000000 01000000*
 L0003120 00000010 00000000 00000000 00000000*
 L0003152 00000000 00000000 00000000 00000000*
-L0003184 00000011 00000000 00000000 00000000*
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@@ -348,25 +348,25 @@ L0008704 00000001 00000000 00000000 00000000*
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@@ -1077,8 +1077,8 @@ L0029712 000000 000000 000000 000000*
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@@ -1092,11 +1092,11 @@ L0030144 000000 000000 000000 000000*
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 L0030400 00000000 00000000 00000000 00000000*
 L0030432 00000000 00000000 00000000 00000000*
 L0030464 00000000 00000000 00000000 00000000*
@@ -1107,11 +1107,11 @@ L0030576 000000 000000 000000 000000*
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 L0030832 00000000 00000000 00000000 00000000*
 L0030864 00000000 00000000 00000000 00000000*
 L0030896 00000000 00000000 00000000 00000000*
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@@ -1164,69 +1164,69 @@ L0032224 00000000 00000000 00000000 00000000*
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 L0035456 00000000 00000000 00000000 00000000*
@@ -1295,16 +1295,16 @@ L0035984 00000000 00000000 00000000 00000000*
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 L0036080 00000000 00000000 00000000 00000000*
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 L0036416 00000000 00000000 00000000 00000000*
 L0036448 00000000 00000000 00000000 00000000*
@@ -1313,48 +1313,48 @@ L0036512 00000000 00000000 00000000 00000000*
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 L0039104 00000000 00000000 00000000 00000000*
 L0039136 00000000 00000000 00000000 00000000*
 L0039168 000000 000000 000000 000000*
-L0039192 000000 000000 000000 000000*
+L0039192 000000 000000 001000 000000*
 L0039216 000000 000000 000000 000000*
 L0039240 000000 000000 000000 000000*
 L0039264 000000 000000 000000 000000*
@@ -1417,71 +1417,71 @@ L0039504 00000000 00000000 00000000 00000000*
 L0039536 00000100 00000000 00000000 00000000*
 L0039568 00000000 00000000 00000000 00000000*
 L0039600 000000 000000 000000 000000*
-L0039624 000000 000000 000000 000000*
+L0039624 000000 000000 000010 000000*
 L0039648 000000 000000 000000 000000*
 L0039672 000000 000000 000000 000000*
 L0039696 000000 000000 000000 000000*
 L0039720 000000 000000 000000 000000*
-L0039744 00000000 10000000 00000000 00000000*
+L0039744 00000000 00000000 00000000 00000000*
 L0039776 00000000 00000000 00000000 00000000*
-L0039808 00000000 00000000 00000000 00000000*
+L0039808 00000000 00000000 00000000 10011100*
 L0039840 00000000 00000000 00000000 00000000*
 L0039872 00000000 00000000 00000000 00000000*
 L0039904 00000000 00000000 00000000 00000000*
 L0039936 00000000 00000000 00000000 00000000*
-L0039968 00000000 00000000 00000000 00000000*
-L0040000 00000000 00000000 00000000 00000000*
+L0039968 00000000 10000000 00000000 00000100*
+L0040000 00000000 00000000 00000000 00010100*
 L0040032 000000 000000 000000 000000*
 L0040056 000000 000000 000000 000000*
 L0040080 000000 000000 000000 000000*
-L0040104 000000 000000 000000 000000*
+L0040104 000000 000000 000000 000111*
 L0040128 000000 000000 000000 000000*
 L0040152 000000 000000 000000 000000*
 L0040176 00000000 00000000 00000000 00000000*
 L0040208 00000000 00000000 00000000 00000000*
 L0040240 00000000 00000000 00000000 00000000*
-L0040272 00000000 00000000 00000000 00000000*
-L0040304 00000000 00000000 00000000 00000000*
+L0040272 00000000 00000000 00000000 01100000*
+L0040304 00000000 00000000 00000000 00000100*
 L0040336 00000000 00000000 00000000 00000000*
-L0040368 00000000 00000000 00000000 00000000*
+L0040368 00000000 00000000 00000000 00000100*
 L0040400 00000000 00000000 00000000 00000000*
 L0040432 00000000 00000000 00000000 00000000*
 L0040464 000000 000000 000000 000000*
 L0040488 000000 000000 000000 000000*
 L0040512 000000 000000 000000 000000*
 L0040536 000000 000000 000000 000000*
-L0040560 000000 000000 000000 000000*
+L0040560 000000 000000 000000 011000*
 L0040584 000000 000000 000000 000000*
 L0040608 00000000 00000000 00000000 00000000*
 L0040640 00000000 00000000 00000000 00000000*
 L0040672 00000000 00000000 00000000 00000000*
 L0040704 00000000 00000000 00000000 00000000*
 L0040736 00000000 00000000 00000000 00000000*
-L0040768 00000000 00000000 00000000 00000000*
-L0040800 00000000 00000000 00000000 00000000*
-L0040832 00000000 00000000 00000000 00000000*
-L0040864 00000000 00000000 00000000 00000000*
-L0040896 000000 000000 000000 000000*
-L0040920 000000 000000 000000 000000*
-L0040944 000000 000000 000000 000000*
-L0040968 000000 000000 000000 000000*
-L0040992 000000 000000 000000 000000*
+L0040768 01100100 00000000 00000000 00000000*
+L0040800 01100100 00000000 00000000 00000000*
+L0040832 01100100 00000000 00000000 00000000*
+L0040864 01100100 00000000 00000000 00000000*
+L0040896 010001 000000 000000 000000*
+L0040920 010010 000000 000000 000000*
+L0040944 010010 000000 000000 000001*
+L0040968 010010 000000 000000 000000*
+L0040992 010000 000000 000000 000000*
 L0041016 000000 000000 000000 000000*
-L0041040 00000000 00000000 00000000 00000000*
+L0041040 11111100 01000000 00000000 00000000*
 L0041072 00000000 00000000 00000000 00000000*
 L0041104 00000000 00000000 00000000 00000000*
 L0041136 00000000 00000000 00000000 00000000*
 L0041168 00000000 00000000 00000000 00000000*
-L0041200 00000000 00000000 00000000 00000000*
+L0041200 10011000 00000000 00000000 00000000*
 L0041232 00000000 00000000 00000000 00000000*
 L0041264 00000000 00000000 00000000 00000000*
 L0041296 00000000 00000000 00000000 00000000*
 L0041328 000000 000000 000000 000000*
-L0041352 000000 000000 000000 000000*
+L0041352 101101 000000 000000 000000*
 L0041376 000000 000000 000000 000000*
 L0041400 000000 000000 000000 000000*
 L0041424 000000 000000 000000 000000*
-L0041448 000000 000000 000000 000000*
+L0041448 000000 000000 000000 000001*
 L0041472 00000000 00000000 00000000 00000000*
 L0041504 00000000 00000000 00000000 00000000*
 L0041536 00000000 00000000 00000000 00000000*
@@ -1492,29 +1492,29 @@ L0041664 00000000 00000000 00000000 00000000*
 L0041696 00000000 00000000 00000000 00000000*
 L0041728 00000000 00000000 00000000 00000000*
 L0041760 000000 000000 000000 000000*
-L0041784 000000 000000 000000 000000*
-L0041808 000000 010000 000000 000000*
+L0041784 000000 010000 000000 000000*
+L0041808 000000 000000 000000 000000*
 L0041832 000000 000000 000000 000000*
 L0041856 000000 000000 000000 000000*
 L0041880 000000 000000 000000 000000*
-L0041904 00000000 00000000 00000000 00000000*
-L0041936 00000000 00000000 00000000 00000000*
-L0041968 00000000 00000000 00000000 00000000*
-L0042000 00000000 00000000 00000000 00000000*
-L0042032 00000000 00000000 00000000 00000000*
+L0041904 00000000 10000000 00000000 00000000*
+L0041936 00000000 10000000 00000000 00000000*
+L0041968 00000000 10000000 00000000 00000000*
+L0042000 00000000 10111000 00000000 00000000*
+L0042032 00000000 10000000 00000000 00000000*
 L0042064 00000000 00000000 00000000 00000000*
-L0042096 00000000 00000000 00000000 00000000*
-L0042128 00000000 00000000 00000000 00000000*
-L0042160 00000000 00000000 00000000 00000000*
-L0042192 000000 000000 000000 000000*
+L0042096 00000000 01000000 00000000 00000000*
+L0042128 00000000 10000000 00000000 00000000*
+L0042160 00000000 00110000 00000000 00000000*
+L0042192 000000 100000 000000 000000*
 L0042216 000000 000000 000000 000000*
 L0042240 000000 000000 000000 000000*
-L0042264 000000 000000 000000 000000*
-L0042288 000000 000000 000000 000000*
+L0042264 000000 100000 000000 000000*
+L0042288 000000 000100 000000 000000*
 L0042312 000000 000000 000000 000000*
 L0042336 00000000 00000000 00000000 00000000*
 L0042368 00000000 00000000 00000000 00000000*
-L0042400 00000000 00000000 00000000 00000000*
+L0042400 00000000 10000000 00000000 00000000*
 L0042432 00000000 00000000 00000000 00000000*
 L0042464 00000000 00000000 00000000 00000000*
 L0042496 00000000 00000000 00000000 00000000*
@@ -1524,7 +1524,7 @@ L0042592 00000000 00000000 00000000 00000000*
 L0042624 000000 000000 000000 000000*
 L0042648 000000 000000 000000 000000*
 L0042672 000000 000000 000000 000000*
-L0042696 000000 000000 000000 100000*
+L0042696 000000 000000 000000 000000*
 L0042720 000000 000000 000000 000000*
 L0042744 000000 000000 000000 000000*
 L0042768 00000000 00000000 00000000 00000000*
@@ -1548,12 +1548,12 @@ L0043264 00000000 00000000 00000000 00000000*
 L0043296 00000000 00000000 00000000 00000000*
 L0043328 00000000 00000000 00000000 00000000*
 L0043360 00000000 00000000 00000000 00000000*
-L0043392 00010000 00000000 00000000 00000000*
+L0043392 00000000 00000000 00000000 00000000*
 L0043424 00000000 00000000 00000000 00000000*
 L0043456 00000000 00000000 00000000 00000000*
 L0043488 000000 000000 000000 000000*
 L0043512 000000 000000 000000 000000*
-L0043536 000000 000000 000000 000000*
+L0043536 000000 000000 001000 000000*
 L0043560 000000 010000 000000 000000*
 L0043584 000000 000000 000000 000000*
 L0043608 000000 000000 000000 000000*
@@ -1562,48 +1562,48 @@ L0043664 00000000 00000000 00000000 00000000*
 L0043696 00000000 00000000 00000000 00000000*
 L0043728 00000000 00000000 00000000 00000000*
 L0043760 00000000 00000000 00000000 00000000*
-L0043792 00100000 00000000 00000000 00000000*
+L0043792 00000000 00000000 00000000 11100000*
 L0043824 00000000 00000000 00000000 00000000*
 L0043856 00000000 00000000 00000000 00000000*
 L0043888 00000000 00000000 00000000 00000000*
-L0043920 000100 000000 000000 000000*
-L0043944 000000 000000 000000 000000*
+L0043920 000000 000000 000000 000000*
+L0043944 000000 000000 000010 000000*
 L0043968 000000 010000 000000 000000*
-L0043992 000000 000000 000000 000000*
+L0043992 000010 000000 000000 000000*
 L0044016 000000 000000 000000 000000*
 L0044040 000000 000000 000000 000000*
 L0044064 00000000 00000000 00000000 00000000*
 L0044096 00000000 00000000 00000000 00000000*
-L0044128 00000000 00000000 00000000 00000000*
-L0044160 00000000 00000000 00000000 00000000*
-L0044192 00000000 00000000 00000000 00000000*
+L0044128 00000000 10000000 00000000 00000000*
+L0044160 00000000 10000000 00000000 00000000*
+L0044192 00000000 10000000 00000000 00000000*
 L0044224 00000000 00000000 00000000 00000000*
 L0044256 00000000 00000000 00000000 00000000*
 L0044288 00000000 00000000 00000000 00000000*
 L0044320 00000000 00000000 00000000 00000000*
-L0044352 000000 000000 000000 000000*
+L0044352 000000 100000 000000 000000*
 L0044376 000000 000000 000000 000000*
 L0044400 000000 000000 000000 000000*
-L0044424 000000 010000 000000 000000*
+L0044424 000000 000000 000000 000000*
 L0044448 000000 000000 000000 000000*
 L0044472 000000 000000 000000 000000*
-L0044496 00000000 00000000 00000000 00000000*
-L0044528 00000000 00000000 00000000 00000000*
+L0044496 00000000 10000000 00000000 00000000*
+L0044528 00000000 10000000 00000000 00000000*
 L0044560 00000000 00000000 00000000 00000000*
 L0044592 00000000 00000000 00000000 00000000*
 L0044624 00000000 00000000 00000000 00000000*
-L0044656 01100100 00000000 11100000 00000000*
-L0044688 01100100 00000000 11100000 00000000*
-L0044720 01100100 00000000 11100000 00000000*
-L0044752 01100100 00000000 10000000 00000000*
-L0044784 010001 000000 000000 000000*
-L0044808 010010 000000 000000 000000*
-L0044832 010010 000000 000000 000000*
-L0044856 010010 000000 000000 000000*
-L0044880 010000 000000 000000 000000*
+L0044656 00000000 00000000 00000000 00000000*
+L0044688 00000000 00000000 00000000 00000000*
+L0044720 00000000 10000000 00000000 00000000*
+L0044752 00000000 00000000 00000000 00000000*
+L0044784 000000 000000 000000 000000*
+L0044808 000000 000000 000000 000000*
+L0044832 000000 000000 000000 000000*
+L0044856 000000 100000 000000 000000*
+L0044880 000000 000000 000000 000000*
 L0044904 000000 000000 000000 000000*
 L0044928 00000000 00000000 00000000 00000000*
-L0044960 00000000 00000000 00000000 00000000*
+L0044960 00000100 00000000 00000000 00000000*
 L0044992 00000000 00000000 00000000 00000000*
 L0045024 00000000 00000000 00000000 00000000*
 L0045056 00000000 00000000 00000000 00000000*
@@ -1621,46 +1621,46 @@ L0045360 00000000 00000000 00000000 00000000*
 L0045392 00000000 00000000 00000000 00000000*
 L0045424 00000000 00000000 00000000 00000000*
 L0045456 00000000 00000000 00000000 00000000*
-L0045488 00000000 00000000 00000000 00000000*
+L0045488 00000100 00000000 00000000 00000000*
 L0045520 00000000 00000000 00000000 00000000*
 L0045552 00000000 00000000 00000000 00000000*
 L0045584 00000000 00000000 00000000 00000000*
-L0045616 00000000 00000000 00000000 00000000*
+L0045616 00000000 00000000 10000000 00000000*
 L0045648 000000 000000 000000 000000*
-L0045672 000000 000000 000000 000000*
+L0045672 010000 000000 000000 000000*
 L0045696 000000 000000 000000 000000*
 L0045720 000000 000000 000000 000000*
 L0045744 000000 000000 000000 000000*
 L0045768 000000 000000 000000 000000*
 L0045792 00000000 00000000 00000000 00000000*
-L0045824 00100000 00000000 00000000 00000000*
+L0045824 00000000 00000000 00000000 00000000*
 L0045856 00000000 00000000 00000000 00000000*
 L0045888 00000000 00000000 00000000 00000000*
 L0045920 00000000 00000000 00000000 00000000*
 L0045952 00000000 00000000 00000000 00000000*
 L0045984 00000000 00000000 00000000 00000000*
-L0046016 00000000 00000000 00000000 00100000*
+L0046016 00000000 00000000 00000000 00000000*
 L0046048 00000000 00000000 00000000 00000000*
 L0046080 000000 000000 000000 000000*
 L0046104 000000 000000 000000 000000*
 L0046128 000000 000000 000000 000000*
-L0046152 000000 000000 000000 000000*
+L0046152 000000 010000 000000 100000*
 L0046176 000000 000000 000000 000000*
 L0046200 000000 000000 000000 000000*
 L0046224 00000000 00000000 00000000 00000000*
 L0046256 00000000 00000000 00000000 00000000*
 L0046288 00000000 00000000 00000000 00000000*
 L0046320 00000000 00000000 00000000 00000000*
-L0046352 00100000 00000000 00000000 00000000*
-L0046384 00000000 00000000 00000000 00000000*
-L0046416 00000000 00000000 00000000 00100000*
-L0046448 00000000 00000000 00000000 00000000*
-L0046480 00000000 00000000 00000000 00000000*
-L0046512 000000 000000 000000 000000*
-L0046536 000000 000000 000000 000000*
-L0046560 000000 000000 000000 000000*
-L0046584 000000 000000 000000 000000*
-L0046608 000000 000000 000000 000000*
+L0046352 00000000 00000000 00000000 00000000*
+L0046384 01100100 00000000 11100000 00000000*
+L0046416 01100100 00000000 11100000 00000000*
+L0046448 01100100 00000000 11100000 00000000*
+L0046480 01100100 00000000 10000000 00000000*
+L0046512 010001 000000 000000 000000*
+L0046536 010010 000000 000000 000000*
+L0046560 010010 000000 000000 000000*
+L0046584 010010 000000 000000 000000*
+L0046608 010000 000000 000000 000000*
 L0046632 000000 000000 000000 000000*
-C6FA2*
-190B
+C9205*
+18E9
diff --git a/spi6502b.mfd b/spi6502b.mfd
index 5dee314..a1c2f4f 100644
--- a/spi6502b.mfd
+++ b/spi6502b.mfd
@@ -2,276 +2,276 @@ MDF Database:  version 1.0
 MDF_INFO | spi6502b | XC9572XL-10-PC44
 MACROCELL | 1 | 1 | int_mosi
 ATTRIBUTES | 8652706 | 0
-INPUTS | 12 | shiftcnt<3>  | shiftcnt<2>  | shiftcnt<1>  | shiftdone  | spidataout<5>  | shifting2  | spidataout<1>  | EXP6_.EXP  | shifting2.EXP  | $OpTx$INV$22__$INT  | cpu_Nres  | tmo
-INPUTMC | 11 | 1 | 14 | 1 | 15 | 1 | 16 | 1 | 3 | 3 | 5 | 1 | 2 | 0 | 2 | 1 | 0 | 1 | 2 | 1 | 5 | 0 | 6
+INPUTS | 12 | shiftcnt<3>  | shiftcnt<2>  | shiftcnt<1>  | shiftdone  | spidataout<4>  | shifting2  | spidataout<0>  | EXP6_.EXP  | shifting2.EXP  | $OpTx$INV$24__$INT  | cpu_Nres  | tmo
+INPUTMC | 11 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 3 | 8 | 1 | 2 | 0 | 3 | 1 | 0 | 1 | 2 | 1 | 5 | 0 | 6
 INPUTP | 1 | 49
 IMPORTS | 2 | 1 | 0 | 1 | 2
 EQ | 21 | 
-   !spi_mosi.D = shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & 
-	!shiftdone & !spidataout<1> & shifting2
-	# !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & 
-	!shiftdone & !spidataout<5> & shifting2
-;Imported pterms FB2_1
-	# shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & 
+   !spi_mosi.D = shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & 
 	!shiftdone & !spidataout<0> & shifting2
+	# !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & 
+	!shiftdone & !spidataout<4> & shifting2
+;Imported pterms FB2_1
 	# shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & 
 	!shiftdone & !spidataout<2> & shifting2
 	# shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & 
 	!shiftdone & !spidataout<3> & shifting2
-	# !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & 
-	!shiftdone & !spidataout<4> & shifting2
+	# !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & 
+	!shiftdone & !spidataout<5> & shifting2
+	# !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & 
+	!shiftdone & !spidataout<6> & shifting2
 	# !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & 
 	!shiftdone & !spidataout<7> & shifting2
 ;Imported pterms FB2_3
-	# !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & 
-	!shiftdone & !spidataout<6> & shifting2;
-   spi_mosi.CLK = !$OpTx$INV$22__$INT;
+	# shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & 
+	!shiftdone & !spidataout<1> & shifting2;
+   spi_mosi.CLK = !$OpTx$INV$24__$INT;
    spi_mosi.AP = !cpu_Nres;
    spi_mosi.OE = !tmo;
 
 MACROCELL | 3 | 10 | slavesel
 ATTRIBUTES | 4588514 | 0
-OUTPUTMC | 4 | 3 | 10 | 1 | 13 | 0 | 4 | 3 | 13
-INPUTS | 8 | spi_Nsel  | cpu_a<1>  | cpu_a<0>  | cpu_d<0>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+OUTPUTMC | 4 | 3 | 10 | 3 | 11 | 0 | 4 | 3 | 13
+INPUTS | 7 | spi_Nsel  | cpu_a<1>  | cpu_a<0>  | cpu_d<0>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 3 | 10
-INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24
 EQ | 5 | 
    spi_Nsel.T = spi_Nsel & cpu_a<1> & cpu_a<0> & !cpu_d<0>.PIN
 	# !spi_Nsel & cpu_a<1> & cpu_a<0> & cpu_d<0>.PIN;
-   !spi_Nsel.CLK = cs1 & !Ncs2;
+   spi_Nsel.CLK = Ncs2;
    spi_Nsel.AP = !cpu_Nres;
    spi_Nsel.CE = !cpu_rnw;
 
 MACROCELL | 0 | 15 | cpol
 ATTRIBUTES | 4326256 | 0
 OUTPUTMC | 3 | 0 | 15 | 3 | 16 | 0 | 5
-INPUTS | 8 | cpol  | cpu_a<1>  | cpu_a<0>  | cpu_d<1>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | cpol  | cpu_a<1>  | cpu_a<0>  | cpu_d<1>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 15
-INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24
 EQ | 5 | 
    cpol.T = cpol & !cpu_a<1> & cpu_a<0> & !cpu_d<1>.PIN
 	# !cpol & !cpu_a<1> & cpu_a<0> & cpu_d<1>.PIN;
-   !cpol.CLK = cs1 & !Ncs2;
+   cpol.CLK = Ncs2;
    cpol.AR = !cpu_Nres;
    cpol.CE = !cpu_rnw;
 
 MACROCELL | 0 | 10 | ece
 ATTRIBUTES | 4326256 | 0
 OUTPUTMC | 3 | 0 | 10 | 0 | 7 | 1 | 5
-INPUTS | 8 | ece  | cpu_a<1>  | cpu_a<0>  | cpu_d<2>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | ece  | cpu_a<1>  | cpu_a<0>  | cpu_d<2>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 10
-INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24
 EQ | 5 | 
    ece.T = ece & !cpu_a<1> & cpu_a<0> & !cpu_d<2>.PIN
 	# !ece & !cpu_a<1> & cpu_a<0> & cpu_d<2>.PIN;
-   !ece.CLK = cs1 & !Ncs2;
+   ece.CLK = Ncs2;
    ece.AR = !cpu_Nres;
    ece.CE = !cpu_rnw;
 
 MACROCELL | 0 | 17 | cpha
 ATTRIBUTES | 4326256 | 0
 OUTPUTMC | 4 | 0 | 17 | 3 | 16 | 0 | 4 | 3 | 15
-INPUTS | 8 | cpha  | cpu_a<1>  | cpu_a<0>  | cpu_d<0>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | cpha  | cpu_a<1>  | cpu_a<0>  | cpu_d<0>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 17
-INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24
 EQ | 5 | 
    cpha.T = cpha & !cpu_a<1> & cpu_a<0> & !cpu_d<0>.PIN
 	# !cpha & !cpu_a<1> & cpu_a<0> & cpu_d<0>.PIN;
-   !cpha.CLK = cs1 & !Ncs2;
+   cpha.CLK = Ncs2;
    cpha.AR = !cpu_Nres;
    cpha.CE = !cpu_rnw;
 
 MACROCELL | 0 | 9 | frx
 ATTRIBUTES | 4326256 | 0
 OUTPUTMC | 3 | 0 | 9 | 3 | 2 | 0 | 16
-INPUTS | 8 | frx  | cpu_a<1>  | cpu_a<0>  | cpu_d<4>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | frx  | cpu_a<1>  | cpu_a<0>  | cpu_d<4>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 9
-INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24
 EQ | 5 | 
    frx.T = frx & !cpu_a<1> & cpu_a<0> & !cpu_d<4>.PIN
 	# !frx & !cpu_a<1> & cpu_a<0> & cpu_d<4>.PIN;
-   !frx.CLK = cs1 & !Ncs2;
+   frx.CLK = Ncs2;
    frx.AR = !cpu_Nres;
    frx.CE = !cpu_rnw;
 
-MACROCELL | 3 | 8 | ier
+MACROCELL | 3 | 17 | ier
 ATTRIBUTES | 4326256 | 0
-OUTPUTMC | 3 | 3 | 8 | 2 | 4 | 3 | 0
-INPUTS | 8 | ier  | cpu_a<1>  | cpu_a<0>  | cpu_d<6>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
-INPUTMC | 1 | 3 | 8
-INPUTP | 7 | 59 | 52 | 31 | 50 | 46 | 49 | 24
+OUTPUTMC | 3 | 3 | 17 | 2 | 4 | 2 | 17
+INPUTS | 7 | ier  | cpu_a<1>  | cpu_a<0>  | cpu_d<6>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTMC | 1 | 3 | 17
+INPUTP | 6 | 59 | 52 | 31 | 46 | 49 | 24
 EQ | 5 | 
    ier.T = ier & !cpu_a<1> & cpu_a<0> & !cpu_d<6>.PIN
 	# !ier & !cpu_a<1> & cpu_a<0> & cpu_d<6>.PIN;
-   !ier.CLK = cs1 & !Ncs2;
+   ier.CLK = Ncs2;
    ier.AR = !cpu_Nres;
    ier.CE = !cpu_rnw;
 
 MACROCELL | 0 | 8 | slaveinten
 ATTRIBUTES | 4326256 | 0
-OUTPUTMC | 3 | 0 | 8 | 0 | 16 | 3 | 0
-INPUTS | 8 | slaveinten  | cpu_a<1>  | cpu_a<0>  | cpu_d<4>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+OUTPUTMC | 3 | 0 | 8 | 0 | 16 | 2 | 17
+INPUTS | 7 | slaveinten  | cpu_a<1>  | cpu_a<0>  | cpu_d<4>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 8
-INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24
 EQ | 5 | 
    slaveinten.T = slaveinten & cpu_a<1> & cpu_a<0> & !cpu_d<4>.PIN
 	# !slaveinten & cpu_a<1> & cpu_a<0> & cpu_d<4>.PIN;
-   !slaveinten.CLK = cs1 & !Ncs2;
+   slaveinten.CLK = Ncs2;
    slaveinten.AR = !cpu_Nres;
    slaveinten.CE = !cpu_rnw;
 
 MACROCELL | 0 | 6 | tmo
 ATTRIBUTES | 4326256 | 0
 OUTPUTMC | 3 | 1 | 1 | 0 | 6 | 0 | 14
-INPUTS | 8 | tmo  | cpu_a<1>  | cpu_a<0>  | cpu_d<3>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | tmo  | cpu_a<1>  | cpu_a<0>  | cpu_d<3>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 6
-INPUTP | 7 | 59 | 52 | 26 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 26 | 46 | 49 | 24
 EQ | 5 | 
    tmo.T = tmo & !cpu_a<1> & cpu_a<0> & !cpu_d<3>.PIN
 	# !tmo & !cpu_a<1> & cpu_a<0> & cpu_d<3>.PIN;
-   !tmo.CLK = cs1 & !Ncs2;
+   tmo.CLK = Ncs2;
    tmo.AR = !cpu_Nres;
    tmo.CE = !cpu_rnw;
 
 MACROCELL | 0 | 13 | divisor<0>
 ATTRIBUTES | 4326256 | 0
 OUTPUTMC | 2 | 0 | 13 | 0 | 4
-INPUTS | 8 | divisor<0>  | cpu_a<1>  | cpu_a<0>  | cpu_d<0>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | divisor<0>  | cpu_a<1>  | cpu_a<0>  | cpu_d<0>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 13
-INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24
 EQ | 5 | 
    divisor<0>.T = divisor<0> & cpu_a<1> & !cpu_a<0> & !cpu_d<0>.PIN
 	# !divisor<0> & cpu_a<1> & !cpu_a<0> & cpu_d<0>.PIN;
-   !divisor<0>.CLK = cs1 & !Ncs2;
+   divisor<0>.CLK = Ncs2;
    divisor<0>.AR = !cpu_Nres;
    divisor<0>.CE = !cpu_rnw;
 
 MACROCELL | 0 | 12 | divisor<1>
 ATTRIBUTES | 4326256 | 0
 OUTPUTMC | 2 | 0 | 12 | 0 | 5
-INPUTS | 8 | divisor<1>  | cpu_a<1>  | cpu_a<0>  | cpu_d<1>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | divisor<1>  | cpu_a<1>  | cpu_a<0>  | cpu_d<1>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 12
-INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24
 EQ | 5 | 
    divisor<1>.T = divisor<1> & cpu_a<1> & !cpu_a<0> & !cpu_d<1>.PIN
 	# !divisor<1> & cpu_a<1> & !cpu_a<0> & cpu_d<1>.PIN;
-   !divisor<1>.CLK = cs1 & !Ncs2;
+   divisor<1>.CLK = Ncs2;
    divisor<1>.AR = !cpu_Nres;
    divisor<1>.CE = !cpu_rnw;
 
 MACROCELL | 0 | 11 | divisor<2>
 ATTRIBUTES | 4326256 | 0
 OUTPUTMC | 2 | 0 | 11 | 0 | 7
-INPUTS | 8 | divisor<2>  | cpu_a<1>  | cpu_a<0>  | cpu_d<2>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | divisor<2>  | cpu_a<1>  | cpu_a<0>  | cpu_d<2>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 11
-INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24
 EQ | 5 | 
    divisor<2>.T = divisor<2> & cpu_a<1> & !cpu_a<0> & !cpu_d<2>.PIN
 	# !divisor<2> & cpu_a<1> & !cpu_a<0> & cpu_d<2>.PIN;
-   !divisor<2>.CLK = cs1 & !Ncs2;
+   divisor<2>.CLK = Ncs2;
    divisor<2>.AR = !cpu_Nres;
    divisor<2>.CE = !cpu_rnw;
 
-MACROCELL | 1 | 13 | spidatain<0>
+MACROCELL | 3 | 11 | spidatain<0>
 ATTRIBUTES | 8520560 | 0
-OUTPUTMC | 2 | 1 | 12 | 0 | 4
-INPUTS | 6 | spi_Nsel  | spi_miso  | $OpTx$INV$22__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
+OUTPUTMC | 2 | 3 | 9 | 0 | 4
+INPUTS | 6 | spi_Nsel  | spi_miso  | $OpTx$INV$24__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
 INPUTMC | 4 | 3 | 10 | 1 | 5 | 1 | 4 | 1 | 2
 INPUTP | 2 | 10 | 49
 EQ | 4 | 
    spidatain<0>.D = !spi_Nsel & spi_miso;
-   spidatain<0>.CLK = !$OpTx$INV$22__$INT;
+   spidatain<0>.CLK = !$OpTx$INV$24__$INT;
    spidatain<0>.AR = !cpu_Nres;
    spidatain<0>.CE = shiftcnt<0> & shifting2;
 
-MACROCELL | 1 | 12 | spidatain<1>
+MACROCELL | 3 | 9 | spidatain<1>
 ATTRIBUTES | 8520560 | 0
-OUTPUTMC | 2 | 1 | 11 | 0 | 5
-INPUTS | 5 | spidatain<0>  | $OpTx$INV$22__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
-INPUTMC | 4 | 1 | 13 | 1 | 5 | 1 | 4 | 1 | 2
+OUTPUTMC | 2 | 1 | 12 | 0 | 5
+INPUTS | 5 | spidatain<0>  | $OpTx$INV$24__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
+INPUTMC | 4 | 3 | 11 | 1 | 5 | 1 | 4 | 1 | 2
 INPUTP | 1 | 49
 EQ | 4 | 
    spidatain<1>.D = spidatain<0>;
-   spidatain<1>.CLK = !$OpTx$INV$22__$INT;
+   spidatain<1>.CLK = !$OpTx$INV$24__$INT;
    spidatain<1>.AR = !cpu_Nres;
    spidatain<1>.CE = shiftcnt<0> & shifting2;
 
-MACROCELL | 1 | 11 | spidatain<2>
+MACROCELL | 1 | 12 | spidatain<2>
 ATTRIBUTES | 8520560 | 0
-OUTPUTMC | 2 | 1 | 10 | 0 | 7
-INPUTS | 5 | spidatain<1>  | $OpTx$INV$22__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
-INPUTMC | 4 | 1 | 12 | 1 | 5 | 1 | 4 | 1 | 2
+OUTPUTMC | 2 | 1 | 11 | 0 | 7
+INPUTS | 5 | spidatain<1>  | $OpTx$INV$24__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
+INPUTMC | 4 | 3 | 9 | 1 | 5 | 1 | 4 | 1 | 2
 INPUTP | 1 | 49
 EQ | 4 | 
    spidatain<2>.D = spidatain<1>;
-   spidatain<2>.CLK = !$OpTx$INV$22__$INT;
+   spidatain<2>.CLK = !$OpTx$INV$24__$INT;
    spidatain<2>.AR = !cpu_Nres;
    spidatain<2>.CE = shiftcnt<0> & shifting2;
 
-MACROCELL | 1 | 10 | spidatain<3>
+MACROCELL | 1 | 11 | spidatain<3>
 ATTRIBUTES | 8520560 | 0
-OUTPUTMC | 2 | 1 | 9 | 0 | 14
-INPUTS | 5 | spidatain<2>  | $OpTx$INV$22__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
-INPUTMC | 4 | 1 | 11 | 1 | 5 | 1 | 4 | 1 | 2
+OUTPUTMC | 2 | 1 | 10 | 0 | 14
+INPUTS | 5 | spidatain<2>  | $OpTx$INV$24__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
+INPUTMC | 4 | 1 | 12 | 1 | 5 | 1 | 4 | 1 | 2
 INPUTP | 1 | 49
 EQ | 4 | 
    spidatain<3>.D = spidatain<2>;
-   spidatain<3>.CLK = !$OpTx$INV$22__$INT;
+   spidatain<3>.CLK = !$OpTx$INV$24__$INT;
    spidatain<3>.AR = !cpu_Nres;
    spidatain<3>.CE = shiftcnt<0> & shifting2;
 
-MACROCELL | 1 | 9 | spidatain<4>
+MACROCELL | 1 | 10 | spidatain<4>
 ATTRIBUTES | 8520560 | 0
-OUTPUTMC | 2 | 1 | 8 | 0 | 16
-INPUTS | 5 | spidatain<3>  | $OpTx$INV$22__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
-INPUTMC | 4 | 1 | 10 | 1 | 5 | 1 | 4 | 1 | 2
+OUTPUTMC | 2 | 1 | 9 | 0 | 16
+INPUTS | 5 | spidatain<3>  | $OpTx$INV$24__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
+INPUTMC | 4 | 1 | 11 | 1 | 5 | 1 | 4 | 1 | 2
 INPUTP | 1 | 49
 EQ | 4 | 
    spidatain<4>.D = spidatain<3>;
-   spidatain<4>.CLK = !$OpTx$INV$22__$INT;
+   spidatain<4>.CLK = !$OpTx$INV$24__$INT;
    spidatain<4>.AR = !cpu_Nres;
    spidatain<4>.CE = shiftcnt<0> & shifting2;
 
-MACROCELL | 1 | 8 | spidatain<5>
+MACROCELL | 1 | 9 | spidatain<5>
 ATTRIBUTES | 8520560 | 0
 OUTPUTMC | 2 | 1 | 7 | 2 | 1
-INPUTS | 5 | spidatain<4>  | $OpTx$INV$22__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
-INPUTMC | 4 | 1 | 9 | 1 | 5 | 1 | 4 | 1 | 2
+INPUTS | 5 | spidatain<4>  | $OpTx$INV$24__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
+INPUTMC | 4 | 1 | 10 | 1 | 5 | 1 | 4 | 1 | 2
 INPUTP | 1 | 49
 EQ | 4 | 
    spidatain<5>.D = spidatain<4>;
-   spidatain<5>.CLK = !$OpTx$INV$22__$INT;
+   spidatain<5>.CLK = !$OpTx$INV$24__$INT;
    spidatain<5>.AR = !cpu_Nres;
    spidatain<5>.CE = shiftcnt<0> & shifting2;
 
 MACROCELL | 1 | 7 | spidatain<6>
 ATTRIBUTES | 8520560 | 0
 OUTPUTMC | 2 | 1 | 6 | 2 | 4
-INPUTS | 5 | spidatain<5>  | $OpTx$INV$22__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
-INPUTMC | 4 | 1 | 8 | 1 | 5 | 1 | 4 | 1 | 2
+INPUTS | 5 | spidatain<5>  | $OpTx$INV$24__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
+INPUTMC | 4 | 1 | 9 | 1 | 5 | 1 | 4 | 1 | 2
 INPUTP | 1 | 49
 EQ | 4 | 
    spidatain<6>.D = spidatain<5>;
-   spidatain<6>.CLK = !$OpTx$INV$22__$INT;
+   spidatain<6>.CLK = !$OpTx$INV$24__$INT;
    spidatain<6>.AR = !cpu_Nres;
    spidatain<6>.CE = shiftcnt<0> & shifting2;
 
 MACROCELL | 1 | 6 | spidatain<7>
 ATTRIBUTES | 8520560 | 0
 OUTPUTMC | 1 | 2 | 7
-INPUTS | 5 | spidatain<6>  | $OpTx$INV$22__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
+INPUTS | 5 | spidatain<6>  | $OpTx$INV$24__$INT  | cpu_Nres  | shiftcnt<0>  | shifting2
 INPUTMC | 4 | 1 | 7 | 1 | 5 | 1 | 4 | 1 | 2
 INPUTP | 1 | 49
 EQ | 4 | 
    spidatain<7>.D = spidatain<6>;
-   spidatain<7>.CLK = !$OpTx$INV$22__$INT;
+   spidatain<7>.CLK = !$OpTx$INV$24__$INT;
    spidatain<7>.AR = !cpu_Nres;
    spidatain<7>.CE = shiftcnt<0> & shifting2;
 
 MACROCELL | 3 | 16 | int_sclk
 ATTRIBUTES | 8651698 | 0
-INPUTS | 8 | cpol  | cpu_Nres  | cpha  | shiftcnt<0>  | shiftdone  | shifting2  | $OpTx$INV$22__$INT  | EXP7_.EXP
-INPUTMC | 7 | 0 | 15 | 0 | 17 | 1 | 4 | 1 | 3 | 1 | 2 | 1 | 5 | 3 | 15
+INPUTS | 8 | cpol  | cpu_Nres  | cpha  | shiftcnt<0>  | shiftdone  | shifting2  | $OpTx$INV$24__$INT  | shiftcnt<1>.EXP
+INPUTMC | 7 | 0 | 15 | 0 | 17 | 1 | 4 | 3 | 0 | 1 | 2 | 1 | 5 | 3 | 15
 INPUTP | 1 | 49
 IMPORTS | 1 | 3 | 15
 EQ | 9 | 
@@ -281,327 +281,368 @@ EQ | 9 |
 ;Imported pterms FB4_16
 	# cpu_Nres & cpha & !shiftcnt<0> & !shiftdone & 
 	shifting2;
-   spi_sclk.CLK = !$OpTx$INV$22__$INT;
+   spi_sclk.CLK = !$OpTx$INV$24__$INT;
    spi_sclk.AP = !cpu_Nres & cpol;
    spi_sclk.AR = !cpu_Nres & !cpol;
 
 MACROCELL | 0 | 14 | int_dout<3>
 ATTRIBUTES | 265986 | 0
-INPUTS | 8 | cpu_rnw  | spidatain<3>  | cpu_a<1>  | cs1  | Ncs2  | cpu_a<0>  | cpu_Nphi2  | tmo
-INPUTMC | 2 | 1 | 10 | 0 | 6
-INPUTP | 6 | 24 | 59 | 50 | 46 | 52 | 20
+INPUTS | 7 | Ncs2  | cpu_rnw  | spidatain<3>  | cpu_a<1>  | cpu_a<0>  | cpu_Nphi2  | tmo
+INPUTMC | 2 | 1 | 11 | 0 | 6
+INPUTP | 5 | 46 | 24 | 59 | 52 | 20
 EQ | 5 | 
-   cpu_d<3> = cpu_rnw & tmo & !cpu_a<1> & cs1 & !Ncs2 & 
-	cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & spidatain<3> & !cpu_a<1> & cs1 & !Ncs2 & 
+   cpu_d<3> = !Ncs2 & cpu_rnw & tmo & !cpu_a<1> & cpu_a<0> & 
+	cpu_Nphi2
+	# !Ncs2 & cpu_rnw & spidatain<3> & !cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2;
-   cpu_d<3>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
+   cpu_d<3>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
 
 MACROCELL | 2 | 1 | int_dout<5>
 ATTRIBUTES | 265986 | 0
-INPUTS | 9 | cpu_rnw  | cpu_a<1>  | start_shifting  | cs1  | Ncs2  | cpu_a<0>  | cpu_Nphi2  | shifting2  | spidatain<5>
-INPUTMC | 3 | 3 | 2 | 1 | 2 | 1 | 8
-INPUTP | 6 | 24 | 59 | 50 | 46 | 52 | 20
+INPUTS | 8 | Ncs2  | cpu_rnw  | cpu_a<1>  | start_shifting  | cpu_a<0>  | cpu_Nphi2  | shifting2  | spidatain<5>
+INPUTMC | 3 | 3 | 2 | 1 | 2 | 1 | 9
+INPUTP | 5 | 46 | 24 | 59 | 52 | 20
 EQ | 7 | 
-   cpu_d<5> = cpu_rnw & spidatain<5> & !cpu_a<1> & cs1 & !Ncs2 & 
+   cpu_d<5> = !Ncs2 & cpu_rnw & spidatain<5> & !cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & !cpu_a<1> & start_shifting & cs1 & 
-	!Ncs2 & cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & !cpu_a<1> & cs1 & !Ncs2 & cpu_a<0> & 
+	# !Ncs2 & cpu_rnw & !cpu_a<1> & start_shifting & 
+	cpu_a<0> & cpu_Nphi2
+	# !Ncs2 & cpu_rnw & !cpu_a<1> & cpu_a<0> & 
 	shifting2 & cpu_Nphi2;
-   cpu_d<5>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
+   cpu_d<5>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
 
 MACROCELL | 2 | 4 | int_dout<6>
 ATTRIBUTES | 265986 | 0
-INPUTS | 8 | cpu_rnw  | spidatain<6>  | cpu_a<1>  | cs1  | Ncs2  | cpu_a<0>  | cpu_Nphi2  | ier
-INPUTMC | 2 | 1 | 7 | 3 | 8
-INPUTP | 6 | 24 | 59 | 50 | 46 | 52 | 20
+INPUTS | 7 | Ncs2  | cpu_rnw  | spidatain<6>  | cpu_a<1>  | cpu_a<0>  | cpu_Nphi2  | ier
+INPUTMC | 2 | 1 | 7 | 3 | 17
+INPUTP | 5 | 46 | 24 | 59 | 52 | 20
 EQ | 5 | 
-   cpu_d<6> = cpu_rnw & ier & !cpu_a<1> & cs1 & !Ncs2 & 
-	cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & spidatain<6> & !cpu_a<1> & cs1 & !Ncs2 & 
+   cpu_d<6> = !Ncs2 & cpu_rnw & ier & !cpu_a<1> & cpu_a<0> & 
+	cpu_Nphi2
+	# !Ncs2 & cpu_rnw & spidatain<6> & !cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2;
-   cpu_d<6>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
+   cpu_d<6>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
 
 MACROCELL | 2 | 7 | int_dout<7>
 ATTRIBUTES | 265986 | 0
-INPUTS | 8 | cpu_rnw  | spidatain<7>  | cpu_a<1>  | cs1  | Ncs2  | cpu_a<0>  | cpu_Nphi2  | tc
-INPUTMC | 2 | 1 | 6 | 3 | 1
-INPUTP | 6 | 24 | 59 | 50 | 46 | 52 | 20
+INPUTS | 7 | Ncs2  | cpu_rnw  | spidatain<7>  | cpu_a<1>  | cpu_a<0>  | cpu_Nphi2  | tc
+INPUTMC | 2 | 1 | 6 | 1 | 3
+INPUTP | 5 | 46 | 24 | 59 | 52 | 20
 EQ | 5 | 
-   cpu_d<7> = cpu_rnw & spidatain<7> & !cpu_a<1> & cs1 & !Ncs2 & 
+   cpu_d<7> = !Ncs2 & cpu_rnw & spidatain<7> & !cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & !cpu_a<1> & tc & cs1 & !Ncs2 & 
-	cpu_a<0> & cpu_Nphi2;
-   cpu_d<7>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
+	# !Ncs2 & cpu_rnw & !cpu_a<1> & tc & cpu_a<0> & 
+	cpu_Nphi2;
+   cpu_d<7>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
 
-MACROCELL | 1 | 14 | shiftcnt<3>
+MACROCELL | 3 | 12 | shiftcnt<3>
 ATTRIBUTES | 4326192 | 0
-OUTPUTMC | 5 | 1 | 1 | 1 | 14 | 1 | 3 | 1 | 0 | 1 | 2
-INPUTS | 7 | shiftcnt<2>  | shiftcnt<0>  | shiftcnt<1>  | shifting2  | shiftcnt<3>  | $OpTx$INV$22__$INT  | cpu_Nres
-INPUTMC | 6 | 1 | 15 | 1 | 4 | 1 | 16 | 1 | 2 | 1 | 14 | 1 | 5
+OUTPUTMC | 5 | 1 | 1 | 3 | 12 | 3 | 0 | 1 | 0 | 1 | 2
+INPUTS | 7 | shiftcnt<2>  | shiftcnt<0>  | shiftcnt<1>  | shifting2  | shiftcnt<3>  | $OpTx$INV$24__$INT  | cpu_Nres
+INPUTMC | 6 | 3 | 14 | 1 | 4 | 3 | 15 | 1 | 2 | 3 | 12 | 1 | 5
 INPUTP | 1 | 49
 EQ | 5 | 
    shiftcnt<3>.T = shiftcnt<3> & !shifting2
 	# shiftcnt<2> & shiftcnt<0> & shiftcnt<1> & 
 	shifting2;
-   shiftcnt<3>.CLK = !$OpTx$INV$22__$INT;
+   shiftcnt<3>.CLK = !$OpTx$INV$24__$INT;
    shiftcnt<3>.AR = !cpu_Nres;
 
-MACROCELL | 1 | 15 | shiftcnt<2>
+MACROCELL | 3 | 14 | shiftcnt<2>
 ATTRIBUTES | 4326192 | 0
-OUTPUTMC | 6 | 1 | 1 | 1 | 14 | 1 | 15 | 1 | 3 | 1 | 0 | 1 | 2
-INPUTS | 6 | shiftcnt<0>  | shiftcnt<1>  | shifting2  | shiftcnt<2>  | $OpTx$INV$22__$INT  | cpu_Nres
-INPUTMC | 5 | 1 | 4 | 1 | 16 | 1 | 2 | 1 | 15 | 1 | 5
+OUTPUTMC | 6 | 1 | 1 | 3 | 12 | 3 | 14 | 3 | 0 | 1 | 0 | 1 | 2
+INPUTS | 6 | shiftcnt<0>  | shiftcnt<1>  | shifting2  | shiftcnt<2>  | $OpTx$INV$24__$INT  | cpu_Nres
+INPUTMC | 5 | 1 | 4 | 3 | 15 | 1 | 2 | 3 | 14 | 1 | 5
 INPUTP | 1 | 49
 EQ | 4 | 
    shiftcnt<2>.T = shiftcnt<2> & !shifting2
 	# shiftcnt<0> & shiftcnt<1> & shifting2;
-   shiftcnt<2>.CLK = !$OpTx$INV$22__$INT;
+   shiftcnt<2>.CLK = !$OpTx$INV$24__$INT;
    shiftcnt<2>.AR = !cpu_Nres;
 
 MACROCELL | 1 | 4 | shiftcnt<0>
 ATTRIBUTES | 8520496 | 0
-OUTPUTMC | 15 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 3 | 16 | 1 | 14 | 1 | 15 | 1 | 4 | 1 | 16 | 1 | 3 | 3 | 15
-INPUTS | 4 | shiftcnt<0>  | shifting2  | $OpTx$INV$22__$INT  | cpu_Nres
+OUTPUTMC | 14 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0
+INPUTS | 4 | shiftcnt<0>  | shifting2  | $OpTx$INV$24__$INT  | cpu_Nres
 INPUTMC | 3 | 1 | 4 | 1 | 2 | 1 | 5
 INPUTP | 1 | 49
 EQ | 3 | 
    shiftcnt<0>.D = !shiftcnt<0> & shifting2;
-   shiftcnt<0>.CLK = !$OpTx$INV$22__$INT;
+   shiftcnt<0>.CLK = !$OpTx$INV$24__$INT;
    shiftcnt<0>.AR = !cpu_Nres;
 
-MACROCELL | 1 | 16 | shiftcnt<1>
+MACROCELL | 3 | 15 | shiftcnt<1>
 ATTRIBUTES | 8520496 | 0
-OUTPUTMC | 7 | 1 | 1 | 1 | 14 | 1 | 15 | 1 | 16 | 1 | 3 | 1 | 0 | 1 | 2
-INPUTS | 5 | shiftcnt<0>  | shiftcnt<1>  | shifting2  | $OpTx$INV$22__$INT  | cpu_Nres
-INPUTMC | 4 | 1 | 4 | 1 | 16 | 1 | 2 | 1 | 5
+OUTPUTMC | 8 | 1 | 1 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 1 | 0 | 1 | 2 | 3 | 16
+INPUTS | 7 | shiftcnt<0>  | shiftcnt<1>  | shifting2  | $OpTx$INV$24__$INT  | cpu_Nres  | cpha  | shiftdone
+INPUTMC | 6 | 1 | 4 | 3 | 15 | 1 | 2 | 1 | 5 | 0 | 17 | 3 | 0
 INPUTP | 1 | 49
-EQ | 4 | 
+EXPORTS | 1 | 3 | 16
+EQ | 6 | 
    shiftcnt<1>.D = shiftcnt<0> & !shiftcnt<1> & shifting2
 	# !shiftcnt<0> & shiftcnt<1> & shifting2;
-   shiftcnt<1>.CLK = !$OpTx$INV$22__$INT;
+   shiftcnt<1>.CLK = !$OpTx$INV$24__$INT;
    shiftcnt<1>.AR = !cpu_Nres;
+    shiftcnt<1>.EXP  =  cpu_Nres & cpha & !shiftcnt<0> & !shiftdone & 
+	shifting2
 
-MACROCELL | 1 | 3 | shiftdone
+MACROCELL | 3 | 0 | shiftdone
 ATTRIBUTES | 8520496 | 0
-OUTPUTMC | 7 | 1 | 1 | 3 | 16 | 3 | 1 | 1 | 2 | 1 | 17 | 1 | 0 | 3 | 15
-INPUTS | 6 | shiftcnt<3>  | shiftcnt<2>  | shiftcnt<0>  | shiftcnt<1>  | $OpTx$INV$22__$INT  | cpu_Nres
-INPUTMC | 5 | 1 | 14 | 1 | 15 | 1 | 4 | 1 | 16 | 1 | 5
+OUTPUTMC | 7 | 1 | 1 | 3 | 16 | 1 | 3 | 1 | 2 | 1 | 17 | 1 | 0 | 3 | 15
+INPUTS | 6 | shiftcnt<3>  | shiftcnt<2>  | shiftcnt<0>  | shiftcnt<1>  | $OpTx$INV$24__$INT  | cpu_Nres
+INPUTMC | 5 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 1 | 5
 INPUTP | 1 | 49
 EQ | 4 | 
    shiftdone.D = shiftcnt<3> & shiftcnt<2> & shiftcnt<0> & 
 	shiftcnt<1>;
-   shiftdone.CLK = !$OpTx$INV$22__$INT;
+   shiftdone.CLK = !$OpTx$INV$24__$INT;
    shiftdone.AR = !cpu_Nres;
 
 MACROCELL | 3 | 2 | start_shifting
 ATTRIBUTES | 4326192 | 0
 OUTPUTMC | 5 | 2 | 1 | 3 | 2 | 1 | 2 | 3 | 13 | 1 | 5
-INPUTS | 8 | frx  | cpu_a<1>  | start_shifting  | cpu_a<0>  | cpu_rnw  | cs1  | Ncs2  | start_shifting/start_shifting_RSTF__$INT
+INPUTS | 7 | frx  | cpu_a<1>  | start_shifting  | cpu_a<0>  | cpu_rnw  | Ncs2  | start_shifting/start_shifting_RSTF__$INT
 INPUTMC | 3 | 0 | 9 | 3 | 2 | 1 | 17
-INPUTP | 5 | 59 | 52 | 24 | 50 | 46
+INPUTP | 4 | 59 | 52 | 24 | 46
 EQ | 4 | 
    start_shifting.T = !cpu_rnw & !cpu_a<1> & !start_shifting & !cpu_a<0>
 	# frx & !cpu_a<1> & !start_shifting & !cpu_a<0>;
-   !start_shifting.CLK = cs1 & !Ncs2;
+   start_shifting.CLK = Ncs2;
    start_shifting.AR = !start_shifting/start_shifting_RSTF__$INT;
 
-MACROCELL | 3 | 1 | tc
+MACROCELL | 1 | 3 | tc
 ATTRIBUTES | 8520672 | 0
-OUTPUTMC | 2 | 2 | 7 | 3 | 0
-INPUTS | 5 | cs1  | Ncs2  | shiftdone  | cpu_a<1>  | cpu_a<0>
-INPUTMC | 1 | 1 | 3
-INPUTP | 4 | 50 | 46 | 59 | 52
+OUTPUTMC | 2 | 2 | 7 | 2 | 17
+INPUTS | 4 | Ncs2  | shiftdone  | cpu_a<1>  | cpu_a<0>
+INPUTMC | 1 | 3 | 0
+INPUTP | 3 | 46 | 59 | 52
 EQ | 4 | 
    tc.D = Gnd;
-   !tc.CLK = cs1 & !Ncs2;
+   tc.CLK = Ncs2;
    tc.AP = shiftdone;
    tc.CE = !cpu_a<1> & !cpu_a<0>;
 
 MACROCELL | 0 | 3 | spidataout<0>
 ATTRIBUTES | 4326240 | 0
-OUTPUTMC | 2 | 1 | 0 | 0 | 3
-INPUTS | 8 | cpu_a<1>  | spidataout<0>  | cpu_a<0>  | cpu_d<0>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+OUTPUTMC | 2 | 1 | 1 | 0 | 3
+INPUTS | 7 | cpu_a<1>  | spidataout<0>  | cpu_a<0>  | cpu_d<0>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 3
-INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24
 EQ | 6 | 
    spidataout<0>.T = !cpu_a<1> & spidataout<0> & !cpu_a<0> & 
 	!cpu_d<0>.PIN
 	# !cpu_a<1> & !spidataout<0> & !cpu_a<0> & 
 	cpu_d<0>.PIN;
-   !spidataout<0>.CLK = cs1 & !Ncs2;
+   spidataout<0>.CLK = Ncs2;
    spidataout<0>.CE = cpu_Nres & !cpu_rnw;
 
 MACROCELL | 0 | 2 | spidataout<1>
 ATTRIBUTES | 4326240 | 0
-OUTPUTMC | 2 | 1 | 1 | 0 | 2
-INPUTS | 8 | cpu_a<1>  | spidataout<1>  | cpu_a<0>  | cpu_d<1>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+OUTPUTMC | 2 | 0 | 2 | 1 | 2
+INPUTS | 7 | cpu_a<1>  | spidataout<1>  | cpu_a<0>  | cpu_d<1>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 2
-INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24
 EQ | 6 | 
    spidataout<1>.T = !cpu_a<1> & spidataout<1> & !cpu_a<0> & 
 	!cpu_d<1>.PIN
 	# !cpu_a<1> & !spidataout<1> & !cpu_a<0> & 
 	cpu_d<1>.PIN;
-   !spidataout<1>.CLK = cs1 & !Ncs2;
+   spidataout<1>.CLK = Ncs2;
    spidataout<1>.CE = cpu_Nres & !cpu_rnw;
 
 MACROCELL | 0 | 1 | spidataout<2>
 ATTRIBUTES | 4326240 | 0
 OUTPUTMC | 2 | 1 | 0 | 0 | 1
-INPUTS | 8 | cpu_a<1>  | spidataout<2>  | cpu_a<0>  | cpu_d<2>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | cpu_a<1>  | spidataout<2>  | cpu_a<0>  | cpu_d<2>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 0 | 1
-INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24
 EQ | 6 | 
    spidataout<2>.T = !cpu_a<1> & spidataout<2> & !cpu_a<0> & 
 	!cpu_d<2>.PIN
 	# !cpu_a<1> & !spidataout<2> & !cpu_a<0> & 
 	cpu_d<2>.PIN;
-   !spidataout<2>.CLK = cs1 & !Ncs2;
+   spidataout<2>.CLK = Ncs2;
    spidataout<2>.CE = cpu_Nres & !cpu_rnw;
 
-MACROCELL | 3 | 7 | spidataout<3>
+MACROCELL | 0 | 0 | spidataout<3>
 ATTRIBUTES | 4326240 | 0
-OUTPUTMC | 2 | 1 | 0 | 3 | 7
-INPUTS | 8 | cpu_a<1>  | spidataout<3>  | cpu_a<0>  | cpu_d<3>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
-INPUTMC | 1 | 3 | 7
-INPUTP | 7 | 59 | 52 | 26 | 50 | 46 | 49 | 24
+OUTPUTMC | 2 | 1 | 0 | 0 | 0
+INPUTS | 7 | cpu_a<1>  | spidataout<3>  | cpu_a<0>  | cpu_d<3>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTMC | 1 | 0 | 0
+INPUTP | 6 | 59 | 52 | 26 | 46 | 49 | 24
 EQ | 6 | 
    spidataout<3>.T = !cpu_a<1> & spidataout<3> & !cpu_a<0> & 
 	!cpu_d<3>.PIN
 	# !cpu_a<1> & !spidataout<3> & !cpu_a<0> & 
 	cpu_d<3>.PIN;
-   !spidataout<3>.CLK = cs1 & !Ncs2;
+   spidataout<3>.CLK = Ncs2;
    spidataout<3>.CE = cpu_Nres & !cpu_rnw;
 
-MACROCELL | 3 | 6 | spidataout<4>
+MACROCELL | 3 | 8 | spidataout<4>
 ATTRIBUTES | 4326240 | 0
-OUTPUTMC | 2 | 1 | 0 | 3 | 6
-INPUTS | 8 | cpu_a<1>  | spidataout<4>  | cpu_a<0>  | cpu_d<4>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
-INPUTMC | 1 | 3 | 6
-INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24
+OUTPUTMC | 2 | 1 | 1 | 3 | 8
+INPUTS | 7 | cpu_a<1>  | spidataout<4>  | cpu_a<0>  | cpu_d<4>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTMC | 1 | 3 | 8
+INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24
 EQ | 6 | 
    spidataout<4>.T = !cpu_a<1> & spidataout<4> & !cpu_a<0> & 
 	!cpu_d<4>.PIN
 	# !cpu_a<1> & !spidataout<4> & !cpu_a<0> & 
 	cpu_d<4>.PIN;
-   !spidataout<4>.CLK = cs1 & !Ncs2;
+   spidataout<4>.CLK = Ncs2;
    spidataout<4>.CE = cpu_Nres & !cpu_rnw;
 
-MACROCELL | 3 | 5 | spidataout<5>
+MACROCELL | 3 | 6 | spidataout<5>
 ATTRIBUTES | 4326240 | 0
-OUTPUTMC | 2 | 1 | 1 | 3 | 5
-INPUTS | 8 | cpu_a<1>  | spidataout<5>  | cpu_a<0>  | cpu_d<5>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
-INPUTMC | 1 | 3 | 5
-INPUTP | 7 | 59 | 52 | 29 | 50 | 46 | 49 | 24
+OUTPUTMC | 2 | 1 | 0 | 3 | 6
+INPUTS | 7 | cpu_a<1>  | spidataout<5>  | cpu_a<0>  | cpu_d<5>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTMC | 1 | 3 | 6
+INPUTP | 6 | 59 | 52 | 29 | 46 | 49 | 24
 EQ | 6 | 
    spidataout<5>.T = !cpu_a<1> & spidataout<5> & !cpu_a<0> & 
 	!cpu_d<5>.PIN
 	# !cpu_a<1> & !spidataout<5> & !cpu_a<0> & 
 	cpu_d<5>.PIN;
-   !spidataout<5>.CLK = cs1 & !Ncs2;
+   spidataout<5>.CLK = Ncs2;
    spidataout<5>.CE = cpu_Nres & !cpu_rnw;
 
-MACROCELL | 3 | 4 | spidataout<6>
+MACROCELL | 3 | 5 | spidataout<6>
 ATTRIBUTES | 4326240 | 0
-OUTPUTMC | 2 | 3 | 4 | 1 | 2
-INPUTS | 8 | cpu_a<1>  | spidataout<6>  | cpu_a<0>  | cpu_d<6>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
-INPUTMC | 1 | 3 | 4
-INPUTP | 7 | 59 | 52 | 31 | 50 | 46 | 49 | 24
+OUTPUTMC | 2 | 1 | 0 | 3 | 5
+INPUTS | 7 | cpu_a<1>  | spidataout<6>  | cpu_a<0>  | cpu_d<6>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTMC | 1 | 3 | 5
+INPUTP | 6 | 59 | 52 | 31 | 46 | 49 | 24
 EQ | 6 | 
    spidataout<6>.T = !cpu_a<1> & spidataout<6> & !cpu_a<0> & 
 	!cpu_d<6>.PIN
 	# !cpu_a<1> & !spidataout<6> & !cpu_a<0> & 
 	cpu_d<6>.PIN;
-   !spidataout<6>.CLK = cs1 & !Ncs2;
+   spidataout<6>.CLK = Ncs2;
    spidataout<6>.CE = cpu_Nres & !cpu_rnw;
 
 MACROCELL | 3 | 3 | spidataout<7>
 ATTRIBUTES | 4326240 | 0
 OUTPUTMC | 2 | 1 | 0 | 3 | 3
-INPUTS | 8 | cpu_a<1>  | spidataout<7>  | cpu_a<0>  | cpu_d<7>.PIN  | cs1  | Ncs2  | cpu_Nres  | cpu_rnw
+INPUTS | 7 | cpu_a<1>  | spidataout<7>  | cpu_a<0>  | cpu_d<7>.PIN  | Ncs2  | cpu_Nres  | cpu_rnw
 INPUTMC | 1 | 3 | 3
-INPUTP | 7 | 59 | 52 | 33 | 50 | 46 | 49 | 24
+INPUTP | 6 | 59 | 52 | 33 | 46 | 49 | 24
 EQ | 6 | 
    spidataout<7>.T = !cpu_a<1> & spidataout<7> & !cpu_a<0> & 
 	!cpu_d<7>.PIN
 	# !cpu_a<1> & !spidataout<7> & !cpu_a<0> & 
 	cpu_d<7>.PIN;
-   !spidataout<7>.CLK = cs1 & !Ncs2;
+   spidataout<7>.CLK = Ncs2;
    spidataout<7>.CE = cpu_Nres & !cpu_rnw;
 
+MACROCELL | 2 | 14 | ng_OBUF
+ATTRIBUTES | 264962 | 0
+INPUTS | 3 | Ncs2  | nio_stb  | nio_sel
+INPUTP | 3 | 46 | 9 | 3
+EQ | 1 | 
+   ng = Ncs2 & nio_stb & nio_sel;
+
 MACROCELL | 0 | 4 | int_dout<0>
 ATTRIBUTES | 265986 | 0
-INPUTS | 10 | cpu_rnw  | spidatain<0>  | cpu_a<1>  | cs1  | Ncs2  | cpu_a<0>  | cpu_Nphi2  | divisor<0>  | cpha  | spi_Nsel
-INPUTMC | 4 | 1 | 13 | 0 | 13 | 0 | 17 | 3 | 10
-INPUTP | 6 | 24 | 59 | 50 | 46 | 52 | 20
+INPUTS | 9 | Ncs2  | cpu_rnw  | spidatain<0>  | cpu_a<1>  | cpu_a<0>  | cpu_Nphi2  | divisor<0>  | cpha  | spi_Nsel
+INPUTMC | 4 | 3 | 11 | 0 | 13 | 0 | 17 | 3 | 10
+INPUTP | 5 | 46 | 24 | 59 | 52 | 20
 EQ | 9 | 
-   cpu_d<0> = cpu_rnw & spi_Nsel & cpu_a<1> & cs1 & !Ncs2 & 
+   cpu_d<0> = !Ncs2 & cpu_rnw & spi_Nsel & cpu_a<1> & 
 	cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & cpha & !cpu_a<1> & cs1 & !Ncs2 & 
-	cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & divisor<0> & cpu_a<1> & cs1 & !Ncs2 & 
+	# !Ncs2 & cpu_rnw & cpha & !cpu_a<1> & cpu_a<0> & 
+	cpu_Nphi2
+	# !Ncs2 & cpu_rnw & divisor<0> & cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & spidatain<0> & !cpu_a<1> & cs1 & !Ncs2 & 
+	# !Ncs2 & cpu_rnw & spidatain<0> & !cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2;
-   cpu_d<0>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
+   cpu_d<0>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
 
 MACROCELL | 0 | 5 | int_dout<1>
 ATTRIBUTES | 265986 | 0
-INPUTS | 9 | cpu_rnw  | spidatain<1>  | cpu_a<1>  | cs1  | Ncs2  | cpu_a<0>  | cpu_Nphi2  | cpol  | divisor<1>
-INPUTMC | 3 | 1 | 12 | 0 | 15 | 0 | 12
-INPUTP | 6 | 24 | 59 | 50 | 46 | 52 | 20
+INPUTS | 8 | Ncs2  | cpu_rnw  | spidatain<1>  | cpu_a<1>  | cpu_a<0>  | cpu_Nphi2  | cpol  | divisor<1>
+INPUTMC | 3 | 3 | 9 | 0 | 15 | 0 | 12
+INPUTP | 5 | 46 | 24 | 59 | 52 | 20
 EQ | 7 | 
-   cpu_d<1> = cpu_rnw & cpol & !cpu_a<1> & cs1 & !Ncs2 & 
-	cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & divisor<1> & cpu_a<1> & cs1 & !Ncs2 & 
+   cpu_d<1> = !Ncs2 & cpu_rnw & cpol & !cpu_a<1> & cpu_a<0> & 
+	cpu_Nphi2
+	# !Ncs2 & cpu_rnw & divisor<1> & cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & spidatain<1> & !cpu_a<1> & cs1 & !Ncs2 & 
+	# !Ncs2 & cpu_rnw & spidatain<1> & !cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2;
-   cpu_d<1>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
+   cpu_d<1>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
 
 MACROCELL | 0 | 7 | int_dout<2>
 ATTRIBUTES | 265986 | 0
-INPUTS | 9 | cpu_rnw  | spidatain<2>  | cpu_a<1>  | cs1  | Ncs2  | cpu_a<0>  | cpu_Nphi2  | ece  | divisor<2>
-INPUTMC | 3 | 1 | 11 | 0 | 10 | 0 | 11
-INPUTP | 6 | 24 | 59 | 50 | 46 | 52 | 20
+INPUTS | 8 | Ncs2  | cpu_rnw  | spidatain<2>  | cpu_a<1>  | cpu_a<0>  | cpu_Nphi2  | ece  | divisor<2>
+INPUTMC | 3 | 1 | 12 | 0 | 10 | 0 | 11
+INPUTP | 5 | 46 | 24 | 59 | 52 | 20
 EQ | 7 | 
-   cpu_d<2> = cpu_rnw & ece & !cpu_a<1> & cs1 & !Ncs2 & 
-	cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & divisor<2> & cpu_a<1> & cs1 & !Ncs2 & 
+   cpu_d<2> = !Ncs2 & cpu_rnw & ece & !cpu_a<1> & cpu_a<0> & 
+	cpu_Nphi2
+	# !Ncs2 & cpu_rnw & divisor<2> & cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & spidatain<2> & !cpu_a<1> & cs1 & !Ncs2 & 
+	# !Ncs2 & cpu_rnw & spidatain<2> & !cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2;
-   cpu_d<2>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
+   cpu_d<2>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
 
 MACROCELL | 0 | 16 | int_dout<4>
 ATTRIBUTES | 265986 | 0
-INPUTS | 10 | cpu_rnw  | spidatain<4>  | cpu_a<1>  | cs1  | Ncs2  | cpu_a<0>  | cpu_Nphi2  | spi_int  | frx  | slaveinten
-INPUTMC | 3 | 1 | 9 | 0 | 9 | 0 | 8
-INPUTP | 7 | 24 | 59 | 50 | 46 | 52 | 20 | 7
+INPUTS | 9 | Ncs2  | cpu_rnw  | spidatain<4>  | cpu_a<1>  | cpu_a<0>  | cpu_Nphi2  | spi_int  | frx  | slaveinten
+INPUTMC | 3 | 1 | 10 | 0 | 9 | 0 | 8
+INPUTP | 6 | 46 | 24 | 59 | 52 | 20 | 7
 EQ | 9 | 
-   cpu_d<4> = cpu_rnw & frx & !cpu_a<1> & cs1 & !Ncs2 & 
+   cpu_d<4> = !Ncs2 & cpu_rnw & frx & !cpu_a<1> & cpu_a<0> & 
+	cpu_Nphi2
+	# !Ncs2 & cpu_rnw & slaveinten & cpu_a<1> & 
 	cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & slaveinten & cpu_a<1> & cs1 & !Ncs2 & 
-	cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & spidatain<4> & !cpu_a<1> & cs1 & !Ncs2 & 
+	# !Ncs2 & cpu_rnw & spidatain<4> & !cpu_a<1> & 
 	!cpu_a<0> & cpu_Nphi2
-	# cpu_rnw & cpu_a<1> & cs1 & !Ncs2 & !cpu_a<0> & 
-	!spi_int & cpu_Nphi2;
-   cpu_d<4>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
+	# !Ncs2 & cpu_rnw & cpu_a<1> & !cpu_a<0> & !spi_int & 
+	cpu_Nphi2;
+   cpu_d<4>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
 
 MACROCELL | 1 | 2 | shifting2
 ATTRIBUTES | 8520480 | 0
-OUTPUTMC | 20 | 1 | 1 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 3 | 16 | 2 | 1 | 1 | 14 | 1 | 15 | 1 | 4 | 1 | 16 | 3 | 13 | 1 | 5 | 1 | 0 | 1 | 2 | 3 | 15
-INPUTS | 8 | shiftdone  | start_shifting  | $OpTx$INV$22__$INT  | shiftcnt<3>  | shiftcnt<2>  | shiftcnt<1>  | spidataout<6>  | shifting2
-INPUTMC | 8 | 1 | 3 | 3 | 2 | 1 | 5 | 1 | 14 | 1 | 15 | 1 | 16 | 3 | 4 | 1 | 2
+OUTPUTMC | 19 | 1 | 1 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 2 | 1 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 13 | 1 | 5 | 1 | 0 | 1 | 2
+INPUTS | 8 | shiftdone  | start_shifting  | $OpTx$INV$24__$INT  | shiftcnt<3>  | shiftcnt<2>  | shiftcnt<1>  | spidataout<1>  | shifting2
+INPUTMC | 8 | 3 | 0 | 3 | 2 | 1 | 5 | 3 | 12 | 3 | 14 | 3 | 15 | 0 | 2 | 1 | 2
 EXPORTS | 1 | 1 | 1
 EQ | 4 | 
    shifting2.D = !shiftdone & start_shifting;
-   shifting2.CLK = !$OpTx$INV$22__$INT;
-    shifting2.EXP  =  !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & 
-	!shiftdone & !spidataout<6> & shifting2
+   shifting2.CLK = !$OpTx$INV$24__$INT;
+    shifting2.EXP  =  shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & 
+	!shiftdone & !spidataout<1> & shifting2
+
+MACROCELL | 2 | 16 | add_dec/XLXN_11
+ATTRIBUTES | 8553216 | 0
+OUTPUTMC | 1 | 2 | 8
+INPUTS | 4 | nio_stb  | a9  | a8  | a10
+INPUTP | 4 | 9 | 89 | 88 | 90
+EQ | 2 | 
+   !add_dec/XLXN_11.D = !nio_stb & a9 & a8 & a10;
+   add_dec/XLXN_11.CLK = extclk;	// GCK
+GLOBALS | 1 | 2 | extclk
+
+MACROCELL | 3 | 7 | b10_OBUF
+ATTRIBUTES | 264962 | 0
+INPUTS | 2 | a10  | nio_sel
+INPUTP | 2 | 90 | 3
+EQ | 1 | 
+   b10 = a10 & nio_sel;
+
+MACROCELL | 3 | 1 | b8_OBUF
+ATTRIBUTES | 264962 | 0
+INPUTS | 2 | a8  | nio_sel
+INPUTP | 2 | 88 | 3
+EQ | 1 | 
+   b8 = a8 & nio_sel;
+
+MACROCELL | 3 | 4 | b9_OBUF
+ATTRIBUTES | 264962 | 0
+INPUTS | 2 | a9  | nio_sel
+INPUTP | 2 | 89 | 3
+EQ | 1 | 
+   b9 = a9 & nio_sel;
 
 MACROCELL | 3 | 13 | led_OBUF
 ATTRIBUTES | 264962 | 0
@@ -610,22 +651,31 @@ INPUTMC | 3 | 3 | 10 | 3 | 2 | 1 | 2
 EQ | 1 | 
    led = spi_Nsel & !start_shifting & !shifting2;
 
-MACROCELL | 2 | 8 | cpu_Nirq_OBUFE
+MACROCELL | 2 | 8 | noe_OBUF
+ATTRIBUTES | 264962 | 0
+INPUTS | 3 | nio_sel  | add_dec/XLXN_11  | nio_stb
+INPUTMC | 1 | 2 | 16
+INPUTP | 2 | 3 | 9
+EQ | 2 | 
+   !noe = !nio_stb & add_dec/XLXN_11
+	# !nio_sel & add_dec/XLXN_11;
+
+MACROCELL | 1 | 8 | cpu_Nirq_OBUFE
 ATTRIBUTES | 265986 | 0
 INPUTS | 1 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
-INPUTMC | 1 | 3 | 0
+INPUTMC | 1 | 2 | 17
 EQ | 2 | 
    cpu_Nirq = Gnd;
    cpu_Nirq.OE = cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST;
 
-MACROCELL | 1 | 5 | $OpTx$INV$22__$INT
+MACROCELL | 1 | 5 | $OpTx$INV$24__$INT
 ATTRIBUTES | 133888 | 0
-OUTPUTMC | 16 | 1 | 1 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 3 | 16 | 1 | 14 | 1 | 15 | 1 | 4 | 1 | 16 | 1 | 3 | 1 | 2
+OUTPUTMC | 16 | 1 | 1 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0 | 1 | 2
 INPUTS | 5 | ece  | cpu_Nphi2  | extclk  | start_shifting  | shifting2
 INPUTMC | 3 | 0 | 10 | 3 | 2 | 1 | 2
 INPUTP | 2 | 20 | 21
 EQ | 3 | 
-   $OpTx$INV$22__$INT = ece & !extclk
+   $OpTx$INV$24__$INT = ece & !extclk
 	# !ece & !cpu_Nphi2
 	# !start_shifting & !shifting2;
 
@@ -633,16 +683,16 @@ MACROCELL | 1 | 17 | start_shifting/start_shifting_RSTF__$INT
 ATTRIBUTES | 133888 | 0
 OUTPUTMC | 1 | 3 | 2
 INPUTS | 2 | cpu_Nres  | shiftdone
-INPUTMC | 1 | 1 | 3
+INPUTMC | 1 | 3 | 0
 INPUTP | 1 | 49
 EQ | 1 | 
    start_shifting/start_shifting_RSTF__$INT = cpu_Nres & !shiftdone;
 
-MACROCELL | 3 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
+MACROCELL | 2 | 17 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
 ATTRIBUTES | 133888 | 0
-OUTPUTMC | 1 | 2 | 8
+OUTPUTMC | 1 | 1 | 8
 INPUTS | 4 | ier  | tc  | slaveinten  | spi_int
-INPUTMC | 3 | 3 | 8 | 3 | 1 | 0 | 8
+INPUTMC | 3 | 3 | 17 | 1 | 3 | 0 | 8
 INPUTP | 1 | 7
 EQ | 2 | 
    cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST = ier & tc
@@ -651,52 +701,50 @@ EQ | 2 |
 MACROCELL | 1 | 0 | EXP6_
 ATTRIBUTES | 2048 | 0
 OUTPUTMC | 1 | 1 | 1
-INPUTS | 10 | shiftcnt<3>  | shiftcnt<2>  | shiftcnt<1>  | shiftdone  | spidataout<0>  | shifting2  | spidataout<2>  | spidataout<3>  | spidataout<4>  | spidataout<7>
-INPUTMC | 10 | 1 | 14 | 1 | 15 | 1 | 16 | 1 | 3 | 0 | 3 | 1 | 2 | 0 | 1 | 3 | 7 | 3 | 6 | 3 | 3
+INPUTS | 10 | shiftcnt<3>  | shiftcnt<2>  | shiftcnt<1>  | shiftdone  | spidataout<2>  | shifting2  | spidataout<3>  | spidataout<5>  | spidataout<6>  | spidataout<7>
+INPUTMC | 10 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 0 | 1 | 1 | 2 | 0 | 0 | 3 | 6 | 3 | 5 | 3 | 3
 EXPORTS | 1 | 1 | 1
 EQ | 10 | 
-       EXP6_.EXP  =  shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & 
-	!shiftdone & !spidataout<0> & shifting2
-	# shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & 
+       EXP6_.EXP  =  shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & 
 	!shiftdone & !spidataout<2> & shifting2
 	# shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & 
 	!shiftdone & !spidataout<3> & shifting2
-	# !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & 
-	!shiftdone & !spidataout<4> & shifting2
+	# !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & 
+	!shiftdone & !spidataout<5> & shifting2
+	# !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & 
+	!shiftdone & !spidataout<6> & shifting2
 	# !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & 
 	!shiftdone & !spidataout<7> & shifting2
 
-MACROCELL | 3 | 15 | EXP7_
-ATTRIBUTES | 2048 | 0
-OUTPUTMC | 1 | 3 | 16
-INPUTS | 5 | cpu_Nres  | cpha  | shiftcnt<0>  | shiftdone  | shifting2
-INPUTMC | 4 | 0 | 17 | 1 | 4 | 1 | 3 | 1 | 2
-INPUTP | 1 | 49
-EXPORTS | 1 | 3 | 16
-EQ | 2 | 
-       EXP7_.EXP  =  cpu_Nres & cpha & !shiftcnt<0> & !shiftdone & 
-	shifting2
-
-PIN | cpu_Nres | 64 | 0 | N/A | 49 | 36 | 1 | 1 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 8 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 3 | 16 | 1 | 14 | 1 | 15 | 1 | 4 | 1 | 16 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 3 | 7 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 1 | 17 | 3 | 15
-PIN | cpu_rnw | 64 | 0 | N/A | 24 | 28 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 8 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 3 | 7 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
-PIN | Ncs2 | 64 | 0 | N/A | 46 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 8 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 3 | 1 | 0 | 3 | 0 | 2 | 0 | 1 | 3 | 7 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
-PIN | cs1 | 64 | 0 | N/A | 50 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 8 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 3 | 1 | 0 | 3 | 0 | 2 | 0 | 1 | 3 | 7 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
-PIN | cpu_a<0> | 64 | 0 | N/A | 52 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 8 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 3 | 1 | 0 | 3 | 0 | 2 | 0 | 1 | 3 | 7 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
-PIN | cpu_a<1> | 64 | 0 | N/A | 59 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 8 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 3 | 1 | 0 | 3 | 0 | 2 | 0 | 1 | 3 | 7 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
-PIN | spi_miso | 64 | 0 | N/A | 10 | 1 | 1 | 13
+PIN | cpu_Nres | 64 | 0 | N/A | 49 | 35 | 1 | 1 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 1 | 17
+PIN | Ncs2 | 64 | 0 | N/A | 46 | 30 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 2 | 14 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
+PIN | cpu_rnw | 64 | 0 | N/A | 24 | 28 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
+PIN | cpu_a<0> | 64 | 0 | N/A | 52 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
+PIN | cpu_a<1> | 64 | 0 | N/A | 59 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
+PIN | spi_miso | 64 | 0 | N/A | 10 | 1 | 3 | 11
+PIN | nio_stb | 64 | 0 | N/A | 9 | 3 | 2 | 14 | 2 | 16 | 2 | 8
+PIN | a9 | 64 | 0 | N/A | 89 | 2 | 2 | 16 | 3 | 4
+PIN | a8 | 64 | 0 | N/A | 88 | 2 | 2 | 16 | 3 | 1
+PIN | a10 | 64 | 0 | N/A | 90 | 2 | 2 | 16 | 3 | 7
 PIN | cpu_Nphi2 | 64 | 0 | N/A | 20 | 9 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16 | 1 | 5
-PIN | spi_int | 64 | 0 | N/A | 7 | 2 | 0 | 16 | 3 | 0
-PIN | extclk | 64 | 0 | N/A | 21 | 1 | 1 | 5
+PIN | nio_sel | 64 | 0 | N/A | 3 | 5 | 2 | 14 | 3 | 7 | 3 | 1 | 3 | 4 | 2 | 8
+PIN | spi_int | 64 | 0 | N/A | 7 | 2 | 0 | 16 | 2 | 17
+PIN | extclk | 8256 | 0 | N/A | 21 | 2 | 1 | 5 | 2 | 16
 PIN | spi_mosi | 536871040 | 0 | N/A | 87
 PIN | spi_Nsel | 536871040 | 0 | N/A | 68
 PIN | spi_sclk | 536871040 | 0 | N/A | 83
+PIN | ng | 536871040 | 0 | N/A | 50
+PIN | b10 | 536871040 | 0 | N/A | 65
+PIN | b8 | 536871040 | 0 | N/A | 62
+PIN | b9 | 536871040 | 0 | N/A | 63
 PIN | led | 536871040 | 0 | N/A | 72
-PIN | cpu_Nirq | 536871040 | 0 | N/A | 38
-PIN | cpu_d<3> | 536870976 | 0 | N/A | 26 | 2 | 0 | 6 | 3 | 7
-PIN | cpu_d<5> | 536870976 | 0 | N/A | 29 | 1 | 3 | 5
-PIN | cpu_d<6> | 536870976 | 0 | N/A | 31 | 2 | 3 | 8 | 3 | 4
+PIN | noe | 536871040 | 0 | N/A | 38
+PIN | cpu_Nirq | 536871040 | 0 | N/A | 92
+PIN | cpu_d<3> | 536870976 | 0 | N/A | 26 | 2 | 0 | 6 | 0 | 0
+PIN | cpu_d<5> | 536870976 | 0 | N/A | 29 | 1 | 3 | 6
+PIN | cpu_d<6> | 536870976 | 0 | N/A | 31 | 2 | 3 | 17 | 3 | 5
 PIN | cpu_d<7> | 536870976 | 0 | N/A | 33 | 1 | 3 | 3
 PIN | cpu_d<0> | 536870976 | 0 | N/A | 12 | 4 | 3 | 10 | 0 | 17 | 0 | 13 | 0 | 3
 PIN | cpu_d<1> | 536870976 | 0 | N/A | 13 | 3 | 0 | 15 | 0 | 12 | 0 | 2
 PIN | cpu_d<2> | 536870976 | 0 | N/A | 15 | 3 | 0 | 10 | 0 | 11 | 0 | 1
-PIN | cpu_d<4> | 536870976 | 0 | N/A | 27 | 3 | 0 | 9 | 0 | 8 | 3 | 6
+PIN | cpu_d<4> | 536870976 | 0 | N/A | 27 | 3 | 0 | 9 | 0 | 8 | 3 | 8
diff --git a/spi6502b.ngc b/spi6502b.ngc
index 6cd68ec..b81ac5d 100644
--- a/spi6502b.ngc
+++ b/spi6502b.ngc
@@ -1,3 +1,3 @@
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.2e
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f5=02Bh96Fkc:k11?6=3`8=6=44oc194?=zj82i6=4<:183!e4211Co85Gdb9j60<722c9:7>5;n`0>5<<uk;3o7>53;294~"d;3h=7Em:;If`?l422900e?850;9lf6<722wi=:j50;194?6|,j9146Fl5:Jgg>o5=3:17d<9:188kg5=831vn<6?:181>5<7s-i86?o4Hb78Lae<a;>1<75`b283>>{e91;1<7<50;2x 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\ No newline at end of file
diff --git a/spi6502b.ngd b/spi6502b.ngd
index 075820f..e54bbae 100644
--- a/spi6502b.ngd
+++ b/spi6502b.ngd
@@ -1,3 +1,3 @@
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.2e
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\ No newline at end of file
diff --git a/spi6502b.ngr b/spi6502b.ngr
index 479932a..f462c34 100644
--- a/spi6502b.ngr
+++ b/spi6502b.ngr
@@ -1,3 +1,3 @@
 XILINX-XDB 0.1 STUB 0.1 ASCII
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\ No newline at end of file
diff --git a/spi6502b.pnx b/spi6502b.pnx
index b04911f..4b243e9 100644
--- a/spi6502b.pnx
+++ b/spi6502b.pnx
@@ -15,4 +15,4 @@
   sr     (SLOW|FAST|slow|fast) "SLOW"
   dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
 ]>
-<ibis><part pkg="PC44" spg="-10" arch="xc9500xl" device="XC9572XL"/><pin nm="cpu_Nres" no="19" dir="input"/><pin nm="cpu_rnw" no="7" dir="input"/><pin nm="Ncs2" no="18" dir="input"/><pin nm="cs1" no="20" dir="input"/><pin nm="cpu_a&lt;0&gt;" no="22" dir="input"/><pin nm="cpu_a&lt;1&gt;" no="24" dir="input"/><pin nm="spi_miso" no="44" dir="input"/><pin nm="cpu_Nphi2" no="5" dir="input"/><pin nm="spi_int" no="42" dir="input"/><pin nm="extclk" no="6" dir="input"/><pin nm="spi_mosi" no="35" sr="fast" dir="output"/><pin nm="spi_Nsel" no="28" sr="fast" dir="output"/><pin nm="spi_sclk" no="34" sr="fast" dir="output"/><pin nm="led" no="29" sr="fast" dir="output"/><pin nm="cpu_Nirq" no="14" sr="fast" dir="output"/><pin nm="cpu_d&lt;3&gt;" no="8" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;5&gt;" no="11" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;6&gt;" no="12" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;7&gt;" no="13" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;0&gt;" no="2" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;1&gt;" no="3" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;2&gt;" no="4" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;4&gt;" no="9" sr="fast" dir="bidir"/></ibis>
+<ibis><part pkg="PC44" spg="-10" arch="xc9500xl" device="XC9572XL"/><pin nm="cpu_Nres" no="19" dir="input"/><pin nm="Ncs2" no="18" dir="input"/><pin nm="cpu_rnw" no="7" dir="input"/><pin nm="cpu_a&lt;0&gt;" no="22" dir="input"/><pin nm="cpu_a&lt;1&gt;" no="24" dir="input"/><pin nm="spi_miso" no="44" dir="input"/><pin nm="nio_stb" no="43" dir="input"/><pin nm="a9" no="37" dir="input"/><pin nm="a8" no="36" dir="input"/><pin nm="a10" no="38" dir="input"/><pin nm="cpu_Nphi2" no="5" dir="input"/><pin nm="nio_sel" no="40" dir="input"/><pin nm="spi_int" no="42" dir="input"/><pin nm="extclk" no="6" dir="input"/><pin nm="spi_mosi" no="35" sr="fast" dir="output"/><pin nm="spi_Nsel" no="28" sr="fast" dir="output"/><pin nm="spi_sclk" no="34" sr="fast" dir="output"/><pin nm="ng" no="20" sr="fast" dir="output"/><pin nm="b10" no="27" sr="fast" dir="output"/><pin nm="b8" no="25" sr="fast" dir="output"/><pin nm="b9" no="26" sr="fast" dir="output"/><pin nm="led" no="29" sr="fast" dir="output"/><pin nm="noe" no="14" sr="fast" dir="output"/><pin nm="cpu_Nirq" no="39" sr="fast" dir="output"/><pin nm="cpu_d&lt;3&gt;" no="8" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;5&gt;" no="11" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;6&gt;" no="12" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;7&gt;" no="13" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;0&gt;" no="2" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;1&gt;" no="3" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;2&gt;" no="4" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;4&gt;" no="9" sr="fast" dir="bidir"/></ibis>
diff --git a/spi6502b.prj b/spi6502b.prj
index dcf3158..7d4ebfb 100644
--- a/spi6502b.prj
+++ b/spi6502b.prj
@@ -1 +1,2 @@
+vhdl work address_decoder.vhf
 vhdl work SPI6502B1.1.vhd
diff --git a/spi6502b.rpt b/spi6502b.rpt
index 8088d76..7880cd0 100644
--- a/spi6502b.rpt
+++ b/spi6502b.rpt
@@ -1,7 +1,7 @@
  
 cpldfit:  version G.38                              Xilinx Inc.
                                   Fitter Report
-Design Name: spi6502b                            Date:  5- 6-2017,  5:47PM
+Design Name: spi6502b                            Date:  5-11-2017,  2:09AM
 Device Used: XC9572XL-10-PC44
 Fitting Status: Successful
 
@@ -9,38 +9,38 @@ Fitting Status: Successful
 
 Macrocells     Product Terms    Registers      Pins           Function Block 
 Used           Used             Used           Used           Inputs Used    
-50 /72  ( 69%) 202 /360  ( 56%) 37 /72  ( 51%) 23 /34  ( 68%) 106/216 ( 49%)
+56 /72  ( 78%) 209 /360  ( 58%) 38 /72  ( 53%) 32 /34  ( 94%) 116/216 ( 54%)
 
 PIN RESOURCES:
 
 Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
 ------------------------------------|---------------------------------------
-Input         :   10          10    |  I/O              :    19        9
-Output        :    5           5    |  GCK/IO           :     3        0
-Bidirectional :    8           8    |  GTS/IO           :     1        1
-GCK           :    0           0    |  GSR/IO           :     0        1
+Input         :   13          13    |  I/O              :    26        2
+Output        :   10          10    |  GCK/IO           :     3        0
+Bidirectional :    8           8    |  GTS/IO           :     2        0
+GCK           :    1           1    |  GSR/IO           :     1        0
 GTS           :    0           0    |
 GSR           :    0           0    |
                  ----        ----
-        Total     23          23
+        Total     32          32
 
 MACROCELL RESOURCES:
 
 Total Macrocells Available                    72
-Registered Macrocells                         37
-Non-registered Macrocell driving I/O          10
+Registered Macrocells                         38
+Non-registered Macrocell driving I/O          15
 
 GLOBAL RESOURCES:
 
-Global clock net(s) unused.
+Signal 'extclk' mapped onto global clock net GCK2.
 Global output enable net(s) unused.
 Global set/reset net(s) unused.
 
 POWER DATA:
 
-There are 50 macrocells in high performance mode (MCHP).
+There are 56 macrocells in high performance mode (MCHP).
 There are 0 macrocells in low power mode (MCLP).
-There are a total of 50 macrocells used (MC).
+There are a total of 56 macrocells used (MC).
 
 End of Resource Summary
 *************** Summary of Required Resources ******************
@@ -48,68 +48,78 @@ End of Resource Summary
 ** LOGIC **
 Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin       Reg Init
 Name                Pt      Used            Mode Rate #    Type      Use       State
-$OpTx$INV$22__$INT  3       5       FB2_6   STD       37   I/O       (b)       
-cpha                5       8       FB1_18  STD            (b)       (b)       RESET
-cpol                5       8       FB1_16  STD            (b)       (b)       RESET
-cpu_Nirq            1       1       FB3_9   STD  FAST 14   I/O       O         
-cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST                    2       4       FB4_1   STD            (b)       (b)       
-cpu_d<0>            5       10      FB1_5   STD  FAST 2    I/O       I/O       
-cpu_d<1>            4       9       FB1_6   STD  FAST 3    I/O       I/O       
-cpu_d<2>            4       9       FB1_8   STD  FAST 4    I/O       I/O       
-cpu_d<3>            3       8       FB1_15  STD  FAST 8    I/O       I/O       
-cpu_d<4>            5       10      FB1_17  STD  FAST 9    I/O       I/O       
-cpu_d<5>            4       9       FB3_2   STD  FAST 11   I/O       I/O       
-cpu_d<6>            3       8       FB3_5   STD  FAST 12   I/O       I/O       
-cpu_d<7>            3       8       FB3_8   STD  FAST 13   I/O       I/O       
-divisor<0>          5       8       FB1_14  STD       7    GCK/I/O   I         RESET
-divisor<1>          5       8       FB1_13  STD            (b)       (b)       RESET
-divisor<2>          5       8       FB1_12  STD            (b)       (b)       RESET
-ece                 5       8       FB1_11  STD       6    GCK/I/O   I         RESET
-frx                 5       8       FB1_10  STD            (b)       (b)       RESET
-ier                 5       8       FB4_9   STD            (b)       (b)       RESET
+$OpTx$INV$24__$INT  3       5       FB2_6   STD       37   I/O       I         
+add_dec/XLXN_11     1       4       FB3_17  STD       22   I/O       I         RESET
+b10                 1       2       FB4_8   STD  FAST 27   I/O       O         
+b8                  1       2       FB4_2   STD  FAST 25   I/O       O         
+b9                  1       2       FB4_5   STD  FAST 26   I/O       O         
+cpha                5       7       FB1_18  STD            (b)       (b)       RESET
+cpol                5       7       FB1_16  STD            (b)       (b)       RESET
+cpu_Nirq            1       1       FB2_9   STD  FAST 39   GSR/I/O   O         
+cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST                    2       4       FB3_18  STD            (b)       (b)       
+cpu_d<0>            5       9       FB1_5   STD  FAST 2    I/O       I/O       
+cpu_d<1>            4       8       FB1_6   STD  FAST 3    I/O       I/O       
+cpu_d<2>            4       8       FB1_8   STD  FAST 4    I/O       I/O       
+cpu_d<3>            3       7       FB1_15  STD  FAST 8    I/O       I/O       
+cpu_d<4>            5       9       FB1_17  STD  FAST 9    I/O       I/O       
+cpu_d<5>            4       8       FB3_2   STD  FAST 11   I/O       I/O       
+cpu_d<6>            3       7       FB3_5   STD  FAST 12   I/O       I/O       
+cpu_d<7>            3       7       FB3_8   STD  FAST 13   I/O       I/O       
+divisor<0>          5       7       FB1_14  STD       7    GCK/I/O   I         RESET
+divisor<1>          5       7       FB1_13  STD            (b)       (b)       RESET
+divisor<2>          5       7       FB1_12  STD            (b)       (b)       RESET
+ece                 5       7       FB1_11  STD       6    GCK/I/O   GCK/I     RESET
+frx                 5       7       FB1_10  STD            (b)       (b)       RESET
+ier                 5       7       FB4_18  STD            (b)       (b)       RESET
 led                 1       3       FB4_14  STD  FAST 29   I/O       O         
-shiftcnt<0>         3       4       FB2_5   STD       36   I/O       (b)       RESET
-shiftcnt<1>         4       5       FB2_17  STD       44   I/O       I         RESET
-shiftcnt<2>         4       6       FB2_16  STD            (b)       (b)       RESET
-shiftcnt<3>         4       7       FB2_15  STD       43   I/O       (b)       RESET
-shiftdone           3       6       FB2_4   STD            (b)       (b)       RESET
+ng                  1       3       FB3_15  STD  FAST 20   I/O       O         
+noe                 2       3       FB3_9   STD  FAST 14   I/O       O         
+shiftcnt<0>         3       4       FB2_5   STD       36   I/O       I         RESET
+shiftcnt<1>         4       5       FB4_16  STD            (b)       (b)       RESET
+shiftcnt<2>         4       6       FB4_15  STD       33   I/O       (b)       RESET
+shiftcnt<3>         4       7       FB4_13  STD            (b)       (b)       RESET
+shiftdone           3       6       FB4_1   STD            (b)       (b)       RESET
 shifting2           2       3       FB2_3   STD            (b)       (b)       RESET
-slaveinten          5       8       FB1_9   STD       5    GCK/I/O   I         RESET
-spi_Nsel            5       8       FB4_11  STD  FAST 28   I/O       O         RESET
+slaveinten          5       7       FB1_9   STD       5    GCK/I/O   I         RESET
+spi_Nsel            5       7       FB4_11  STD  FAST 28   I/O       O         RESET
 spi_mosi            11      16      FB2_2   STD  FAST 35   I/O       O         RESET
 spi_sclk            6       7       FB4_17  STD  FAST 34   I/O       O         RESET
-spidatain<0>        4       6       FB2_14  STD       42   GTS/I/O   I         RESET
-spidatain<1>        4       5       FB2_13  STD            (b)       (b)       RESET
-spidatain<2>        4       5       FB2_12  STD            (b)       (b)       RESET
-spidatain<3>        4       5       FB2_11  STD       40   GTS/I/O   (b)       RESET
-spidatain<4>        4       5       FB2_10  STD            (b)       (b)       RESET
-spidatain<5>        4       5       FB2_9   STD       39   GSR/I/O   (b)       RESET
-spidatain<6>        4       5       FB2_8   STD       38   I/O       (b)       RESET
+spidatain<0>        4       6       FB4_12  STD            (b)       (b)       RESET
+spidatain<1>        4       5       FB4_10  STD            (b)       (b)       RESET
+spidatain<2>        4       5       FB2_13  STD            (b)       (b)       RESET
+spidatain<3>        4       5       FB2_12  STD            (b)       (b)       RESET
+spidatain<4>        4       5       FB2_11  STD       40   GTS/I/O   I         RESET
+spidatain<5>        4       5       FB2_10  STD            (b)       (b)       RESET
+spidatain<6>        4       5       FB2_8   STD       38   I/O       I         RESET
 spidatain<7>        4       5       FB2_7   STD            (b)       (b)       RESET
-spidataout<0>       4       8       FB1_4   STD            (b)       (b)       RESET
-spidataout<1>       4       8       FB1_3   STD            (b)       (b)       RESET
-spidataout<2>       4       8       FB1_2   STD       1    I/O       (b)       RESET
-spidataout<3>       4       8       FB4_8   STD       27   I/O       (b)       RESET
-spidataout<4>       4       8       FB4_7   STD            (b)       (b)       RESET
-spidataout<5>       4       8       FB4_6   STD            (b)       (b)       RESET
-spidataout<6>       4       8       FB4_5   STD       26   I/O       (b)       RESET
-spidataout<7>       4       8       FB4_4   STD            (b)       (b)       RESET
-start_shifting      4       8       FB4_3   STD            (b)       (b)       RESET
+spidataout<0>       4       7       FB1_4   STD            (b)       (b)       RESET
+spidataout<1>       4       7       FB1_3   STD            (b)       (b)       RESET
+spidataout<2>       4       7       FB1_2   STD       1    I/O       (b)       RESET
+spidataout<3>       4       7       FB1_1   STD            (b)       (b)       RESET
+spidataout<4>       4       7       FB4_9   STD            (b)       (b)       RESET
+spidataout<5>       4       7       FB4_7   STD            (b)       (b)       RESET
+spidataout<6>       4       7       FB4_6   STD            (b)       (b)       RESET
+spidataout<7>       4       7       FB4_4   STD            (b)       (b)       RESET
+start_shifting      4       7       FB4_3   STD            (b)       (b)       RESET
 start_shifting/start_shifting_RSTF__$INT                    1       2       FB2_18  STD            (b)       (b)       
-tc                  3       5       FB4_2   STD       25   I/O       (b)       RESET
-tmo                 5       8       FB1_7   STD            (b)       (b)       RESET
+tc                  3       4       FB2_4   STD            (b)       (b)       RESET
+tmo                 5       7       FB1_7   STD            (b)       (b)       RESET
 
 ** INPUTS **
 Signal                              Loc               Pin  Pin       Pin
 Name                                                  #    Type      Use
 Ncs2                                FB3_11            18   I/O       I
+a10                                 FB2_8             38   I/O       I
+a8                                  FB2_5             36   I/O       I
+a9                                  FB2_6             37   I/O       I
 cpu_Nphi2                           FB1_9             5    GCK/I/O   I
 cpu_Nres                            FB3_14            19   I/O       I
 cpu_a<0>                            FB3_17            22   I/O       I
 cpu_a<1>                            FB3_16            24   I/O       I
 cpu_rnw                             FB1_14            7    GCK/I/O   I
-cs1                                 FB3_15            20   I/O       I
-extclk                              FB1_11            6    GCK/I/O   I
+extclk                              FB1_11            6    GCK/I/O   GCK/I
+nio_sel                             FB2_11            40   GTS/I/O   I
+nio_stb                             FB2_15            43   I/O       I
 spi_int                             FB2_14            42   GTS/I/O   I
 spi_miso                            FB2_17            44   I/O       I
 
@@ -118,18 +128,18 @@ End of Resources
 *********************Function Block Resource Summary***********************
 Function    # of        FB Inputs   Signals     Total       O/IO      IO    
 Block       Macrocells  Used        Used        Pt Used     Req       Avail 
-FB1          17          31          31           78         0/5        9   
-FB2          17          30          30           67         1/0        9   
-FB3           4          14          14           11         1/3        9   
-FB4          12          31          31           46         3/0        7   
+FB1          18          31          31           82         0/5        9   
+FB2          13          31          31           48         2/0        9   
+FB3           7          20          20           16         2/3        9   
+FB4          18          34          34           63         6/0        7   
             ----                                -----       -----     ----- 
-             50                                  202         5/8       34   
+             56                                  209        10/8       34   
 *********************************** FB1 ***********************************
 Number of function block inputs used/remaining:               31/23
 Number of signals used by logic mapping into function block:  31
 Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
 Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
-(unused)              0       0     0   5     FB1_1               (b)     
+spidataout<3>         4       0     0   1     FB1_1   STD         (b)     (b)
 spidataout<2>         4       0     0   1     FB1_2   STD   1     I/O     (b)
 spidataout<1>         4       0     0   1     FB1_3   STD         (b)     (b)
 spidataout<0>         4       0     0   1     FB1_4   STD         (b)     (b)
@@ -139,7 +149,7 @@ tmo                   5       0     0   0     FB1_7   STD         (b)     (b)
 cpu_d<2>              4       0     0   1     FB1_8   STD   4     I/O     I/O
 slaveinten            5       0     0   0     FB1_9   STD   5     GCK/I/O I
 frx                   5       0     0   0     FB1_10  STD         (b)     (b)
-ece                   5       0     0   0     FB1_11  STD   6     GCK/I/O I
+ece                   5       0     0   0     FB1_11  STD   6     GCK/I/O GCK/I
 divisor<2>            5       0     0   0     FB1_12  STD         (b)     (b)
 divisor<1>            5       0     0   0     FB1_13  STD         (b)     (b)
 divisor<0>            5       0     0   0     FB1_14  STD   7     GCK/I/O I
@@ -149,37 +159,38 @@ cpu_d<4>              5       0     0   0     FB1_17  STD   9     I/O     I/O
 cpha                  5       0     0   0     FB1_18  STD         (b)     (b)
 
 Signals Used by Logic in Function Block
-  1: cpu_d<0>.PIN      12: cpu_a<1>          22: spi_int 
-  2: cpu_d<1>.PIN      13: cpu_rnw           23: spidatain<0> 
-  3: cpu_d<2>.PIN      14: cs1               24: spidatain<1> 
-  4: cpu_d<3>.PIN      15: divisor<0>        25: spidatain<2> 
-  5: cpu_d<4>.PIN      16: divisor<1>        26: spidatain<3> 
-  6: Ncs2              17: divisor<2>        27: spidatain<4> 
-  7: cpha              18: ece               28: spidataout<0> 
-  8: cpol              19: frx               29: spidataout<1> 
-  9: cpu_Nphi2         20: slaveinten        30: spidataout<2> 
- 10: cpu_Nres          21: spi_Nsel          31: tmo 
+  1: cpu_d<0>.PIN      12: cpu_a<1>          22: spidatain<0> 
+  2: cpu_d<1>.PIN      13: cpu_rnw           23: spidatain<1> 
+  3: cpu_d<2>.PIN      14: divisor<0>        24: spidatain<2> 
+  4: cpu_d<3>.PIN      15: divisor<1>        25: spidatain<3> 
+  5: cpu_d<4>.PIN      16: divisor<2>        26: spidatain<4> 
+  6: Ncs2              17: ece               27: spidataout<0> 
+  7: cpha              18: frx               28: spidataout<1> 
+  8: cpol              19: slaveinten        29: spidataout<2> 
+  9: cpu_Nphi2         20: spi_Nsel          30: spidataout<3> 
+ 10: cpu_Nres          21: spi_int           31: tmo 
  11: cpu_a<0>         
 
 Signal                        1         2         3         4 Signals FB
 Name                0----+----0----+----0----+----0----+----0 Used    Inputs
-spidataout<2>        ..X..X...XXXXX...............X.......... 8       8
-spidataout<1>        .X...X...XXXXX..............X........... 8       8
-spidataout<0>        X....X...XXXXX.............X............ 8       8
-cpu_d<0>             .....XX.X.XXXXX.....X.X................. 10      10
-cpu_d<1>             .....X.XX.XXXX.X.......X................ 9       9
-tmo                  ...X.X...XXXXX................X......... 8       8
-cpu_d<2>             .....X..X.XXXX..XX......X............... 9       9
-slaveinten           ....XX...XXXXX.....X.................... 8       8
-frx                  ....XX...XXXXX....X..................... 8       8
-ece                  ..X..X...XXXXX...X...................... 8       8
-divisor<2>           ..X..X...XXXXX..X....................... 8       8
-divisor<1>           .X...X...XXXXX.X........................ 8       8
-divisor<0>           X....X...XXXXXX......................... 8       8
-cpu_d<3>             .....X..X.XXXX...........X....X......... 8       8
-cpol                 .X...X.X.XXXXX.......................... 8       8
-cpu_d<4>             .....X..X.XXXX....XX.X....X............. 10      10
-cpha                 X....XX..XXXXX.......................... 8       8
+spidataout<3>        ...X.X...XXXX................X.......... 7       7
+spidataout<2>        ..X..X...XXXX...............X........... 7       7
+spidataout<1>        .X...X...XXXX..............X............ 7       7
+spidataout<0>        X....X...XXXX.............X............. 7       7
+cpu_d<0>             .....XX.X.XXXX.....X.X.................. 9       9
+cpu_d<1>             .....X.XX.XXX.X.......X................. 8       8
+tmo                  ...X.X...XXXX.................X......... 7       7
+cpu_d<2>             .....X..X.XXX..XX......X................ 8       8
+slaveinten           ....XX...XXXX.....X..................... 7       7
+frx                  ....XX...XXXX....X...................... 7       7
+ece                  ..X..X...XXXX...X....................... 7       7
+divisor<2>           ..X..X...XXXX..X........................ 7       7
+divisor<1>           .X...X...XXXX.X......................... 7       7
+divisor<0>           X....X...XXXXX.......................... 7       7
+cpu_d<3>             .....X..X.XXX...........X.....X......... 7       7
+cpol                 .X...X.X.XXXX........................... 7       7
+cpu_d<4>             .....X..X.XXX....XX.X....X.............. 9       9
+cpha                 X....XX..XXXX........................... 7       7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
 Legend:
@@ -197,63 +208,61 @@ X(@) - Signal used as input (wire-AND input) to the macrocell logic.
     The number of Signals Used may exceed the number of FB Inputs Used due
     to wire-ANDing in the switch matrix.
 *********************************** FB2 ***********************************
-Number of function block inputs used/remaining:               30/24
-Number of signals used by logic mapping into function block:  30
+Number of function block inputs used/remaining:               31/23
+Number of signals used by logic mapping into function block:  31
 Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
 Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
 (unused)              0       0   \/5   0     FB2_1               (b)     (b)
 spi_mosi             11       6<-   0   0     FB2_2   STD   35    I/O     O
 shifting2             2       0   /\1   2     FB2_3   STD         (b)     (b)
-shiftdone             3       0     0   2     FB2_4   STD         (b)     (b)
-shiftcnt<0>           3       0     0   2     FB2_5   STD   36    I/O     (b)
-$OpTx$INV$22__$INT    3       0     0   2     FB2_6   STD   37    I/O     (b)
+tc                    3       0     0   2     FB2_4   STD         (b)     (b)
+shiftcnt<0>           3       0     0   2     FB2_5   STD   36    I/O     I
+$OpTx$INV$24__$INT    3       0     0   2     FB2_6   STD   37    I/O     I
 spidatain<7>          4       0     0   1     FB2_7   STD         (b)     (b)
-spidatain<6>          4       0     0   1     FB2_8   STD   38    I/O     (b)
-spidatain<5>          4       0     0   1     FB2_9   STD   39    GSR/I/O (b)
-spidatain<4>          4       0     0   1     FB2_10  STD         (b)     (b)
-spidatain<3>          4       0     0   1     FB2_11  STD   40    GTS/I/O (b)
-spidatain<2>          4       0     0   1     FB2_12  STD         (b)     (b)
-spidatain<1>          4       0     0   1     FB2_13  STD         (b)     (b)
-spidatain<0>          4       0     0   1     FB2_14  STD   42    GTS/I/O I
-shiftcnt<3>           4       0     0   1     FB2_15  STD   43    I/O     (b)
-shiftcnt<2>           4       0     0   1     FB2_16  STD         (b)     (b)
-shiftcnt<1>           4       0     0   1     FB2_17  STD   44    I/O     I
+spidatain<6>          4       0     0   1     FB2_8   STD   38    I/O     I
+cpu_Nirq              1       0     0   4     FB2_9   STD   39    GSR/I/O O
+spidatain<5>          4       0     0   1     FB2_10  STD         (b)     (b)
+spidatain<4>          4       0     0   1     FB2_11  STD   40    GTS/I/O I
+spidatain<3>          4       0     0   1     FB2_12  STD         (b)     (b)
+spidatain<2>          4       0     0   1     FB2_13  STD         (b)     (b)
+(unused)              0       0     0   5     FB2_14        42    GTS/I/O I
+(unused)              0       0     0   5     FB2_15        43    I/O     I
+(unused)              0       0     0   5     FB2_16              (b)     
+(unused)              0       0     0   5     FB2_17        44    I/O     I
 start_shifting/start_shifting_RSTF__$INT
                       1       0     0   4     FB2_18  STD         (b)     (b)
 
 Signals Used by Logic in Function Block
-  1: $OpTx$INV$22__$INT 
-                       11: shifting2         21: spidataout<0> 
-  2: cpu_Nphi2         12: spi_Nsel          22: spidataout<1> 
-  3: cpu_Nres          13: spi_miso          23: spidataout<2> 
-  4: ece               14: spidatain<0>      24: spidataout<3> 
-  5: extclk            15: spidatain<1>      25: spidataout<4> 
-  6: shiftcnt<0>       16: spidatain<2>      26: spidataout<5> 
-  7: shiftcnt<1>       17: spidatain<3>      27: spidataout<6> 
-  8: shiftcnt<2>       18: spidatain<4>      28: spidataout<7> 
-  9: shiftcnt<3>       19: spidatain<5>      29: start_shifting 
- 10: shiftdone         20: spidatain<6>      30: tmo 
+  1: $OpTx$INV$24__$INT 
+                       12: shiftcnt<2>       22: spidataout<0> 
+  2: Ncs2              13: shiftcnt<3>       23: spidataout<1> 
+  3: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 
+                       14: shiftdone         24: spidataout<2> 
+  4: cpu_Nphi2         15: shifting2         25: spidataout<3> 
+  5: cpu_Nres          16: spidatain<1>      26: spidataout<4> 
+  6: cpu_a<0>          17: spidatain<2>      27: spidataout<5> 
+  7: cpu_a<1>          18: spidatain<3>      28: spidataout<6> 
+  8: ece               19: spidatain<4>      29: spidataout<7> 
+  9: extclk            20: spidatain<5>      30: start_shifting 
+ 10: shiftcnt<0>       21: spidatain<6>      31: tmo 
+ 11: shiftcnt<1>      
 
 Signal                        1         2         3         4 Signals FB
 Name                0----+----0----+----0----+----0----+----0 Used    Inputs
-spi_mosi             X.X...XXXXX.........XXXXXXXX.X.......... 16      16
-shifting2            X........X..................X........... 3       3
-shiftdone            X.X..XXXX............................... 6       6
-shiftcnt<0>          X.X..X....X............................. 4       4
-$OpTx$INV$22__$INT   .X.XX.....X.................X........... 5       5
-spidatain<7>         X.X..X....X........X.................... 5       5
-spidatain<6>         X.X..X....X.......X..................... 5       5
-spidatain<5>         X.X..X....X......X...................... 5       5
-spidatain<4>         X.X..X....X.....X....................... 5       5
-spidatain<3>         X.X..X....X....X........................ 5       5
-spidatain<2>         X.X..X....X...X......................... 5       5
-spidatain<1>         X.X..X....X..X.......................... 5       5
-spidatain<0>         X.X..X....XXX........................... 6       6
-shiftcnt<3>          X.X..XXXX.X............................. 7       7
-shiftcnt<2>          X.X..XXX..X............................. 6       6
-shiftcnt<1>          X.X..XX...X............................. 5       5
+spi_mosi             X...X.....XXXXX......XXXXXXXX.X......... 16      16
+shifting2            X............X...............X.......... 3       3
+tc                   .X...XX......X.......................... 4       4
+shiftcnt<0>          X...X....X....X......................... 4       4
+$OpTx$INV$24__$INT   ...X...XX.....X..............X.......... 5       5
+spidatain<7>         X...X....X....X.....X................... 5       5
+spidatain<6>         X...X....X....X....X.................... 5       5
+cpu_Nirq             ..X..................................... 1       1
+spidatain<5>         X...X....X....X...X..................... 5       5
+spidatain<4>         X...X....X....X..X...................... 5       5
+spidatain<3>         X...X....X....X.X....................... 5       5
+spidatain<2>         X...X....X....XX........................ 5       5
 start_shifting/start_shifting_RSTF__$INT 
-                     ..X......X.............................. 2       2
+                     ....X........X.......................... 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
 Legend:
@@ -271,8 +280,8 @@ X(@) - Signal used as input (wire-AND input) to the macrocell logic.
     The number of Signals Used may exceed the number of FB Inputs Used due
     to wire-ANDing in the switch matrix.
 *********************************** FB3 ***********************************
-Number of function block inputs used/remaining:               14/40
-Number of signals used by logic mapping into function block:  14
+Number of function block inputs used/remaining:               20/34
+Number of signals used by logic mapping into function block:  20
 Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
 Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
 (unused)              0       0     0   5     FB3_1               (b)     
@@ -283,31 +292,37 @@ cpu_d<6>              3       0     0   2     FB3_5   STD   12    I/O     I/O
 (unused)              0       0     0   5     FB3_6               (b)     
 (unused)              0       0     0   5     FB3_7               (b)     
 cpu_d<7>              3       0     0   2     FB3_8   STD   13    I/O     I/O
-cpu_Nirq              1       0     0   4     FB3_9   STD   14    I/O     O
+noe                   2       0     0   3     FB3_9   STD   14    I/O     O
 (unused)              0       0     0   5     FB3_10              (b)     
 (unused)              0       0     0   5     FB3_11        18    I/O     I
 (unused)              0       0     0   5     FB3_12              (b)     
 (unused)              0       0     0   5     FB3_13              (b)     
 (unused)              0       0     0   5     FB3_14        19    I/O     I
-(unused)              0       0     0   5     FB3_15        20    I/O     I
+ng                    1       0     0   4     FB3_15  STD   20    I/O     O
 (unused)              0       0     0   5     FB3_16        24    I/O     I
-(unused)              0       0     0   5     FB3_17        22    I/O     I
-(unused)              0       0     0   5     FB3_18              (b)     
+add_dec/XLXN_11       1       0     0   4     FB3_17  STD   22    I/O     I
+cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
+                      2       0     0   3     FB3_18  STD         (b)     (b)
 
 Signals Used by Logic in Function Block
-  1: Ncs2               6: cpu_rnw           11: spidatain<6> 
-  2: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 
-                        7: cs1               12: spidatain<7> 
-  3: cpu_Nphi2          8: ier               13: start_shifting 
-  4: cpu_a<0>           9: shifting2         14: tc 
-  5: cpu_a<1>          10: spidatain<5>     
+  1: Ncs2               8: cpu_a<1>          15: spi_int 
+  2: a10                9: cpu_rnw           16: spidatain<5> 
+  3: a8                10: ier               17: spidatain<6> 
+  4: a9                11: nio_sel           18: spidatain<7> 
+  5: add_dec/XLXN_11   12: nio_stb           19: start_shifting 
+  6: cpu_Nphi2         13: shifting2         20: tc 
+  7: cpu_a<0>          14: slaveinten       
 
 Signal                        1         2         3         4 Signals FB
 Name                0----+----0----+----0----+----0----+----0 Used    Inputs
-cpu_d<5>             X.XXXXX.XX..X........................... 9       9
-cpu_d<6>             X.XXXXXX..X............................. 8       8
-cpu_d<7>             X.XXXXX....X.X.......................... 8       8
-cpu_Nirq             .X...................................... 1       1
+cpu_d<5>             X....XXXX...X..X..X..................... 8       8
+cpu_d<6>             X....XXXXX......X....................... 7       7
+cpu_d<7>             X....XXXX........X.X.................... 7       7
+noe                  ....X.....XX............................ 3       3
+ng                   X.........XX............................ 3       3
+add_dec/XLXN_11      .XXX.......X............................ 4       4
+cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 
+                     .........X...XX....X.................... 4       4
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
 Legend:
@@ -325,59 +340,64 @@ X(@) - Signal used as input (wire-AND input) to the macrocell logic.
     The number of Signals Used may exceed the number of FB Inputs Used due
     to wire-ANDing in the switch matrix.
 *********************************** FB4 ***********************************
-Number of function block inputs used/remaining:               31/23
-Number of signals used by logic mapping into function block:  31
+Number of function block inputs used/remaining:               34/20
+Number of signals used by logic mapping into function block:  34
 Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
 Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
-cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
-                      2       0     0   3     FB4_1   STD         (b)     (b)
-tc                    3       0     0   2     FB4_2   STD   25    I/O     (b)
+shiftdone             3       0     0   2     FB4_1   STD         (b)     (b)
+b8                    1       0     0   4     FB4_2   STD   25    I/O     O
 start_shifting        4       0     0   1     FB4_3   STD         (b)     (b)
 spidataout<7>         4       0     0   1     FB4_4   STD         (b)     (b)
-spidataout<6>         4       0     0   1     FB4_5   STD   26    I/O     (b)
-spidataout<5>         4       0     0   1     FB4_6   STD         (b)     (b)
-spidataout<4>         4       0     0   1     FB4_7   STD         (b)     (b)
-spidataout<3>         4       0     0   1     FB4_8   STD   27    I/O     (b)
-ier                   5       0     0   0     FB4_9   STD         (b)     (b)
-(unused)              0       0     0   5     FB4_10              (b)     
+b9                    1       0     0   4     FB4_5   STD   26    I/O     O
+spidataout<6>         4       0     0   1     FB4_6   STD         (b)     (b)
+spidataout<5>         4       0     0   1     FB4_7   STD         (b)     (b)
+b10                   1       0     0   4     FB4_8   STD   27    I/O     O
+spidataout<4>         4       0     0   1     FB4_9   STD         (b)     (b)
+spidatain<1>          4       0     0   1     FB4_10  STD         (b)     (b)
 spi_Nsel              5       0     0   0     FB4_11  STD   28    I/O     O
-(unused)              0       0     0   5     FB4_12              (b)     
-(unused)              0       0     0   5     FB4_13              (b)     
+spidatain<0>          4       0     0   1     FB4_12  STD         (b)     (b)
+shiftcnt<3>           4       0     0   1     FB4_13  STD         (b)     (b)
 led                   1       0     0   4     FB4_14  STD   29    I/O     O
-(unused)              0       0     0   5     FB4_15        33    I/O     
-(unused)              0       0   \/1   4     FB4_16              (b)     (b)
+shiftcnt<2>           4       0     0   1     FB4_15  STD   33    I/O     (b)
+shiftcnt<1>           4       0   \/1   0     FB4_16  STD         (b)     (b)
 spi_sclk              6       1<-   0   0     FB4_17  STD   34    I/O     O
-(unused)              0       0     0   5     FB4_18              (b)     
+ier                   5       0     0   0     FB4_18  STD         (b)     (b)
 
 Signals Used by Logic in Function Block
-  1: $OpTx$INV$22__$INT 
-                       12: cpu_a<0>          22: spi_Nsel 
-  2: cpu_d<0>.PIN      13: cpu_a<1>          23: spi_int 
-  3: cpu_d<3>.PIN      14: cpu_rnw           24: spidataout<3> 
-  4: cpu_d<4>.PIN      15: cs1               25: spidataout<4> 
-  5: cpu_d<5>.PIN      16: frx               26: spidataout<5> 
-  6: cpu_d<6>.PIN      17: ier               27: spidataout<6> 
-  7: cpu_d<7>.PIN      18: shiftcnt<0>       28: spidataout<7> 
-  8: Ncs2              19: shiftdone         29: start_shifting 
-  9: cpha              20: shifting2         30: start_shifting/start_shifting_RSTF__$INT 
- 10: cpol              21: slaveinten        31: tc 
- 11: cpu_Nres         
+  1: $OpTx$INV$24__$INT 
+                       13: cpu_Nres          24: shiftdone 
+  2: cpu_d<0>.PIN      14: cpu_a<0>          25: shifting2 
+  3: cpu_d<4>.PIN      15: cpu_a<1>          26: spi_Nsel 
+  4: cpu_d<5>.PIN      16: cpu_rnw           27: spi_miso 
+  5: cpu_d<6>.PIN      17: frx               28: spidatain<0> 
+  6: cpu_d<7>.PIN      18: ier               29: spidataout<4> 
+  7: Ncs2              19: nio_sel           30: spidataout<5> 
+  8: a10               20: shiftcnt<0>       31: spidataout<6> 
+  9: a8                21: shiftcnt<1>       32: spidataout<7> 
+ 10: a9                22: shiftcnt<2>       33: start_shifting 
+ 11: cpha              23: shiftcnt<3>       34: start_shifting/start_shifting_RSTF__$INT 
+ 12: cpol             
 
 Signal                        1         2         3         4 Signals FB
 Name                0----+----0----+----0----+----0----+----0 Used    Inputs
-cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 
-                     ................X...X.X.......X......... 4       4
-tc                   .......X...XX.X...X..................... 5       5
-start_shifting       .......X...XXXXX............XX.......... 8       8
-spidataout<7>        ......XX..XXXXX............X............ 8       8
-spidataout<6>        .....X.X..XXXXX...........X............. 8       8
-spidataout<5>        ....X..X..XXXXX..........X.............. 8       8
-spidataout<4>        ...X...X..XXXXX.........X............... 8       8
-spidataout<3>        ..X....X..XXXXX........X................ 8       8
-ier                  .....X.X..XXXXX.X....................... 8       8
-spi_Nsel             .X.....X..XXXXX......X.................. 8       8
-led                  ...................X.X......X........... 3       3
-spi_sclk             X.......XXX......XXX.................... 7       7
+shiftdone            X...........X......XXXX................. 6       6
+b8                   ........X.........X..................... 2       2
+start_shifting       ......X......XXXX...............XX...... 7       7
+spidataout<7>        .....XX.....XXXX...............X........ 7       7
+b9                   .........X........X..................... 2       2
+spidataout<6>        ....X.X.....XXXX..............X......... 7       7
+spidataout<5>        ...X..X.....XXXX.............X.......... 7       7
+b10                  .......X..........X..................... 2       2
+spidataout<4>        ..X...X.....XXXX............X........... 7       7
+spidatain<1>         X...........X......X....X..X............ 5       5
+spi_Nsel             .X....X.....XXXX.........X.............. 7       7
+spidatain<0>         X...........X......X....XXX............. 6       6
+shiftcnt<3>          X...........X......XXXX.X............... 7       7
+led                  ........................XX......X....... 3       3
+shiftcnt<2>          X...........X......XXX..X............... 6       6
+shiftcnt<1>          X...........X......XX...X............... 5       5
+spi_sclk             X.........XXX......X...XX............... 7       7
+ier                  ....X.X.....XXXX.X...................... 7       7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
 Legend:
@@ -398,23 +418,31 @@ X(@) - Signal used as input (wire-AND input) to the macrocell logic.
 ; Implemented Equations.
 
 
-$OpTx$INV$22__$INT <= ((ece AND NOT extclk)
+$OpTx$INV$24__$INT <= ((ece AND NOT extclk)
 	OR (NOT ece AND NOT cpu_Nphi2)
 	OR (NOT start_shifting AND NOT shifting2));
 
 
 
+FDCPE_add_dec/XLXN_11: FDCPE port map (add_dec/XLXN_11,add_dec/XLXN_11_D,extclk,'0','0');
+add_dec/XLXN_11_D <= (NOT nio_stb AND a9 AND a8 AND a10);
 
 
-FTCPE_cpha: FTCPE port map (cpha,cpha_T,cpha_C,NOT cpu_Nres,'0',NOT cpu_rnw);
+b10 <= (a10 AND nio_sel);
+
+
+b8 <= (a8 AND nio_sel);
+
+
+b9 <= (a9 AND nio_sel);
+
+FTCPE_cpha: FTCPE port map (cpha,cpha_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 cpha_T <= ((cpha AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
 	OR (NOT cpha AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
-cpha_C <= NOT ((cs1 AND NOT Ncs2));
 
-FTCPE_cpol: FTCPE port map (cpol,cpol_T,cpol_C,NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_cpol: FTCPE port map (cpol,cpol_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 cpol_T <= ((cpol AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(1).PIN)
 	OR (NOT cpol AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(1).PIN));
-cpol_C <= NOT ((cs1 AND NOT Ncs2));
 
 
 cpu_Nirq_I <= '0';
@@ -425,128 +453,122 @@ cpu_Nirq_OE <= cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST;
 cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST <= ((ier AND tc)
 	OR (slaveinten AND NOT spi_int));
 
-FTCPE_divisor0: FTCPE port map (divisor(0),divisor_T(0),divisor_C(0),NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_divisor0: FTCPE port map (divisor(0),divisor_T(0),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 divisor_T(0) <= ((divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(0).PIN)
 	OR (NOT divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(0).PIN));
-divisor_C(0) <= NOT ((cs1 AND NOT Ncs2));
 
-FTCPE_divisor1: FTCPE port map (divisor(1),divisor_T(1),divisor_C(1),NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_divisor1: FTCPE port map (divisor(1),divisor_T(1),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 divisor_T(1) <= ((divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(1).PIN)
 	OR (NOT divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(1).PIN));
-divisor_C(1) <= NOT ((cs1 AND NOT Ncs2));
 
-FTCPE_divisor2: FTCPE port map (divisor(2),divisor_T(2),divisor_C(2),NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_divisor2: FTCPE port map (divisor(2),divisor_T(2),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 divisor_T(2) <= ((divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(2).PIN)
 	OR (NOT divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(2).PIN));
-divisor_C(2) <= NOT ((cs1 AND NOT Ncs2));
 
-FTCPE_ece: FTCPE port map (ece,ece_T,ece_C,NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_ece: FTCPE port map (ece,ece_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 ece_T <= ((ece AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(2).PIN)
 	OR (NOT ece AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(2).PIN));
-ece_C <= NOT ((cs1 AND NOT Ncs2));
 
-FTCPE_frx: FTCPE port map (frx,frx_T,frx_C,NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_frx: FTCPE port map (frx,frx_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 frx_T <= ((frx AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
 	OR (NOT frx AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN));
-frx_C <= NOT ((cs1 AND NOT Ncs2));
 
-FTCPE_ier: FTCPE port map (ier,ier_T,ier_C,NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_ier: FTCPE port map (ier,ier_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 ier_T <= ((ier AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(6).PIN)
 	OR (NOT ier AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(6).PIN));
-ier_C <= NOT ((cs1 AND NOT Ncs2));
 
 
-cpu_d_I(0) <= ((cpu_rnw AND spi_Nsel AND cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+cpu_d_I(0) <= ((NOT Ncs2 AND cpu_rnw AND spi_Nsel AND cpu_a(1) AND 
 	cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND cpha AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
-	cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND divisor(0) AND cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+	OR (NOT Ncs2 AND cpu_rnw AND cpha AND NOT cpu_a(1) AND cpu_a(0) AND 
+	cpu_Nphi2)
+	OR (NOT Ncs2 AND cpu_rnw AND divisor(0) AND cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+	OR (NOT Ncs2 AND cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2));
 cpu_d(0) <= cpu_d_I(0) when cpu_d_OE(0) = '1' else 'Z';
-cpu_d_OE(0) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
+cpu_d_OE(0) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
 
 
-cpu_d_I(1) <= ((cpu_rnw AND cpol AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
-	cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND divisor(1) AND cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+cpu_d_I(1) <= ((NOT Ncs2 AND cpu_rnw AND cpol AND NOT cpu_a(1) AND cpu_a(0) AND 
+	cpu_Nphi2)
+	OR (NOT Ncs2 AND cpu_rnw AND divisor(1) AND cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+	OR (NOT Ncs2 AND cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2));
 cpu_d(1) <= cpu_d_I(1) when cpu_d_OE(1) = '1' else 'Z';
-cpu_d_OE(1) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
+cpu_d_OE(1) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
 
 
-cpu_d_I(2) <= ((cpu_rnw AND ece AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
-	cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND divisor(2) AND cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+cpu_d_I(2) <= ((NOT Ncs2 AND cpu_rnw AND ece AND NOT cpu_a(1) AND cpu_a(0) AND 
+	cpu_Nphi2)
+	OR (NOT Ncs2 AND cpu_rnw AND divisor(2) AND cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+	OR (NOT Ncs2 AND cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2));
 cpu_d(2) <= cpu_d_I(2) when cpu_d_OE(2) = '1' else 'Z';
-cpu_d_OE(2) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
+cpu_d_OE(2) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
 
 
-cpu_d_I(3) <= ((cpu_rnw AND tmo AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
-	cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+cpu_d_I(3) <= ((NOT Ncs2 AND cpu_rnw AND tmo AND NOT cpu_a(1) AND cpu_a(0) AND 
+	cpu_Nphi2)
+	OR (NOT Ncs2 AND cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2));
 cpu_d(3) <= cpu_d_I(3) when cpu_d_OE(3) = '1' else 'Z';
-cpu_d_OE(3) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
+cpu_d_OE(3) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
 
 
-cpu_d_I(4) <= ((cpu_rnw AND frx AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+cpu_d_I(4) <= ((NOT Ncs2 AND cpu_rnw AND frx AND NOT cpu_a(1) AND cpu_a(0) AND 
+	cpu_Nphi2)
+	OR (NOT Ncs2 AND cpu_rnw AND slaveinten AND cpu_a(1) AND 
 	cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND slaveinten AND cpu_a(1) AND cs1 AND NOT Ncs2 AND 
-	cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+	OR (NOT Ncs2 AND cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND cpu_a(1) AND cs1 AND NOT Ncs2 AND NOT cpu_a(0) AND 
-	NOT spi_int AND cpu_Nphi2));
+	OR (NOT Ncs2 AND cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND NOT spi_int AND 
+	cpu_Nphi2));
 cpu_d(4) <= cpu_d_I(4) when cpu_d_OE(4) = '1' else 'Z';
-cpu_d_OE(4) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
+cpu_d_OE(4) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
 
 
-cpu_d_I(5) <= ((cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+cpu_d_I(5) <= ((NOT Ncs2 AND cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND NOT cpu_a(1) AND start_shifting AND cs1 AND 
-	NOT Ncs2 AND cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND cpu_a(0) AND 
+	OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND start_shifting AND 
+	cpu_a(0) AND cpu_Nphi2)
+	OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND cpu_a(0) AND 
 	shifting2 AND cpu_Nphi2));
 cpu_d(5) <= cpu_d_I(5) when cpu_d_OE(5) = '1' else 'Z';
-cpu_d_OE(5) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
+cpu_d_OE(5) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
 
 
-cpu_d_I(6) <= ((cpu_rnw AND ier AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
-	cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+cpu_d_I(6) <= ((NOT Ncs2 AND cpu_rnw AND ier AND NOT cpu_a(1) AND cpu_a(0) AND 
+	cpu_Nphi2)
+	OR (NOT Ncs2 AND cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2));
 cpu_d(6) <= cpu_d_I(6) when cpu_d_OE(6) = '1' else 'Z';
-cpu_d_OE(6) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
+cpu_d_OE(6) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
 
 
-cpu_d_I(7) <= ((cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND 
+cpu_d_I(7) <= ((NOT Ncs2 AND cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND 
 	NOT cpu_a(0) AND cpu_Nphi2)
-	OR (cpu_rnw AND NOT cpu_a(1) AND tc AND cs1 AND NOT Ncs2 AND 
-	cpu_a(0) AND cpu_Nphi2));
+	OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND tc AND cpu_a(0) AND 
+	cpu_Nphi2));
 cpu_d(7) <= cpu_d_I(7) when cpu_d_OE(7) = '1' else 'Z';
-cpu_d_OE(7) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
+cpu_d_OE(7) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
 
-FDCPE_spi_mosi: FDCPE port map (spi_mosi_I,spi_mosi,NOT $OpTx$INV$22__$INT,'0',NOT cpu_Nres);
+FDCPE_spi_mosi: FDCPE port map (spi_mosi_I,spi_mosi,NOT $OpTx$INV$24__$INT,'0',NOT cpu_Nres);
 spi_mosi <= ((EXP6_.EXP)
 	OR (shifting2.EXP)
-	OR (shiftcnt(3) AND shiftcnt(2) AND NOT shiftcnt(1) AND 
-	NOT shiftdone AND NOT spidataout(1) AND shifting2)
-	OR (NOT shiftcnt(3) AND shiftcnt(2) AND NOT shiftcnt(1) AND 
-	NOT shiftdone AND NOT spidataout(5) AND shifting2));
+	OR (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(1) AND 
+	NOT shiftdone AND NOT spidataout(0) AND shifting2)
+	OR (NOT shiftcnt(3) AND shiftcnt(2) AND shiftcnt(1) AND 
+	NOT shiftdone AND NOT spidataout(4) AND shifting2));
 spi_mosi <= spi_mosi_I when spi_mosi_OE = '1' else 'Z';
 spi_mosi_OE <= NOT tmo;
 
-FDCPE_spi_sclk: FDCPE port map (spi_sclk,spi_sclk_D,NOT $OpTx$INV$22__$INT,spi_sclk_CLR,spi_sclk_PRE);
+FDCPE_spi_sclk: FDCPE port map (spi_sclk,spi_sclk_D,NOT $OpTx$INV$24__$INT,spi_sclk_CLR,spi_sclk_PRE);
 spi_sclk_D <= cpol
 	 XOR 
-spi_sclk_D <= ((EXP7_.EXP)
+spi_sclk_D <= ((shiftcnt(1).EXP)
 	OR (cpu_Nres AND NOT cpha AND shiftcnt(0) AND NOT shiftdone AND 
 	shifting2));
 spi_sclk_CLR <= (NOT cpu_Nres AND NOT cpol);
@@ -555,144 +577,138 @@ spi_sclk_PRE <= (NOT cpu_Nres AND cpol);
 
 led <= (spi_Nsel AND NOT start_shifting AND NOT shifting2);
 
-FDCPE_shiftcnt0: FDCPE port map (shiftcnt(0),shiftcnt_D(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
+
+ng <= (Ncs2 AND nio_stb AND nio_sel);
+
+
+noe <= NOT (((NOT nio_stb AND add_dec/XLXN_11)
+	OR (NOT nio_sel AND add_dec/XLXN_11)));
+
+FDCPE_shiftcnt0: FDCPE port map (shiftcnt(0),shiftcnt_D(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
 shiftcnt_D(0) <= (NOT shiftcnt(0) AND shifting2);
 
-FDCPE_shiftcnt1: FDCPE port map (shiftcnt(1),shiftcnt_D(1),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
+FDCPE_shiftcnt1: FDCPE port map (shiftcnt(1),shiftcnt_D(1),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
 shiftcnt_D(1) <= ((shiftcnt(0) AND NOT shiftcnt(1) AND shifting2)
 	OR (NOT shiftcnt(0) AND shiftcnt(1) AND shifting2));
 
-FTCPE_shiftcnt2: FTCPE port map (shiftcnt(2),shiftcnt_T(2),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
+FTCPE_shiftcnt2: FTCPE port map (shiftcnt(2),shiftcnt_T(2),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
 shiftcnt_T(2) <= ((shiftcnt(2) AND NOT shifting2)
 	OR (shiftcnt(0) AND shiftcnt(1) AND shifting2));
 
-FTCPE_shiftcnt3: FTCPE port map (shiftcnt(3),shiftcnt_T(3),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
+FTCPE_shiftcnt3: FTCPE port map (shiftcnt(3),shiftcnt_T(3),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
 shiftcnt_T(3) <= ((shiftcnt(3) AND NOT shifting2)
 	OR (shiftcnt(2) AND shiftcnt(0) AND shiftcnt(1) AND 
 	shifting2));
 
-FDCPE_shiftdone: FDCPE port map (shiftdone,shiftdone_D,NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
+FDCPE_shiftdone: FDCPE port map (shiftdone,shiftdone_D,NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
 shiftdone_D <= (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(0) AND 
 	shiftcnt(1));
 
-FDCPE_shifting2: FDCPE port map (shifting2,shifting2_D,NOT $OpTx$INV$22__$INT,'0','0');
+FDCPE_shifting2: FDCPE port map (shifting2,shifting2_D,NOT $OpTx$INV$24__$INT,'0','0');
 shifting2_D <= (NOT shiftdone AND start_shifting);
 
-FTCPE_slaveinten: FTCPE port map (slaveinten,slaveinten_T,slaveinten_C,NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_slaveinten: FTCPE port map (slaveinten,slaveinten_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 slaveinten_T <= ((slaveinten AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
 	OR (NOT slaveinten AND cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN));
-slaveinten_C <= NOT ((cs1 AND NOT Ncs2));
 
-FTCPE_spi_Nsel: FTCPE port map (spi_Nsel,spi_Nsel_T,spi_Nsel_C,'0',NOT cpu_Nres,NOT cpu_rnw);
+FTCPE_spi_Nsel: FTCPE port map (spi_Nsel,spi_Nsel_T,Ncs2,'0',NOT cpu_Nres,NOT cpu_rnw);
 spi_Nsel_T <= ((spi_Nsel AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
 	OR (NOT spi_Nsel AND cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
-spi_Nsel_C <= NOT ((cs1 AND NOT Ncs2));
 
-FDCPE_spidatain0: FDCPE port map (spidatain(0),spidatain_D(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(0));
+FDCPE_spidatain0: FDCPE port map (spidatain(0),spidatain_D(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(0));
 spidatain_D(0) <= (NOT spi_Nsel AND spi_miso);
 spidatain_CE(0) <= (shiftcnt(0) AND shifting2);
 
-FDCPE_spidatain1: FDCPE port map (spidatain(1),spidatain(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(1));
+FDCPE_spidatain1: FDCPE port map (spidatain(1),spidatain(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(1));
 spidatain_CE(1) <= (shiftcnt(0) AND shifting2);
 
-FDCPE_spidatain2: FDCPE port map (spidatain(2),spidatain(1),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(2));
+FDCPE_spidatain2: FDCPE port map (spidatain(2),spidatain(1),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(2));
 spidatain_CE(2) <= (shiftcnt(0) AND shifting2);
 
-FDCPE_spidatain3: FDCPE port map (spidatain(3),spidatain(2),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(3));
+FDCPE_spidatain3: FDCPE port map (spidatain(3),spidatain(2),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(3));
 spidatain_CE(3) <= (shiftcnt(0) AND shifting2);
 
-FDCPE_spidatain4: FDCPE port map (spidatain(4),spidatain(3),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(4));
+FDCPE_spidatain4: FDCPE port map (spidatain(4),spidatain(3),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(4));
 spidatain_CE(4) <= (shiftcnt(0) AND shifting2);
 
-FDCPE_spidatain5: FDCPE port map (spidatain(5),spidatain(4),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(5));
+FDCPE_spidatain5: FDCPE port map (spidatain(5),spidatain(4),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(5));
 spidatain_CE(5) <= (shiftcnt(0) AND shifting2);
 
-FDCPE_spidatain6: FDCPE port map (spidatain(6),spidatain(5),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(6));
+FDCPE_spidatain6: FDCPE port map (spidatain(6),spidatain(5),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(6));
 spidatain_CE(6) <= (shiftcnt(0) AND shifting2);
 
-FDCPE_spidatain7: FDCPE port map (spidatain(7),spidatain(6),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(7));
+FDCPE_spidatain7: FDCPE port map (spidatain(7),spidatain(6),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(7));
 spidatain_CE(7) <= (shiftcnt(0) AND shifting2);
 
-FTCPE_spidataout0: FTCPE port map (spidataout(0),spidataout_T(0),spidataout_C(0),'0','0',spidataout_CE(0));
+FTCPE_spidataout0: FTCPE port map (spidataout(0),spidataout_T(0),Ncs2,'0','0',spidataout_CE(0));
 spidataout_T(0) <= ((NOT cpu_a(1) AND spidataout(0) AND NOT cpu_a(0) AND 
 	NOT cpu_d(0).PIN)
 	OR (NOT cpu_a(1) AND NOT spidataout(0) AND NOT cpu_a(0) AND 
 	cpu_d(0).PIN));
-spidataout_C(0) <= NOT ((cs1 AND NOT Ncs2));
 spidataout_CE(0) <= (cpu_Nres AND NOT cpu_rnw);
 
-FTCPE_spidataout1: FTCPE port map (spidataout(1),spidataout_T(1),spidataout_C(1),'0','0',spidataout_CE(1));
+FTCPE_spidataout1: FTCPE port map (spidataout(1),spidataout_T(1),Ncs2,'0','0',spidataout_CE(1));
 spidataout_T(1) <= ((NOT cpu_a(1) AND spidataout(1) AND NOT cpu_a(0) AND 
 	NOT cpu_d(1).PIN)
 	OR (NOT cpu_a(1) AND NOT spidataout(1) AND NOT cpu_a(0) AND 
 	cpu_d(1).PIN));
-spidataout_C(1) <= NOT ((cs1 AND NOT Ncs2));
 spidataout_CE(1) <= (cpu_Nres AND NOT cpu_rnw);
 
-FTCPE_spidataout2: FTCPE port map (spidataout(2),spidataout_T(2),spidataout_C(2),'0','0',spidataout_CE(2));
+FTCPE_spidataout2: FTCPE port map (spidataout(2),spidataout_T(2),Ncs2,'0','0',spidataout_CE(2));
 spidataout_T(2) <= ((NOT cpu_a(1) AND spidataout(2) AND NOT cpu_a(0) AND 
 	NOT cpu_d(2).PIN)
 	OR (NOT cpu_a(1) AND NOT spidataout(2) AND NOT cpu_a(0) AND 
 	cpu_d(2).PIN));
-spidataout_C(2) <= NOT ((cs1 AND NOT Ncs2));
 spidataout_CE(2) <= (cpu_Nres AND NOT cpu_rnw);
 
-FTCPE_spidataout3: FTCPE port map (spidataout(3),spidataout_T(3),spidataout_C(3),'0','0',spidataout_CE(3));
+FTCPE_spidataout3: FTCPE port map (spidataout(3),spidataout_T(3),Ncs2,'0','0',spidataout_CE(3));
 spidataout_T(3) <= ((NOT cpu_a(1) AND spidataout(3) AND NOT cpu_a(0) AND 
 	NOT cpu_d(3).PIN)
 	OR (NOT cpu_a(1) AND NOT spidataout(3) AND NOT cpu_a(0) AND 
 	cpu_d(3).PIN));
-spidataout_C(3) <= NOT ((cs1 AND NOT Ncs2));
 spidataout_CE(3) <= (cpu_Nres AND NOT cpu_rnw);
 
-FTCPE_spidataout4: FTCPE port map (spidataout(4),spidataout_T(4),spidataout_C(4),'0','0',spidataout_CE(4));
+FTCPE_spidataout4: FTCPE port map (spidataout(4),spidataout_T(4),Ncs2,'0','0',spidataout_CE(4));
 spidataout_T(4) <= ((NOT cpu_a(1) AND spidataout(4) AND NOT cpu_a(0) AND 
 	NOT cpu_d(4).PIN)
 	OR (NOT cpu_a(1) AND NOT spidataout(4) AND NOT cpu_a(0) AND 
 	cpu_d(4).PIN));
-spidataout_C(4) <= NOT ((cs1 AND NOT Ncs2));
 spidataout_CE(4) <= (cpu_Nres AND NOT cpu_rnw);
 
-FTCPE_spidataout5: FTCPE port map (spidataout(5),spidataout_T(5),spidataout_C(5),'0','0',spidataout_CE(5));
+FTCPE_spidataout5: FTCPE port map (spidataout(5),spidataout_T(5),Ncs2,'0','0',spidataout_CE(5));
 spidataout_T(5) <= ((NOT cpu_a(1) AND spidataout(5) AND NOT cpu_a(0) AND 
 	NOT cpu_d(5).PIN)
 	OR (NOT cpu_a(1) AND NOT spidataout(5) AND NOT cpu_a(0) AND 
 	cpu_d(5).PIN));
-spidataout_C(5) <= NOT ((cs1 AND NOT Ncs2));
 spidataout_CE(5) <= (cpu_Nres AND NOT cpu_rnw);
 
-FTCPE_spidataout6: FTCPE port map (spidataout(6),spidataout_T(6),spidataout_C(6),'0','0',spidataout_CE(6));
+FTCPE_spidataout6: FTCPE port map (spidataout(6),spidataout_T(6),Ncs2,'0','0',spidataout_CE(6));
 spidataout_T(6) <= ((NOT cpu_a(1) AND spidataout(6) AND NOT cpu_a(0) AND 
 	NOT cpu_d(6).PIN)
 	OR (NOT cpu_a(1) AND NOT spidataout(6) AND NOT cpu_a(0) AND 
 	cpu_d(6).PIN));
-spidataout_C(6) <= NOT ((cs1 AND NOT Ncs2));
 spidataout_CE(6) <= (cpu_Nres AND NOT cpu_rnw);
 
-FTCPE_spidataout7: FTCPE port map (spidataout(7),spidataout_T(7),spidataout_C(7),'0','0',spidataout_CE(7));
+FTCPE_spidataout7: FTCPE port map (spidataout(7),spidataout_T(7),Ncs2,'0','0',spidataout_CE(7));
 spidataout_T(7) <= ((NOT cpu_a(1) AND spidataout(7) AND NOT cpu_a(0) AND 
 	NOT cpu_d(7).PIN)
 	OR (NOT cpu_a(1) AND NOT spidataout(7) AND NOT cpu_a(0) AND 
 	cpu_d(7).PIN));
-spidataout_C(7) <= NOT ((cs1 AND NOT Ncs2));
 spidataout_CE(7) <= (cpu_Nres AND NOT cpu_rnw);
 
-FTCPE_start_shifting: FTCPE port map (start_shifting,start_shifting_T,start_shifting_C,NOT start_shifting/start_shifting_RSTF__$INT,'0');
+FTCPE_start_shifting: FTCPE port map (start_shifting,start_shifting_T,Ncs2,NOT start_shifting/start_shifting_RSTF__$INT,'0');
 start_shifting_T <= ((NOT cpu_rnw AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0))
 	OR (frx AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0)));
-start_shifting_C <= NOT ((cs1 AND NOT Ncs2));
 
 
 start_shifting/start_shifting_RSTF__$INT <= (cpu_Nres AND NOT shiftdone);
 
-FDCPE_tc: FDCPE port map (tc,'0',tc_C,'0',shiftdone,tc_CE);
-tc_C <= NOT ((cs1 AND NOT Ncs2));
+FDCPE_tc: FDCPE port map (tc,'0',Ncs2,'0',shiftdone,tc_CE);
 tc_CE <= (NOT cpu_a(1) AND NOT cpu_a(0));
 
-FTCPE_tmo: FTCPE port map (tmo,tmo_T,tmo_C,NOT cpu_Nres,'0',NOT cpu_rnw);
+FTCPE_tmo: FTCPE port map (tmo,tmo_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
 tmo_T <= ((tmo AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(3).PIN)
 	OR (NOT tmo AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(3).PIN));
-tmo_C <= NOT ((cs1 AND NOT Ncs2));
 
 Register Legend:
  FDCPE (Q,D,C,CLR,PRE,CE); 
@@ -725,9 +741,9 @@ Pin Signal                         Pin Signal
 No. Name                           No. Name                          
   1 TIE                              23 GND                           
   2 cpu_d<0>                         24 cpu_a<1>                      
-  3 cpu_d<1>                         25 TIE                           
-  4 cpu_d<2>                         26 TIE                           
-  5 cpu_Nphi2                        27 TIE                           
+  3 cpu_d<1>                         25 b8                            
+  4 cpu_d<2>                         26 b9                            
+  5 cpu_Nphi2                        27 b10                           
   6 extclk                           28 spi_Nsel                      
   7 cpu_rnw                          29 led                           
   8 cpu_d<3>                         30 TDO                           
@@ -736,14 +752,14 @@ No. Name                           No. Name
  11 cpu_d<5>                         33 TIE                           
  12 cpu_d<6>                         34 spi_sclk                      
  13 cpu_d<7>                         35 spi_mosi                      
- 14 cpu_Nirq                         36 TIE                           
- 15 TDI                              37 TIE                           
- 16 TMS                              38 TIE                           
- 17 TCK                              39 TIE                           
- 18 Ncs2                             40 TIE                           
+ 14 noe                              36 a8                            
+ 15 TDI                              37 a9                            
+ 16 TMS                              38 a10                           
+ 17 TCK                              39 cpu_Nirq                      
+ 18 Ncs2                             40 nio_sel                       
  19 cpu_Nres                         41 VCC                           
- 20 cs1                              42 spi_int                       
- 21 VCC                              43 TIE                           
+ 20 ng                               42 spi_int                       
+ 21 VCC                              43 nio_stb                       
  22 cpu_a<0>                         44 spi_miso                      
 
 
diff --git a/spi6502b.syr b/spi6502b.syr
index 86a74ef..3b0c698 100644
--- a/spi6502b.syr
+++ b/spi6502b.syr
@@ -66,6 +66,10 @@ wysiwyg                            : NO
 =========================================================================
 *                          HDL Compilation                              *
 =========================================================================
+Compiling vhdl file C:/sources/AppleIISd/address_decoder.vhf in Library work.
+Architecture behavioral of Entity fd_mxilinx_address_decoder is up to date.
+Architecture behavioral of Entity fdrs_mxilinx_address_decoder is up to date.
+Architecture behavioral of Entity address_decoder is up to date.
 Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work.
 Entity <spi6502b> (Architecture <behavioral>) compiled.
 
@@ -73,22 +77,48 @@ Entity <spi6502b> (Architecture <behavioral>) compiled.
 *                            HDL Analysis                               *
 =========================================================================
 Analyzing Entity <spi6502b> (Architecture <behavioral>).
-INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 203: Mux is complete : default of case is discarded
-INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 316: Mux is complete : default of case is discarded
+INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 240: Mux is complete : default of case is discarded
+INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 353: Mux is complete : default of case is discarded
 Entity <spi6502b> analyzed. Unit <spi6502b> generated.
 
+Analyzing Entity <address_decoder> (Architecture <behavioral>).
+    Set user-defined property "HU_SET =  XLXI_16_1" for instance <XLXI_16> in unit <address_decoder>.
+Entity <address_decoder> analyzed. Unit <address_decoder> generated.
+
+Analyzing Entity <FDRS_MXILINX_address_decoder> (Architecture <behavioral>).
+    Set user-defined property "HU_SET =  U0_0" for instance <U0> in unit <FDRS_MXILINX_address_decoder>.
+Entity <FDRS_MXILINX_address_decoder> analyzed. Unit <FDRS_MXILINX_address_decoder> generated.
+
+Analyzing Entity <FD_MXILINX_address_decoder> (Architecture <behavioral>).
+Entity <FD_MXILINX_address_decoder> analyzed. Unit <FD_MXILINX_address_decoder> generated.
+
 
 =========================================================================
 *                           HDL Synthesis                               *
 =========================================================================
 
+Synthesizing Unit <FD_MXILINX_address_decoder>.
+    Related source file is C:/sources/AppleIISd/address_decoder.vhf.
+Unit <FD_MXILINX_address_decoder> synthesized.
+
+
+Synthesizing Unit <FDRS_MXILINX_address_decoder>.
+    Related source file is C:/sources/AppleIISd/address_decoder.vhf.
+Unit <FDRS_MXILINX_address_decoder> synthesized.
+
+
+Synthesizing Unit <address_decoder>.
+    Related source file is C:/sources/AppleIISd/address_decoder.vhf.
+Unit <address_decoder> synthesized.
+
+
 Synthesizing Unit <spi6502b>.
     Related source file is C:/sources/AppleIISd/SPI6502B1.1.vhd.
     Found 8-bit tristate buffer for signal <cpu_d>.
     Found 1-bit tristate buffer for signal <cpu_Nirq>.
     Found 1-bit tristate buffer for signal <spi_mosi>.
-    Found 1-bit xor3 for signal <$n0040> created at line 206.
-    Found 4-bit adder for signal <$n0047> created at line 160.
+    Found 1-bit xor3 for signal <$n0040> created at line 243.
+    Found 4-bit adder for signal <$n0047> created at line 197.
     Found 1-bit register for signal <cpha>.
     Found 1-bit register for signal <cpol>.
     Found 3-bit down counter for signal <divcnt>.
@@ -153,6 +183,12 @@ Macro Statistics
 
 Optimizing unit <spi6502b> ...
 
+Optimizing unit <FD_MXILINX_address_decoder> ...
+
+Optimizing unit <FDRS_MXILINX_address_decoder> ...
+
+Optimizing unit <address_decoder> ...
+
 =========================================================================
 *                            Final Report                               *
 =========================================================================
@@ -169,7 +205,7 @@ Clock Enable                       : YES
 wysiwyg                            : NO
 
 Design Statistics
-# IOs                              : 23
+# IOs                              : 32
 
 Macro Statistics :
 # Registers                        : 60
@@ -181,33 +217,37 @@ Macro Statistics :
 #      1-bit xor2                  : 5
 
 Cell Usage :
-# BELS                             : 252
-#      AND2                        : 119
-#      AND3                        : 5
+# BELS                             : 256
+#      AND2                        : 120
+#      AND3                        : 6
 #      AND4                        : 1
-#      GND                         : 1
-#      INV                         : 77
-#      OR2                         : 42
+#      GND                         : 2
+#      INV                         : 76
+#      OR2                         : 43
 #      OR3                         : 1
-#      VCC                         : 1
+#      VCC                         : 2
 #      XOR2                        : 5
-# FlipFlops/Latches                : 37
+# FlipFlops/Latches                : 38
 #      FD                          : 1
 #      FDC                         : 5
 #      FDCE                        : 27
-#      FDCP                        : 1
+#      FDCP                        : 2
 #      FDP                         : 1
 #      FDPE                        : 2
-# IO Buffers                       : 23
-#      IBUF                        : 10
+# IO Buffers                       : 32
+#      IBUF                        : 14
 #      IOBUFE                      : 8
-#      OBUF                        : 3
+#      OBUF                        : 8
 #      OBUFE                       : 2
+# Others                           : 5
+#      AND2B1                      : 2
+#      AND4B1                      : 1
+#      NAND2                       : 2
 =========================================================================
-CPU : 0.65 / 1.07 s | Elapsed : 0.00 / 1.00 s
+CPU : 1.05 / 1.48 s | Elapsed : 1.00 / 1.00 s
  
 --> 
 
-Total memory usage is 68376 kilobytes
+Total memory usage is 69656 kilobytes
 
 
diff --git a/spi6502b.vm6 b/spi6502b.vm6
index 694f27c..cd64402 100644
--- a/spi6502b.vm6
+++ b/spi6502b.vm6
@@ -8,3425 +8,3536 @@ NETWORK | spi6502b | 0 | 0 | 16391
 
 INPUT_INSTANCE | 0 | 0 | NULL | cpu_Nres_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_Nres | 4063 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | cpu_Nres | 4234 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 
 MACROCELL_INSTANCE | Inv+PrldLow+PinTrst+OptxMapped | int_mosi | spi6502b_COPY_0_COPY_0 | 2155889920 | 12 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<5> | 4018 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
+NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<1> | 4014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
+NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | EXP6_.EXP | 4389 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT
+NODE | EXP6_.EXP | 4588 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2.EXP | 4390 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT
+NODE | shifting2.EXP | 4589 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tmo | 3983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
+NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_mosi | 3972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.Q | int_mosi | 0 | 0 | MC_Q
+NODE | int_mosi | 4127 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.Q | int_mosi | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_mosi$OE | 3973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.BUFOE.OUT | int_mosi | 2 | 0 | MC_OE
+NODE | int_mosi$OE | 4128 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.BUFOE.OUT | int_mosi | 2 | 0 | MC_OE
 
 SIGNAL_INSTANCE | int_mosi.SI | int_mosi | 0 | 12 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<5> | 4018 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
+NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<1> | 4014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
+NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | EXP6_.EXP | 4389 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT
+NODE | EXP6_.EXP | 4588 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2.EXP | 4390 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT
+NODE | shifting2.EXP | 4589 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tmo | 3983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
+NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_mosi.D1 | 4074 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_mosi.D1 | 4249 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_mosi.D2 | 4075 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | int_mosi.D2 | 4250 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 1 | IV_TRUE | EXP6_.EXP
 SPPTERM | 1 | IV_TRUE | shifting2.EXP
-SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<1> | IV_TRUE | shifting2
-SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<5> | IV_TRUE | shifting2
+SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<0> | IV_TRUE | shifting2
+SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<4> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | int_mosi.CLKF | 4076 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | int_mosi.CLKF | 4251 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF
-SIGNAL | NODE | int_mosi.SETF | 4077 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 5 | 9 | MC_SI_SETF
+SIGNAL | NODE | int_mosi.SETF | 4252 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 5 | 9 | MC_SI_SETF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_mosi.TRST | 4079 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | int_mosi.TRST | 4254 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 4 | 9 | MC_SI_TRST
 SPPTERM | 1 | IV_FALSE | tmo
 
 SRFF_INSTANCE | int_mosi.REG | int_mosi | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_mosi.D | 4073 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.XOR | 0 | 7 | ALU_F
+NODE | int_mosi.D | 4248 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | int_mosi.CLKF | 4076 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | int_mosi.CLKF | 4251 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 2 | 8 | SRFF_S
-SIGNAL | NODE | int_mosi.SETF | 4077 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 5 | 9 | MC_SI_SETF
+SIGNAL | NODE | int_mosi.SETF | 4252 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 5 | 9 | MC_SI_SETF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_mosi.Q | 4080 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.REG | 0 | 8 | SRFF_Q
+NODE | int_mosi.Q | 4255 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_mosi.BUFOE | int_mosi | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_mosi.TRST | 4079 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | int_mosi.TRST | 4254 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 4 | 9 | MC_SI_TRST
 SPPTERM | 1 | IV_FALSE | tmo
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_mosi.BUFOE.OUT | 4078 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.BUFOE | 0 | 10 | BUF_OUT
-
-INPUT_INSTANCE | 0 | 0 | NULL | cpu_rnw_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
-INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_rnw | 4064 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
-OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | int_mosi.BUFOE.OUT | 4253 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.BUFOE | 0 | 10 | BUF_OUT
 
 INPUT_INSTANCE | 0 | 0 | NULL | Ncs2_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | Ncs2 | 4068 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | Ncs2 | 4235 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 
-INPUT_INSTANCE | 0 | 0 | NULL | cs1_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | cpu_rnw_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cs1 | 4067 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | cpu_rnw | 4236 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 
-INPUT_INSTANCE | 0 | 0 | NULL | N2889 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | N3017 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_d<0> | 4054 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<0> | 0 | 6 | OI_OUT
+NODE | cpu_d<0> | 4221 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<0> | 0 | 6 | OI_OUT
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 
 INPUT_INSTANCE | 0 | 0 | NULL | cpu_a_0_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_a<0> | 4069 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | cpu_a<0> | 4244 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 
 INPUT_INSTANCE | 0 | 0 | NULL | cpu_a_1_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_a<1> | 4066 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | cpu_a<1> | 4242 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slavesel | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 2
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | slavesel | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | slavesel$Q | 3975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 0 | 0 | MC_Q
+NODE | slavesel$Q | 4131 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | slavesel.SI | slavesel | 0 | 8 | 5
+SIGNAL_INSTANCE | slavesel.SI | slavesel | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | slavesel.D1 | 4082 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | slavesel.D1 | 4257 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | slavesel.D2 | 4083 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N2889
-SPPTERM | 4 | IV_FALSE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N2889
+SIGNAL | NODE | slavesel.D2 | 4258 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3017
+SPPTERM | 4 | IV_FALSE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3017
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | slavesel.CLKF | 4084 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | slavesel.CLKF | 4259 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF
-SIGNAL | NODE | slavesel.SETF | 4085 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 5 | 9 | MC_SI_SETF
+SIGNAL | NODE | slavesel.SETF | 4260 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 5 | 9 | MC_SI_SETF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | slavesel.CE | 4086 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | slavesel.CE | 4261 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | slavesel.REG | slavesel | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | slavesel.D | 4081 | ? | 0 | 0 | slavesel | NULL | NULL | slavesel.XOR | 0 | 7 | ALU_F
+NODE | slavesel.D | 4256 | ? | 0 | 0 | slavesel | NULL | NULL | slavesel.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | slavesel.CLKF | 4084 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | slavesel.CLKF | 4259 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 2 | 8 | SRFF_S
-SIGNAL | NODE | slavesel.SETF | 4085 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 5 | 9 | MC_SI_SETF
+SIGNAL | NODE | slavesel.SETF | 4260 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 5 | 9 | MC_SI_SETF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | slavesel.CE | 4086 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | slavesel.CE | 4261 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | slavesel.Q | 4087 | ? | 0 | 0 | slavesel | NULL | NULL | slavesel.REG | 0 | 8 | SRFF_Q
+NODE | slavesel.Q | 4262 | ? | 0 | 0 | slavesel | NULL | NULL | slavesel.REG | 0 | 8 | SRFF_Q
 
-INPUT_INSTANCE | 0 | 0 | NULL | N2891 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | N3019 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_d<1> | 4055 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<1> | 0 | 6 | OI_OUT
+NODE | cpu_d<1> | 4222 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<1> | 0 | 6 | OI_OUT
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | N2891 | 4034 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2891 | 0 | 5 | II_IMUX
+NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | cpol | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | cpol | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpol | 3977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
+NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2891 | 4034 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2891 | 0 | 5 | II_IMUX
+NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | cpol | 3977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
+NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | cpol.SI | cpol | 0 | 8 | 5
+SIGNAL_INSTANCE | cpol.SI | cpol | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpol | 3977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
+NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2891 | 4034 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2891 | 0 | 5 | II_IMUX
+NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | cpol.D1 | 4089 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | cpol.D1 | 4264 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | cpol.D2 | 4090 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N2891
-SPPTERM | 4 | IV_FALSE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N2891
+SIGNAL | NODE | cpol.D2 | 4265 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3019
+SPPTERM | 4 | IV_FALSE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3019
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | cpol.CLKF | 4091 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | cpol.CLKF | 4266 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | cpol.RSTF | 4092 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | cpol.RSTF | 4267 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | cpol.CE | 4093 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | cpol.CE | 4268 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | cpol.REG | cpol | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | cpol.D | 4088 | ? | 0 | 0 | cpol | NULL | NULL | cpol.XOR | 0 | 7 | ALU_F
+NODE | cpol.D | 4263 | ? | 0 | 0 | cpol | NULL | NULL | cpol.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | cpol.CLKF | 4091 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | cpol.CLKF | 4266 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | cpol.RSTF | 4092 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | cpol.RSTF | 4267 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | cpol.CE | 4093 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | cpol.CE | 4268 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | cpol.Q | 4094 | ? | 0 | 0 | cpol | NULL | NULL | cpol.REG | 0 | 8 | SRFF_Q
+NODE | cpol.Q | 4269 | ? | 0 | 0 | cpol | NULL | NULL | cpol.REG | 0 | 8 | SRFF_Q
 
-INPUT_INSTANCE | 0 | 0 | NULL | N2893 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | N3021 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_d<2> | 4056 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<2> | 0 | 6 | OI_OUT
+NODE | cpu_d<2> | 4223 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<2> | 0 | 6 | OI_OUT
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | N2893 | 4035 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2893 | 0 | 5 | II_IMUX
+NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | ece | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | ece | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ece | 3978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
+NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2893 | 4035 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2893 | 0 | 5 | II_IMUX
+NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | ece | 3978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
+NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | ece.SI | ece | 0 | 8 | 5
+SIGNAL_INSTANCE | ece.SI | ece | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ece | 3978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
+NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2893 | 4035 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2893 | 0 | 5 | II_IMUX
+NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | ece.D1 | 4096 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ece.D1 | 4271 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | ece.D2 | 4097 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N2893
-SPPTERM | 4 | IV_FALSE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N2893
+SIGNAL | NODE | ece.D2 | 4272 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3021
+SPPTERM | 4 | IV_FALSE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3021
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | ece.CLKF | 4098 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | ece.CLKF | 4273 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | ece.RSTF | 4099 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | ece.RSTF | 4274 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | ece.CE | 4100 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | ece.CE | 4275 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | ece.REG | ece | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | ece.D | 4095 | ? | 0 | 0 | ece | NULL | NULL | ece.XOR | 0 | 7 | ALU_F
+NODE | ece.D | 4270 | ? | 0 | 0 | ece | NULL | NULL | ece.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | ece.CLKF | 4098 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | ece.CLKF | 4273 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | ece.RSTF | 4099 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | ece.RSTF | 4274 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | ece.CE | 4100 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | ece.CE | 4275 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | ece.Q | 4101 | ? | 0 | 0 | ece | NULL | NULL | ece.REG | 0 | 8 | SRFF_Q
+NODE | ece.Q | 4276 | ? | 0 | 0 | ece | NULL | NULL | ece.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | cpha | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | cpha | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | cpha.SI | cpha | 0 | 8 | 5
+SIGNAL_INSTANCE | cpha.SI | cpha | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | cpha.D1 | 4103 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | cpha.D1 | 4278 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | cpha.D2 | 4104 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N2889
-SPPTERM | 4 | IV_FALSE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N2889
+SIGNAL | NODE | cpha.D2 | 4279 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3017
+SPPTERM | 4 | IV_FALSE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3017
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | cpha.CLKF | 4105 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | cpha.CLKF | 4280 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | cpha.RSTF | 4106 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | cpha.RSTF | 4281 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | cpha.CE | 4107 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | cpha.CE | 4282 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | cpha.REG | cpha | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | cpha.D | 4102 | ? | 0 | 0 | cpha | NULL | NULL | cpha.XOR | 0 | 7 | ALU_F
+NODE | cpha.D | 4277 | ? | 0 | 0 | cpha | NULL | NULL | cpha.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | cpha.CLKF | 4105 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | cpha.CLKF | 4280 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | cpha.RSTF | 4106 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | cpha.RSTF | 4281 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | cpha.CE | 4107 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | cpha.CE | 4282 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | cpha.Q | 4108 | ? | 0 | 0 | cpha | NULL | NULL | cpha.REG | 0 | 8 | SRFF_Q
+NODE | cpha.Q | 4283 | ? | 0 | 0 | cpha | NULL | NULL | cpha.REG | 0 | 8 | SRFF_Q
 
-INPUT_INSTANCE | 0 | 0 | NULL | N2897 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | N3025 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_d<4> | 4057 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<4> | 0 | 6 | OI_OUT
+NODE | cpu_d<4> | 4224 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<4> | 0 | 6 | OI_OUT
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | N2897 | 4037 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2897 | 0 | 5 | II_IMUX
+NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | frx | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | frx | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | frx | 3980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
+NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2897 | 4037 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2897 | 0 | 5 | II_IMUX
+NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | frx | 3980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
+NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | frx.SI | frx | 0 | 8 | 5
+SIGNAL_INSTANCE | frx.SI | frx | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | frx | 3980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
+NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2897 | 4037 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2897 | 0 | 5 | II_IMUX
+NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | frx.D1 | 4110 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | frx.D1 | 4285 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | frx.D2 | 4111 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N2897
-SPPTERM | 4 | IV_FALSE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N2897
+SIGNAL | NODE | frx.D2 | 4286 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3025
+SPPTERM | 4 | IV_FALSE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3025
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | frx.CLKF | 4112 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | frx.CLKF | 4287 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | frx.RSTF | 4113 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | frx.RSTF | 4288 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | frx.CE | 4114 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | frx.CE | 4289 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | frx.REG | frx | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | frx.D | 4109 | ? | 0 | 0 | frx | NULL | NULL | frx.XOR | 0 | 7 | ALU_F
+NODE | frx.D | 4284 | ? | 0 | 0 | frx | NULL | NULL | frx.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | frx.CLKF | 4112 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | frx.CLKF | 4287 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | frx.RSTF | 4113 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | frx.RSTF | 4288 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | frx.CE | 4114 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | frx.CE | 4289 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | frx.Q | 4115 | ? | 0 | 0 | frx | NULL | NULL | frx.REG | 0 | 8 | SRFF_Q
+NODE | frx.Q | 4290 | ? | 0 | 0 | frx | NULL | NULL | frx.REG | 0 | 8 | SRFF_Q
 
-INPUT_INSTANCE | 0 | 0 | NULL | N2901 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | N3029 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_d<6> | 4052 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<6> | 0 | 6 | OI_OUT
+NODE | cpu_d<6> | 4218 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<6> | 0 | 6 | OI_OUT
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | N2901 | 4038 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2901 | 0 | 5 | II_IMUX
+NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | ier | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | ier | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ier | 3981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
+NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2901 | 4038 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2901 | 0 | 5 | II_IMUX
+NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | ier | 3981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
+NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | ier.SI | ier | 0 | 8 | 5
+SIGNAL_INSTANCE | ier.SI | ier | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ier | 3981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
+NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2901 | 4038 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2901 | 0 | 5 | II_IMUX
+NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | ier.D1 | 4117 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ier.D1 | 4292 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | ier.D2 | 4118 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N2901
-SPPTERM | 4 | IV_FALSE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N2901
+SIGNAL | NODE | ier.D2 | 4293 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3029
+SPPTERM | 4 | IV_FALSE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3029
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | ier.CLKF | 4119 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | ier.CLKF | 4294 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | ier.RSTF | 4120 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | ier.RSTF | 4295 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | ier.CE | 4121 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | ier.CE | 4296 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | ier.REG | ier | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | ier.D | 4116 | ? | 0 | 0 | ier | NULL | NULL | ier.XOR | 0 | 7 | ALU_F
+NODE | ier.D | 4291 | ? | 0 | 0 | ier | NULL | NULL | ier.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | ier.CLKF | 4119 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | ier.CLKF | 4294 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | ier.RSTF | 4120 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | ier.RSTF | 4295 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | ier.CE | 4121 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | ier.CE | 4296 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | ier.Q | 4122 | ? | 0 | 0 | ier | NULL | NULL | ier.REG | 0 | 8 | SRFF_Q
+NODE | ier.Q | 4297 | ? | 0 | 0 | ier | NULL | NULL | ier.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slaveinten | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | slaveinten | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slaveinten | 3982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
+NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2897 | 4037 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2897 | 0 | 5 | II_IMUX
+NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | slaveinten | 3982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
+NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | slaveinten.SI | slaveinten | 0 | 8 | 5
+SIGNAL_INSTANCE | slaveinten.SI | slaveinten | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slaveinten | 3982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
+NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2897 | 4037 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2897 | 0 | 5 | II_IMUX
+NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | slaveinten.D1 | 4124 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | slaveinten.D1 | 4299 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | slaveinten.D2 | 4125 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N2897
-SPPTERM | 4 | IV_FALSE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N2897
+SIGNAL | NODE | slaveinten.D2 | 4300 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3025
+SPPTERM | 4 | IV_FALSE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3025
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | slaveinten.CLKF | 4126 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | slaveinten.CLKF | 4301 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | slaveinten.RSTF | 4127 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | slaveinten.RSTF | 4302 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | slaveinten.CE | 4128 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | slaveinten.CE | 4303 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | slaveinten.REG | slaveinten | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | slaveinten.D | 4123 | ? | 0 | 0 | slaveinten | NULL | NULL | slaveinten.XOR | 0 | 7 | ALU_F
+NODE | slaveinten.D | 4298 | ? | 0 | 0 | slaveinten | NULL | NULL | slaveinten.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | slaveinten.CLKF | 4126 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | slaveinten.CLKF | 4301 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | slaveinten.RSTF | 4127 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | slaveinten.RSTF | 4302 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | slaveinten.CE | 4128 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | slaveinten.CE | 4303 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | slaveinten.Q | 4129 | ? | 0 | 0 | slaveinten | NULL | NULL | slaveinten.REG | 0 | 8 | SRFF_Q
+NODE | slaveinten.Q | 4304 | ? | 0 | 0 | slaveinten | NULL | NULL | slaveinten.REG | 0 | 8 | SRFF_Q
 
-INPUT_INSTANCE | 0 | 0 | NULL | N2895 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | N3023 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_d<3> | 4050 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<3> | 0 | 6 | OI_OUT
+NODE | cpu_d<3> | 4216 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<3> | 0 | 6 | OI_OUT
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | N2895 | 4036 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2895 | 0 | 5 | II_IMUX
+NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | tmo | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | tmo | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tmo | 3983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
+NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2895 | 4036 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2895 | 0 | 5 | II_IMUX
+NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | tmo | 3983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
+NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | tmo.SI | tmo | 0 | 8 | 5
+SIGNAL_INSTANCE | tmo.SI | tmo | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tmo | 3983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
+NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2895 | 4036 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2895 | 0 | 5 | II_IMUX
+NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | tmo.D1 | 4131 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | tmo.D1 | 4306 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | tmo.D2 | 4132 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N2895
-SPPTERM | 4 | IV_FALSE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N2895
+SIGNAL | NODE | tmo.D2 | 4307 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3023
+SPPTERM | 4 | IV_FALSE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3023
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | tmo.CLKF | 4133 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | tmo.CLKF | 4308 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | tmo.RSTF | 4134 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | tmo.RSTF | 4309 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | tmo.CE | 4135 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | tmo.CE | 4310 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | tmo.REG | tmo | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | tmo.D | 4130 | ? | 0 | 0 | tmo | NULL | NULL | tmo.XOR | 0 | 7 | ALU_F
+NODE | tmo.D | 4305 | ? | 0 | 0 | tmo | NULL | NULL | tmo.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | tmo.CLKF | 4133 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | tmo.CLKF | 4308 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | tmo.RSTF | 4134 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | tmo.RSTF | 4309 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | tmo.CE | 4135 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | tmo.CE | 4310 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | tmo.Q | 4136 | ? | 0 | 0 | tmo | NULL | NULL | tmo.REG | 0 | 8 | SRFF_Q
+NODE | tmo.Q | 4311 | ? | 0 | 0 | tmo | NULL | NULL | tmo.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | divisor<0> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | divisor<0> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<0> | 3984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
+NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | divisor<0> | 3984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
+NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | divisor<0>.SI | divisor<0> | 0 | 8 | 5
+SIGNAL_INSTANCE | divisor<0>.SI | divisor<0> | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<0> | 3984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
+NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | divisor<0>.D1 | 4138 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | divisor<0>.D1 | 4313 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | divisor<0>.D2 | 4139 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2889
-SPPTERM | 4 | IV_FALSE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2889
+SIGNAL | NODE | divisor<0>.D2 | 4314 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3017
+SPPTERM | 4 | IV_FALSE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3017
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | divisor<0>.CLKF | 4140 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | divisor<0>.CLKF | 4315 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | divisor<0>.RSTF | 4141 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | divisor<0>.RSTF | 4316 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | divisor<0>.CE | 4142 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | divisor<0>.CE | 4317 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | divisor<0>.REG | divisor<0> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | divisor<0>.D | 4137 | ? | 0 | 0 | divisor<0> | NULL | NULL | divisor<0>.XOR | 0 | 7 | ALU_F
+NODE | divisor<0>.D | 4312 | ? | 0 | 0 | divisor<0> | NULL | NULL | divisor<0>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | divisor<0>.CLKF | 4140 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | divisor<0>.CLKF | 4315 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | divisor<0>.RSTF | 4141 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | divisor<0>.RSTF | 4316 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | divisor<0>.CE | 4142 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | divisor<0>.CE | 4317 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | divisor<0>.Q | 4143 | ? | 0 | 0 | divisor<0> | NULL | NULL | divisor<0>.REG | 0 | 8 | SRFF_Q
+NODE | divisor<0>.Q | 4318 | ? | 0 | 0 | divisor<0> | NULL | NULL | divisor<0>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | divisor<1> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | divisor<1> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<1> | 3985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
+NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2891 | 4034 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2891 | 0 | 5 | II_IMUX
+NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | divisor<1> | 3985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
+NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | divisor<1>.SI | divisor<1> | 0 | 8 | 5
+SIGNAL_INSTANCE | divisor<1>.SI | divisor<1> | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<1> | 3985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
+NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2891 | 4034 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2891 | 0 | 5 | II_IMUX
+NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | divisor<1>.D1 | 4145 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | divisor<1>.D1 | 4320 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | divisor<1>.D2 | 4146 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2891
-SPPTERM | 4 | IV_FALSE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2891
+SIGNAL | NODE | divisor<1>.D2 | 4321 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3019
+SPPTERM | 4 | IV_FALSE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3019
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | divisor<1>.CLKF | 4147 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | divisor<1>.CLKF | 4322 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | divisor<1>.RSTF | 4148 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | divisor<1>.RSTF | 4323 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | divisor<1>.CE | 4149 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | divisor<1>.CE | 4324 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | divisor<1>.REG | divisor<1> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | divisor<1>.D | 4144 | ? | 0 | 0 | divisor<1> | NULL | NULL | divisor<1>.XOR | 0 | 7 | ALU_F
+NODE | divisor<1>.D | 4319 | ? | 0 | 0 | divisor<1> | NULL | NULL | divisor<1>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | divisor<1>.CLKF | 4147 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | divisor<1>.CLKF | 4322 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | divisor<1>.RSTF | 4148 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | divisor<1>.RSTF | 4323 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | divisor<1>.CE | 4149 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | divisor<1>.CE | 4324 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | divisor<1>.Q | 4150 | ? | 0 | 0 | divisor<1> | NULL | NULL | divisor<1>.REG | 0 | 8 | SRFF_Q
+NODE | divisor<1>.Q | 4325 | ? | 0 | 0 | divisor<1> | NULL | NULL | divisor<1>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | divisor<2> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | divisor<2> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<2> | 3986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
+NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2893 | 4035 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2893 | 0 | 5 | II_IMUX
+NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | divisor<2> | 3986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
+NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | divisor<2>.SI | divisor<2> | 0 | 8 | 5
+SIGNAL_INSTANCE | divisor<2>.SI | divisor<2> | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<2> | 3986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
+NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2893 | 4035 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2893 | 0 | 5 | II_IMUX
+NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | divisor<2>.D1 | 4152 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | divisor<2>.D1 | 4327 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | divisor<2>.D2 | 4153 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_TRUE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2893
-SPPTERM | 4 | IV_FALSE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2893
+SIGNAL | NODE | divisor<2>.D2 | 4328 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3021
+SPPTERM | 4 | IV_FALSE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3021
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | divisor<2>.CLKF | 4154 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | divisor<2>.CLKF | 4329 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | divisor<2>.RSTF | 4155 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | divisor<2>.RSTF | 4330 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | divisor<2>.CE | 4156 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | divisor<2>.CE | 4331 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | divisor<2>.REG | divisor<2> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | divisor<2>.D | 4151 | ? | 0 | 0 | divisor<2> | NULL | NULL | divisor<2>.XOR | 0 | 7 | ALU_F
+NODE | divisor<2>.D | 4326 | ? | 0 | 0 | divisor<2> | NULL | NULL | divisor<2>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | divisor<2>.CLKF | 4154 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | divisor<2>.CLKF | 4329 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | divisor<2>.RSTF | 4155 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | divisor<2>.RSTF | 4330 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | divisor<2>.CE | 4156 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | divisor<2>.CE | 4331 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | divisor<2>.Q | 4157 | ? | 0 | 0 | divisor<2> | NULL | NULL | divisor<2>.REG | 0 | 8 | SRFF_Q
+NODE | divisor<2>.Q | 4332 | ? | 0 | 0 | divisor<2> | NULL | NULL | divisor<2>.REG | 0 | 8 | SRFF_Q
 
 INPUT_INSTANCE | 0 | 0 | NULL | spi_miso_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | spi_miso | 4065 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | spi_miso | 4237 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | spi_miso_IBUF | 3987 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX
+NODE | spi_miso_IBUF | 4143 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<0> | spi6502b_COPY_0_COPY_0 | 2155873280 | 6 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spi_miso_IBUF | 3987 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX
+NODE | spi_miso_IBUF | 4143 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidatain<0> | 3988 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
+NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | spidatain<0>.SI | spidatain<0> | 0 | 6 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spi_miso_IBUF | 3987 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX
+NODE | spi_miso_IBUF | 4143 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidatain<0>.D1 | 4159 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidatain<0>.D1 | 4334 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidatain<0>.D2 | 4160 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | spidatain<0>.D2 | 4335 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 2 | IV_FALSE | slavesel | IV_TRUE | spi_miso_IBUF
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidatain<0>.CLKF | 4161 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<0>.CLKF | 4336 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | spidatain<0>.RSTF | 4162 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<0>.RSTF | 4337 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidatain<0>.CE | 4163 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<0>.CE | 4338 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | spidatain<0>.REG | spidatain<0> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidatain<0>.D | 4158 | ? | 0 | 0 | spidatain<0> | NULL | NULL | spidatain<0>.XOR | 0 | 7 | ALU_F
+NODE | spidatain<0>.D | 4333 | ? | 0 | 0 | spidatain<0> | NULL | NULL | spidatain<0>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidatain<0>.CLKF | 4161 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<0>.CLKF | 4336 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | spidatain<0>.RSTF | 4162 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<0>.RSTF | 4337 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidatain<0>.CE | 4163 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<0>.CE | 4338 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidatain<0>.Q | 4164 | ? | 0 | 0 | spidatain<0> | NULL | NULL | spidatain<0>.REG | 0 | 8 | SRFF_Q
+NODE | spidatain<0>.Q | 4339 | ? | 0 | 0 | spidatain<0> | NULL | NULL | spidatain<0>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<1> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<0> | 3988 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
+NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidatain<1> | 3989 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
+NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | spidatain<1>.SI | spidatain<1> | 0 | 5 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<0> | 3988 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
+NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidatain<1>.D1 | 4166 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidatain<1>.D1 | 4341 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidatain<1>.D2 | 4167 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | spidatain<1>.D2 | 4342 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 1 | IV_TRUE | spidatain<0>
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidatain<1>.CLKF | 4168 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<1>.CLKF | 4343 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | spidatain<1>.RSTF | 4169 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<1>.RSTF | 4344 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidatain<1>.CE | 4170 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<1>.CE | 4345 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | spidatain<1>.REG | spidatain<1> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidatain<1>.D | 4165 | ? | 0 | 0 | spidatain<1> | NULL | NULL | spidatain<1>.XOR | 0 | 7 | ALU_F
+NODE | spidatain<1>.D | 4340 | ? | 0 | 0 | spidatain<1> | NULL | NULL | spidatain<1>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidatain<1>.CLKF | 4168 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<1>.CLKF | 4343 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | spidatain<1>.RSTF | 4169 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<1>.RSTF | 4344 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidatain<1>.CE | 4170 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<1>.CE | 4345 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidatain<1>.Q | 4171 | ? | 0 | 0 | spidatain<1> | NULL | NULL | spidatain<1>.REG | 0 | 8 | SRFF_Q
+NODE | spidatain<1>.Q | 4346 | ? | 0 | 0 | spidatain<1> | NULL | NULL | spidatain<1>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<2> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<1> | 3989 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
+NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidatain<2> | 3990 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
+NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | spidatain<2>.SI | spidatain<2> | 0 | 5 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<1> | 3989 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
+NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidatain<2>.D1 | 4173 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidatain<2>.D1 | 4348 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidatain<2>.D2 | 4174 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | spidatain<2>.D2 | 4349 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 1 | IV_TRUE | spidatain<1>
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidatain<2>.CLKF | 4175 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<2>.CLKF | 4350 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | spidatain<2>.RSTF | 4176 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<2>.RSTF | 4351 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidatain<2>.CE | 4177 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<2>.CE | 4352 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | spidatain<2>.REG | spidatain<2> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidatain<2>.D | 4172 | ? | 0 | 0 | spidatain<2> | NULL | NULL | spidatain<2>.XOR | 0 | 7 | ALU_F
+NODE | spidatain<2>.D | 4347 | ? | 0 | 0 | spidatain<2> | NULL | NULL | spidatain<2>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidatain<2>.CLKF | 4175 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<2>.CLKF | 4350 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | spidatain<2>.RSTF | 4176 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<2>.RSTF | 4351 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidatain<2>.CE | 4177 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<2>.CE | 4352 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidatain<2>.Q | 4178 | ? | 0 | 0 | spidatain<2> | NULL | NULL | spidatain<2>.REG | 0 | 8 | SRFF_Q
+NODE | spidatain<2>.Q | 4353 | ? | 0 | 0 | spidatain<2> | NULL | NULL | spidatain<2>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<3> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<2> | 3990 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
+NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidatain<3> | 3991 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
+NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | spidatain<3>.SI | spidatain<3> | 0 | 5 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<2> | 3990 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
+NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidatain<3>.D1 | 4180 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidatain<3>.D1 | 4355 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidatain<3>.D2 | 4181 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | spidatain<3>.D2 | 4356 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 1 | IV_TRUE | spidatain<2>
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidatain<3>.CLKF | 4182 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<3>.CLKF | 4357 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | spidatain<3>.RSTF | 4183 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<3>.RSTF | 4358 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidatain<3>.CE | 4184 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<3>.CE | 4359 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | spidatain<3>.REG | spidatain<3> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidatain<3>.D | 4179 | ? | 0 | 0 | spidatain<3> | NULL | NULL | spidatain<3>.XOR | 0 | 7 | ALU_F
+NODE | spidatain<3>.D | 4354 | ? | 0 | 0 | spidatain<3> | NULL | NULL | spidatain<3>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidatain<3>.CLKF | 4182 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<3>.CLKF | 4357 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | spidatain<3>.RSTF | 4183 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<3>.RSTF | 4358 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidatain<3>.CE | 4184 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<3>.CE | 4359 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidatain<3>.Q | 4185 | ? | 0 | 0 | spidatain<3> | NULL | NULL | spidatain<3>.REG | 0 | 8 | SRFF_Q
+NODE | spidatain<3>.Q | 4360 | ? | 0 | 0 | spidatain<3> | NULL | NULL | spidatain<3>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<4> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<3> | 3991 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
+NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidatain<4> | 3992 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
+NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | spidatain<4>.SI | spidatain<4> | 0 | 5 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<3> | 3991 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
+NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidatain<4>.D1 | 4187 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidatain<4>.D1 | 4362 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidatain<4>.D2 | 4188 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | spidatain<4>.D2 | 4363 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 1 | IV_TRUE | spidatain<3>
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidatain<4>.CLKF | 4189 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<4>.CLKF | 4364 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | spidatain<4>.RSTF | 4190 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<4>.RSTF | 4365 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidatain<4>.CE | 4191 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<4>.CE | 4366 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | spidatain<4>.REG | spidatain<4> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidatain<4>.D | 4186 | ? | 0 | 0 | spidatain<4> | NULL | NULL | spidatain<4>.XOR | 0 | 7 | ALU_F
+NODE | spidatain<4>.D | 4361 | ? | 0 | 0 | spidatain<4> | NULL | NULL | spidatain<4>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidatain<4>.CLKF | 4189 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<4>.CLKF | 4364 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | spidatain<4>.RSTF | 4190 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<4>.RSTF | 4365 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidatain<4>.CE | 4191 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<4>.CE | 4366 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidatain<4>.Q | 4192 | ? | 0 | 0 | spidatain<4> | NULL | NULL | spidatain<4>.REG | 0 | 8 | SRFF_Q
+NODE | spidatain<4>.Q | 4367 | ? | 0 | 0 | spidatain<4> | NULL | NULL | spidatain<4>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<5> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<4> | 3992 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
+NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidatain<5> | 3993 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
+NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | spidatain<5>.SI | spidatain<5> | 0 | 5 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<4> | 3992 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
+NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidatain<5>.D1 | 4194 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidatain<5>.D1 | 4369 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidatain<5>.D2 | 4195 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | spidatain<5>.D2 | 4370 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 1 | IV_TRUE | spidatain<4>
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidatain<5>.CLKF | 4196 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<5>.CLKF | 4371 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | spidatain<5>.RSTF | 4197 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<5>.RSTF | 4372 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidatain<5>.CE | 4198 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<5>.CE | 4373 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | spidatain<5>.REG | spidatain<5> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidatain<5>.D | 4193 | ? | 0 | 0 | spidatain<5> | NULL | NULL | spidatain<5>.XOR | 0 | 7 | ALU_F
+NODE | spidatain<5>.D | 4368 | ? | 0 | 0 | spidatain<5> | NULL | NULL | spidatain<5>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidatain<5>.CLKF | 4196 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<5>.CLKF | 4371 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | spidatain<5>.RSTF | 4197 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<5>.RSTF | 4372 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidatain<5>.CE | 4198 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<5>.CE | 4373 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidatain<5>.Q | 4199 | ? | 0 | 0 | spidatain<5> | NULL | NULL | spidatain<5>.REG | 0 | 8 | SRFF_Q
+NODE | spidatain<5>.Q | 4374 | ? | 0 | 0 | spidatain<5> | NULL | NULL | spidatain<5>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<6> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<5> | 3993 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
+NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidatain<6> | 3994 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
+NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | spidatain<6>.SI | spidatain<6> | 0 | 5 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<5> | 3993 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
+NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidatain<6>.D1 | 4201 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidatain<6>.D1 | 4376 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidatain<6>.D2 | 4202 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | spidatain<6>.D2 | 4377 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 1 | IV_TRUE | spidatain<5>
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidatain<6>.CLKF | 4203 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<6>.CLKF | 4378 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | spidatain<6>.RSTF | 4204 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<6>.RSTF | 4379 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidatain<6>.CE | 4205 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<6>.CE | 4380 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | spidatain<6>.REG | spidatain<6> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidatain<6>.D | 4200 | ? | 0 | 0 | spidatain<6> | NULL | NULL | spidatain<6>.XOR | 0 | 7 | ALU_F
+NODE | spidatain<6>.D | 4375 | ? | 0 | 0 | spidatain<6> | NULL | NULL | spidatain<6>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidatain<6>.CLKF | 4203 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<6>.CLKF | 4378 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | spidatain<6>.RSTF | 4204 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<6>.RSTF | 4379 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidatain<6>.CE | 4205 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<6>.CE | 4380 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidatain<6>.Q | 4206 | ? | 0 | 0 | spidatain<6> | NULL | NULL | spidatain<6>.REG | 0 | 8 | SRFF_Q
+NODE | spidatain<6>.Q | 4381 | ? | 0 | 0 | spidatain<6> | NULL | NULL | spidatain<6>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | nio_stb_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | nio_stb | 4238 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | a9_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | a9 | 4239 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | a8_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | a8 | 4240 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | a10_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | a10 | 4241 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<7> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<6> | 3994 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
+NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidatain<7> | 3995 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM
+NODE | spidatain<7> | 4155 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | spidatain<7>.SI | spidatain<7> | 0 | 5 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<6> | 3994 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
+NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidatain<7>.D1 | 4208 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidatain<7>.D1 | 4383 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidatain<7>.D2 | 4209 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | spidatain<7>.D2 | 4384 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 1 | IV_TRUE | spidatain<6>
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidatain<7>.CLKF | 4210 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<7>.CLKF | 4385 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | spidatain<7>.RSTF | 4211 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<7>.RSTF | 4386 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidatain<7>.CE | 4212 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<7>.CE | 4387 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | spidatain<7>.REG | spidatain<7> | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidatain<7>.D | 4207 | ? | 0 | 0 | spidatain<7> | NULL | NULL | spidatain<7>.XOR | 0 | 7 | ALU_F
+NODE | spidatain<7>.D | 4382 | ? | 0 | 0 | spidatain<7> | NULL | NULL | spidatain<7>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidatain<7>.CLKF | 4210 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | spidatain<7>.CLKF | 4385 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | spidatain<7>.RSTF | 4211 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | spidatain<7>.RSTF | 4386 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidatain<7>.CE | 4212 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidatain<7>.CE | 4387 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidatain<7>.Q | 4213 | ? | 0 | 0 | spidatain<7> | NULL | NULL | spidatain<7>.REG | 0 | 8 | SRFF_Q
+NODE | spidatain<7>.Q | 4388 | ? | 0 | 0 | spidatain<7> | NULL | NULL | spidatain<7>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | int_sclk | spi6502b_COPY_0_COPY_0 | 2155873280 | 8 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpol | 3977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
+NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | EXP7_.EXP | 4392 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP7_.EXP | EXP7_ | 4 | 0 | MC_EXPORT
+NODE | shiftcnt<1>.EXP | 4591 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.EXP | shiftcnt<1> | 4 | 0 | MC_EXPORT
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_sclk | 3996 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_sclk.Q | int_sclk | 0 | 0 | MC_Q
+NODE | int_sclk | 4156 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_sclk.Q | int_sclk | 0 | 0 | MC_Q
 
 SIGNAL_INSTANCE | int_sclk.SI | int_sclk | 0 | 8 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpol | 3977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
+NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | EXP7_.EXP | 4392 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP7_.EXP | EXP7_ | 4 | 0 | MC_EXPORT
+NODE | shiftcnt<1>.EXP | 4591 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.EXP | shiftcnt<1> | 4 | 0 | MC_EXPORT
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_sclk.D1 | 4215 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_sclk.D1 | 4390 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 1 | IV_TRUE | cpol
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_sclk.D2 | 4216 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 1 | IV_TRUE | EXP7_.EXP
+SIGNAL | NODE | int_sclk.D2 | 4391 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | shiftcnt<1>.EXP
 SPPTERM | 5 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpha | IV_TRUE | shiftcnt<0> | IV_FALSE | shiftdone | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | int_sclk.CLKF | 4217 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | int_sclk.CLKF | 4392 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF
-SIGNAL | NODE | int_sclk.SETF | 4218 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 5 | 9 | MC_SI_SETF
+SIGNAL | NODE | int_sclk.SETF | 4393 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 5 | 9 | MC_SI_SETF
 SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_TRUE | cpol
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | int_sclk.RSTF | 4219 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | int_sclk.RSTF | 4394 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_FALSE | cpol
 
 SRFF_INSTANCE | int_sclk.REG | int_sclk | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_sclk.D | 4214 | ? | 0 | 0 | int_sclk | NULL | NULL | int_sclk.XOR | 0 | 7 | ALU_F
+NODE | int_sclk.D | 4389 | ? | 0 | 0 | int_sclk | NULL | NULL | int_sclk.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | int_sclk.CLKF | 4217 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | int_sclk.CLKF | 4392 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 2 | 8 | SRFF_S
-SIGNAL | NODE | int_sclk.SETF | 4218 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 5 | 9 | MC_SI_SETF
+SIGNAL | NODE | int_sclk.SETF | 4393 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 5 | 9 | MC_SI_SETF
 SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_TRUE | cpol
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | int_sclk.RSTF | 4219 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | int_sclk.RSTF | 4394 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_FALSE | cpol
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_sclk.Q | 4220 | ? | 0 | 0 | int_sclk | NULL | NULL | int_sclk.REG | 0 | 8 | SRFF_Q
+NODE | int_sclk.Q | 4395 | ? | 0 | 0 | int_sclk | NULL | NULL | int_sclk.REG | 0 | 8 | SRFF_Q
 
 INPUT_INSTANCE | 0 | 0 | NULL | cpu_Nphi2_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_Nphi2 | 4071 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | cpu_Nphi2 | 4247 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<3> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2
+MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<3> | spi6502b_COPY_0_COPY_0 | 2155888640 | 7 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<3> | 3991 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tmo | 3983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
+NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_dout<3> | 3998 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.Q | int_dout<3> | 0 | 0 | MC_Q
+NODE | int_dout<3> | 4158 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.Q | int_dout<3> | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_dout<3>$OE | 3999 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.BUFOE.OUT | int_dout<3> | 2 | 0 | MC_OE
+NODE | int_dout<3>$OE | 4159 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.BUFOE.OUT | int_dout<3> | 2 | 0 | MC_OE
 
-SIGNAL_INSTANCE | int_dout<3>.SI | int_dout<3> | 0 | 8 | 3
+SIGNAL_INSTANCE | int_dout<3>.SI | int_dout<3> | 0 | 7 | 3
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<3> | 3991 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tmo | 3983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
+NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_dout<3>.D1 | 4222 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_dout<3>.D1 | 4397 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_dout<3>.D2 | 4223 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<3> | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<3>.D2 | 4398 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<3> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_dout<3>.TRST | 4225 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<3>.TRST | 4400 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 
 SRFF_INSTANCE | int_dout<3>.REG | int_dout<3> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_dout<3>.D | 4221 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.XOR | 0 | 7 | ALU_F
+NODE | int_dout<3>.D | 4396 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_dout<3>.Q | 4226 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.REG | 0 | 8 | SRFF_Q
+NODE | int_dout<3>.Q | 4401 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_dout<3>.BUFOE | int_dout<3> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_dout<3>.TRST | 4225 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<3>.TRST | 4400 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_dout<3>.BUFOE.OUT | 4224 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.BUFOE | 0 | 10 | BUF_OUT
+NODE | int_dout<3>.BUFOE.OUT | 4399 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.BUFOE | 0 | 10 | BUF_OUT
 
-MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<5> | spi6502b_COPY_0_COPY_0 | 2155888640 | 9 | 2
+MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<5> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<5> | 3993 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
+NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_dout<5> | 4000 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.Q | int_dout<5> | 0 | 0 | MC_Q
+NODE | int_dout<5> | 4160 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.Q | int_dout<5> | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_dout<5>$OE | 4001 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.BUFOE.OUT | int_dout<5> | 2 | 0 | MC_OE
+NODE | int_dout<5>$OE | 4161 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.BUFOE.OUT | int_dout<5> | 2 | 0 | MC_OE
 
-SIGNAL_INSTANCE | int_dout<5>.SI | int_dout<5> | 0 | 9 | 3
+SIGNAL_INSTANCE | int_dout<5>.SI | int_dout<5> | 0 | 8 | 3
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<5> | 3993 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
+NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_dout<5>.D1 | 4228 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_dout<5>.D1 | 4403 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_dout<5>.D2 | 4229 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<5> | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | start_shifting | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | shifting2 | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<5>.D2 | 4404 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<5> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | start_shifting | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | shifting2 | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_dout<5>.TRST | 4231 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<5>.TRST | 4406 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 
 SRFF_INSTANCE | int_dout<5>.REG | int_dout<5> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_dout<5>.D | 4227 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.XOR | 0 | 7 | ALU_F
+NODE | int_dout<5>.D | 4402 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_dout<5>.Q | 4232 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.REG | 0 | 8 | SRFF_Q
+NODE | int_dout<5>.Q | 4407 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_dout<5>.BUFOE | int_dout<5> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_dout<5>.TRST | 4231 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<5>.TRST | 4406 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_dout<5>.BUFOE.OUT | 4230 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.BUFOE | 0 | 10 | BUF_OUT
+NODE | int_dout<5>.BUFOE.OUT | 4405 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.BUFOE | 0 | 10 | BUF_OUT
 
-MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<6> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2
+MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<6> | spi6502b_COPY_0_COPY_0 | 2155888640 | 7 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<6> | 3994 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ier | 3981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
+NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_dout<6> | 4002 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.Q | int_dout<6> | 0 | 0 | MC_Q
+NODE | int_dout<6> | 4162 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.Q | int_dout<6> | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_dout<6>$OE | 4003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.BUFOE.OUT | int_dout<6> | 2 | 0 | MC_OE
+NODE | int_dout<6>$OE | 4163 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.BUFOE.OUT | int_dout<6> | 2 | 0 | MC_OE
 
-SIGNAL_INSTANCE | int_dout<6>.SI | int_dout<6> | 0 | 8 | 3
+SIGNAL_INSTANCE | int_dout<6>.SI | int_dout<6> | 0 | 7 | 3
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<6> | 3994 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ier | 3981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
+NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_dout<6>.D1 | 4234 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_dout<6>.D1 | 4409 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_dout<6>.D2 | 4235 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<6> | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<6>.D2 | 4410 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<6> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_dout<6>.TRST | 4237 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<6>.TRST | 4412 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 
 SRFF_INSTANCE | int_dout<6>.REG | int_dout<6> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_dout<6>.D | 4233 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.XOR | 0 | 7 | ALU_F
+NODE | int_dout<6>.D | 4408 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_dout<6>.Q | 4238 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.REG | 0 | 8 | SRFF_Q
+NODE | int_dout<6>.Q | 4413 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_dout<6>.BUFOE | int_dout<6> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_dout<6>.TRST | 4237 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<6>.TRST | 4412 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_dout<6>.BUFOE.OUT | 4236 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.BUFOE | 0 | 10 | BUF_OUT
+NODE | int_dout<6>.BUFOE.OUT | 4411 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.BUFOE | 0 | 10 | BUF_OUT
 
-MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<7> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2
+MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<7> | spi6502b_COPY_0_COPY_0 | 2155888640 | 7 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<7> | 3995 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<7> | 4155 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tc | 4012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
+NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_dout<7> | 4004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.Q | int_dout<7> | 0 | 0 | MC_Q
+NODE | int_dout<7> | 4164 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.Q | int_dout<7> | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_dout<7>$OE | 4005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.BUFOE.OUT | int_dout<7> | 2 | 0 | MC_OE
+NODE | int_dout<7>$OE | 4165 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.BUFOE.OUT | int_dout<7> | 2 | 0 | MC_OE
 
-SIGNAL_INSTANCE | int_dout<7>.SI | int_dout<7> | 0 | 8 | 3
+SIGNAL_INSTANCE | int_dout<7>.SI | int_dout<7> | 0 | 7 | 3
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<7> | 3995 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<7> | 4155 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tc | 4012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
+NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_dout<7>.D1 | 4240 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_dout<7>.D1 | 4415 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_dout<7>.D2 | 4241 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<7> | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | tc | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<7>.D2 | 4416 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<7> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | tc | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_dout<7>.TRST | 4243 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<7>.TRST | 4418 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 
 SRFF_INSTANCE | int_dout<7>.REG | int_dout<7> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_dout<7>.D | 4239 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.XOR | 0 | 7 | ALU_F
+NODE | int_dout<7>.D | 4414 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_dout<7>.Q | 4244 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.REG | 0 | 8 | SRFF_Q
+NODE | int_dout<7>.Q | 4419 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_dout<7>.BUFOE | int_dout<7> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_dout<7>.TRST | 4243 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<7>.TRST | 4418 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_dout<7>.BUFOE.OUT | 4242 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.BUFOE | 0 | 10 | BUF_OUT
+NODE | int_dout<7>.BUFOE.OUT | 4417 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.BUFOE | 0 | 10 | BUF_OUT
 
 MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | shiftcnt<3> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | shiftcnt<3>.SI | shiftcnt<3> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | shiftcnt<3>.D1 | 4246 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | shiftcnt<3>.D1 | 4421 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | shiftcnt<3>.D2 | 4247 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | shiftcnt<3>.D2 | 4422 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 2 | IV_TRUE | shiftcnt<3> | IV_FALSE | shifting2
 SPPTERM | 4 | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | shiftcnt<3>.CLKF | 4248 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftcnt<3>.CLKF | 4423 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | shiftcnt<3>.RSTF | 4249 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftcnt<3>.RSTF | 4424 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 
 SRFF_INSTANCE | shiftcnt<3>.REG | shiftcnt<3> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | shiftcnt<3>.D | 4245 | ? | 0 | 0 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.XOR | 0 | 7 | ALU_F
+NODE | shiftcnt<3>.D | 4420 | ? | 0 | 0 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | shiftcnt<3>.CLKF | 4248 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftcnt<3>.CLKF | 4423 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | shiftcnt<3>.RSTF | 4249 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftcnt<3>.RSTF | 4424 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | shiftcnt<3>.Q | 4250 | ? | 0 | 0 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.REG | 0 | 8 | SRFF_Q
+NODE | shiftcnt<3>.Q | 4425 | ? | 0 | 0 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | shiftcnt<2> | spi6502b_COPY_0_COPY_0 | 2155877376 | 6 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | shiftcnt<2>.SI | shiftcnt<2> | 0 | 6 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | shiftcnt<2>.D1 | 4252 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | shiftcnt<2>.D1 | 4427 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | shiftcnt<2>.D2 | 4253 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | shiftcnt<2>.D2 | 4428 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 2 | IV_TRUE | shiftcnt<2> | IV_FALSE | shifting2
 SPPTERM | 3 | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | shiftcnt<2>.CLKF | 4254 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftcnt<2>.CLKF | 4429 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | shiftcnt<2>.RSTF | 4255 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftcnt<2>.RSTF | 4430 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 
 SRFF_INSTANCE | shiftcnt<2>.REG | shiftcnt<2> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | shiftcnt<2>.D | 4251 | ? | 0 | 0 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.XOR | 0 | 7 | ALU_F
+NODE | shiftcnt<2>.D | 4426 | ? | 0 | 0 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | shiftcnt<2>.CLKF | 4254 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftcnt<2>.CLKF | 4429 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | shiftcnt<2>.RSTF | 4255 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftcnt<2>.RSTF | 4430 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | shiftcnt<2>.Q | 4256 | ? | 0 | 0 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.REG | 0 | 8 | SRFF_Q
+NODE | shiftcnt<2>.Q | 4431 | ? | 0 | 0 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftcnt<0> | spi6502b_COPY_0_COPY_0 | 2155873280 | 4 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | shiftcnt<0>.SI | shiftcnt<0> | 0 | 4 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | shiftcnt<0>.D1 | 4258 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | shiftcnt<0>.D1 | 4433 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | shiftcnt<0>.D2 | 4259 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | shiftcnt<0>.D2 | 4434 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 2 | IV_FALSE | shiftcnt<0> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | shiftcnt<0>.CLKF | 4260 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftcnt<0>.CLKF | 4435 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | shiftcnt<0>.RSTF | 4261 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftcnt<0>.RSTF | 4436 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 
 SRFF_INSTANCE | shiftcnt<0>.REG | shiftcnt<0> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | shiftcnt<0>.D | 4257 | ? | 0 | 0 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.XOR | 0 | 7 | ALU_F
+NODE | shiftcnt<0>.D | 4432 | ? | 0 | 0 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | shiftcnt<0>.CLKF | 4260 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftcnt<0>.CLKF | 4435 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | shiftcnt<0>.RSTF | 4261 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftcnt<0>.RSTF | 4436 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | shiftcnt<0>.Q | 4262 | ? | 0 | 0 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.REG | 0 | 8 | SRFF_Q
+NODE | shiftcnt<0>.Q | 4437 | ? | 0 | 0 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftcnt<1> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1
+MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftcnt<1> | spi6502b_COPY_0_COPY_0 | 2155873280 | 7 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | shiftcnt<1>.EXP | 4591 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.EXP | shiftcnt<1> | 4 | 0 | MC_EXPORT
 
-SIGNAL_INSTANCE | shiftcnt<1>.SI | shiftcnt<1> | 0 | 5 | 4
+SIGNAL_INSTANCE | shiftcnt<1>.SI | shiftcnt<1> | 0 | 7 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | shiftcnt<1>.D1 | 4264 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | shiftcnt<1>.D1 | 4439 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | shiftcnt<1>.D2 | 4265 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | shiftcnt<1>.D2 | 4440 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 3 | IV_TRUE | shiftcnt<0> | IV_FALSE | shiftcnt<1> | IV_TRUE | shifting2
 SPPTERM | 3 | IV_FALSE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | shiftcnt<1>.CLKF | 4266 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftcnt<1>.CLKF | 4441 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | shiftcnt<1>.RSTF | 4267 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftcnt<1>.RSTF | 4442 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | shiftcnt<1>.EXP | 4590 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 5 | IV_TRUE | cpu_Nres_IBUF | IV_TRUE | cpha | IV_FALSE | shiftcnt<0> | IV_FALSE | shiftdone | IV_TRUE | shifting2
 
 SRFF_INSTANCE | shiftcnt<1>.REG | shiftcnt<1> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | shiftcnt<1>.D | 4263 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.XOR | 0 | 7 | ALU_F
+NODE | shiftcnt<1>.D | 4438 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | shiftcnt<1>.CLKF | 4266 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftcnt<1>.CLKF | 4441 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | shiftcnt<1>.RSTF | 4267 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftcnt<1>.RSTF | 4442 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | shiftcnt<1>.Q | 4268 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.REG | 0 | 8 | SRFF_Q
+NODE | shiftcnt<1>.Q | 4443 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftdone | spi6502b_COPY_0_COPY_0 | 2155873280 | 6 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | shiftdone.SI | shiftdone | 0 | 6 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
+NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | shiftdone.D1 | 4270 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | shiftdone.D1 | 4445 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | shiftdone.D2 | 4271 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | shiftdone.D2 | 4446 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 4 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1>
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | shiftdone.CLKF | 4272 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftdone.CLKF | 4447 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | shiftdone.RSTF | 4273 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftdone.RSTF | 4448 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 
 SRFF_INSTANCE | shiftdone.REG | shiftdone | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | shiftdone.D | 4269 | ? | 0 | 0 | shiftdone | NULL | NULL | shiftdone.XOR | 0 | 7 | ALU_F
+NODE | shiftdone.D | 4444 | ? | 0 | 0 | shiftdone | NULL | NULL | shiftdone.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | shiftdone.CLKF | 4272 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shiftdone.CLKF | 4447 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | shiftdone.RSTF | 4273 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | shiftdone.RSTF | 4448 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | shiftdone.Q | 4274 | ? | 0 | 0 | shiftdone | NULL | NULL | shiftdone.REG | 0 | 8 | SRFF_Q
+NODE | shiftdone.Q | 4449 | ? | 0 | 0 | shiftdone | NULL | NULL | shiftdone.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | start_shifting | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | start_shifting | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | frx | 3980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
+NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4061 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM
+NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4232 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | start_shifting.SI | start_shifting | 0 | 8 | 4
+SIGNAL_INSTANCE | start_shifting.SI | start_shifting | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | frx | 3980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
+NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4061 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM
+NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4232 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | start_shifting.D1 | 4276 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | start_shifting.D1 | 4451 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | start_shifting.D2 | 4277 | ? | 0 | 6144 | start_shifting | NULL | NULL | start_shifting.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | start_shifting.D2 | 4452 | ? | 0 | 6144 | start_shifting | NULL | NULL | start_shifting.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 4 | IV_FALSE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | start_shifting | IV_FALSE | cpu_a_0_IBUF
 SPPTERM | 4 | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | start_shifting | IV_FALSE | cpu_a_0_IBUF
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | start_shifting.CLKF | 4278 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | start_shifting.CLKF | 4453 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
-SIGNAL | NODE | start_shifting.RSTF | 4279 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | start_shifting.RSTF | 4454 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | start_shifting/start_shifting_RSTF__$INT.UIM
 
 SRFF_INSTANCE | start_shifting.REG | start_shifting | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | start_shifting.D | 4275 | ? | 0 | 0 | start_shifting | NULL | NULL | start_shifting.XOR | 0 | 7 | ALU_F
+NODE | start_shifting.D | 4450 | ? | 0 | 0 | start_shifting | NULL | NULL | start_shifting.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | start_shifting.CLKF | 4278 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | start_shifting.CLKF | 4453 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 3 | 8 | SRFF_R
-SIGNAL | NODE | start_shifting.RSTF | 4279 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 6 | 9 | MC_SI_RSTF
+SIGNAL | NODE | start_shifting.RSTF | 4454 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 6 | 9 | MC_SI_RSTF
 SPPTERM | 1 | IV_FALSE | start_shifting/start_shifting_RSTF__$INT.UIM
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | start_shifting.Q | 4280 | ? | 0 | 0 | start_shifting | NULL | NULL | start_shifting.REG | 0 | 8 | SRFF_Q
+NODE | start_shifting.Q | 4455 | ? | 0 | 0 | start_shifting | NULL | NULL | start_shifting.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+OptxMapped+Ce | tc | spi6502b_COPY_0_COPY_0 | 2424308736 | 5 | 1
+MACROCELL_INSTANCE | PrldLow+OptxMapped | tc | spi6502b_COPY_0_COPY_0 | 2155873280 | 4 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | tc | 4012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
+NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | tc.SI | tc | 0 | 5 | 5
+SIGNAL_INSTANCE | tc.SI | tc | 0 | 4 | 5
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | tc.D1 | 4282 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | tc.D1 | 4457 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | tc.D2 | 4283 | ? | 0 | 6144 | tc | NULL | NULL | tc.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | tc.D2 | 4458 | ? | 0 | 6144 | tc | NULL | NULL | tc.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | tc.CLKF | 4284 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | tc.CLKF | 4459 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF
-SIGNAL | NODE | tc.SETF | 4285 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 5 | 9 | MC_SI_SETF
+SIGNAL | NODE | tc.SETF | 4460 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 5 | 9 | MC_SI_SETF
 SPPTERM | 1 | IV_TRUE | shiftdone
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | tc.CE | 4286 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | tc.CE | 4461 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF
 
 SRFF_INSTANCE | tc.REG | tc | 0 | 4 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | tc.D | 4281 | ? | 0 | 0 | tc | NULL | NULL | tc.XOR | 0 | 7 | ALU_F
+NODE | tc.D | 4456 | ? | 0 | 0 | tc | NULL | NULL | tc.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | tc.CLKF | 4284 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | tc.CLKF | 4459 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 2 | 8 | SRFF_S
-SIGNAL | NODE | tc.SETF | 4285 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 5 | 9 | MC_SI_SETF
+SIGNAL | NODE | tc.SETF | 4460 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 5 | 9 | MC_SI_SETF
 SPPTERM | 1 | IV_TRUE | shiftdone
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | tc.CE | 4286 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | tc.CE | 4461 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | tc.Q | 4287 | ? | 0 | 0 | tc | NULL | NULL | tc.REG | 0 | 8 | SRFF_Q
+NODE | tc.Q | 4462 | ? | 0 | 0 | tc | NULL | NULL | tc.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<0> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<0> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<0> | 4013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
+NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidataout<0> | 4013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
+NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | spidataout<0>.SI | spidataout<0> | 0 | 8 | 4
+SIGNAL_INSTANCE | spidataout<0>.SI | spidataout<0> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<0> | 4013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
+NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2889 | 4033 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2889 | 0 | 5 | II_IMUX
+NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidataout<0>.D1 | 4289 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidataout<0>.D1 | 4464 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidataout<0>.D2 | 4290 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<0> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2889
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<0> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2889
+SIGNAL | NODE | spidataout<0>.D2 | 4465 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<0> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3017
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<0> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3017
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidataout<0>.CLKF | 4291 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<0>.CLKF | 4466 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidataout<0>.CE | 4292 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<0>.CE | 4467 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | spidataout<0>.REG | spidataout<0> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidataout<0>.D | 4288 | ? | 0 | 0 | spidataout<0> | NULL | NULL | spidataout<0>.XOR | 0 | 7 | ALU_F
+NODE | spidataout<0>.D | 4463 | ? | 0 | 0 | spidataout<0> | NULL | NULL | spidataout<0>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidataout<0>.CLKF | 4291 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<0>.CLKF | 4466 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidataout<0>.CE | 4292 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<0>.CE | 4467 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidataout<0>.Q | 4293 | ? | 0 | 0 | spidataout<0> | NULL | NULL | spidataout<0>.REG | 0 | 8 | SRFF_Q
+NODE | spidataout<0>.Q | 4468 | ? | 0 | 0 | spidataout<0> | NULL | NULL | spidataout<0>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<1> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<1> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<1> | 4014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
+NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2891 | 4034 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2891 | 0 | 5 | II_IMUX
+NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidataout<1> | 4014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
+NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | spidataout<1>.SI | spidataout<1> | 0 | 8 | 4
+SIGNAL_INSTANCE | spidataout<1>.SI | spidataout<1> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<1> | 4014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
+NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2891 | 4034 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2891 | 0 | 5 | II_IMUX
+NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidataout<1>.D1 | 4295 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidataout<1>.D1 | 4470 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidataout<1>.D2 | 4296 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<1> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2891
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<1> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2891
+SIGNAL | NODE | spidataout<1>.D2 | 4471 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<1> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3019
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<1> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3019
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidataout<1>.CLKF | 4297 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<1>.CLKF | 4472 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidataout<1>.CE | 4298 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<1>.CE | 4473 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | spidataout<1>.REG | spidataout<1> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidataout<1>.D | 4294 | ? | 0 | 0 | spidataout<1> | NULL | NULL | spidataout<1>.XOR | 0 | 7 | ALU_F
+NODE | spidataout<1>.D | 4469 | ? | 0 | 0 | spidataout<1> | NULL | NULL | spidataout<1>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidataout<1>.CLKF | 4297 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<1>.CLKF | 4472 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidataout<1>.CE | 4298 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<1>.CE | 4473 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidataout<1>.Q | 4299 | ? | 0 | 0 | spidataout<1> | NULL | NULL | spidataout<1>.REG | 0 | 8 | SRFF_Q
+NODE | spidataout<1>.Q | 4474 | ? | 0 | 0 | spidataout<1> | NULL | NULL | spidataout<1>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<2> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<2> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<2> | 4015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
+NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2893 | 4035 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2893 | 0 | 5 | II_IMUX
+NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidataout<2> | 4015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
+NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | spidataout<2>.SI | spidataout<2> | 0 | 8 | 4
+SIGNAL_INSTANCE | spidataout<2>.SI | spidataout<2> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<2> | 4015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
+NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2893 | 4035 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2893 | 0 | 5 | II_IMUX
+NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidataout<2>.D1 | 4301 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidataout<2>.D1 | 4476 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidataout<2>.D2 | 4302 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<2> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2893
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<2> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2893
+SIGNAL | NODE | spidataout<2>.D2 | 4477 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<2> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3021
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<2> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3021
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidataout<2>.CLKF | 4303 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<2>.CLKF | 4478 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidataout<2>.CE | 4304 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<2>.CE | 4479 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | spidataout<2>.REG | spidataout<2> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidataout<2>.D | 4300 | ? | 0 | 0 | spidataout<2> | NULL | NULL | spidataout<2>.XOR | 0 | 7 | ALU_F
+NODE | spidataout<2>.D | 4475 | ? | 0 | 0 | spidataout<2> | NULL | NULL | spidataout<2>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidataout<2>.CLKF | 4303 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<2>.CLKF | 4478 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidataout<2>.CE | 4304 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<2>.CE | 4479 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidataout<2>.Q | 4305 | ? | 0 | 0 | spidataout<2> | NULL | NULL | spidataout<2>.REG | 0 | 8 | SRFF_Q
+NODE | spidataout<2>.Q | 4480 | ? | 0 | 0 | spidataout<2> | NULL | NULL | spidataout<2>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<3> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<3> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<3> | 4016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
+NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2895 | 4036 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2895 | 0 | 5 | II_IMUX
+NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidataout<3> | 4016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
+NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | spidataout<3>.SI | spidataout<3> | 0 | 8 | 4
+SIGNAL_INSTANCE | spidataout<3>.SI | spidataout<3> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<3> | 4016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
+NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2895 | 4036 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2895 | 0 | 5 | II_IMUX
+NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidataout<3>.D1 | 4307 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidataout<3>.D1 | 4482 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidataout<3>.D2 | 4308 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<3> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2895
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<3> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2895
+SIGNAL | NODE | spidataout<3>.D2 | 4483 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<3> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3023
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<3> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3023
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidataout<3>.CLKF | 4309 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<3>.CLKF | 4484 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidataout<3>.CE | 4310 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<3>.CE | 4485 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | spidataout<3>.REG | spidataout<3> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidataout<3>.D | 4306 | ? | 0 | 0 | spidataout<3> | NULL | NULL | spidataout<3>.XOR | 0 | 7 | ALU_F
+NODE | spidataout<3>.D | 4481 | ? | 0 | 0 | spidataout<3> | NULL | NULL | spidataout<3>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidataout<3>.CLKF | 4309 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<3>.CLKF | 4484 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidataout<3>.CE | 4310 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<3>.CE | 4485 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidataout<3>.Q | 4311 | ? | 0 | 0 | spidataout<3> | NULL | NULL | spidataout<3>.REG | 0 | 8 | SRFF_Q
+NODE | spidataout<3>.Q | 4486 | ? | 0 | 0 | spidataout<3> | NULL | NULL | spidataout<3>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<4> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<4> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<4> | 4017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
+NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2897 | 4037 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2897 | 0 | 5 | II_IMUX
+NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidataout<4> | 4017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
+NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | spidataout<4>.SI | spidataout<4> | 0 | 8 | 4
+SIGNAL_INSTANCE | spidataout<4>.SI | spidataout<4> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<4> | 4017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
+NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2897 | 4037 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2897 | 0 | 5 | II_IMUX
+NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidataout<4>.D1 | 4313 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidataout<4>.D1 | 4488 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidataout<4>.D2 | 4314 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<4> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2897
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<4> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2897
+SIGNAL | NODE | spidataout<4>.D2 | 4489 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<4> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3025
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<4> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3025
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidataout<4>.CLKF | 4315 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<4>.CLKF | 4490 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidataout<4>.CE | 4316 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<4>.CE | 4491 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | spidataout<4>.REG | spidataout<4> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidataout<4>.D | 4312 | ? | 0 | 0 | spidataout<4> | NULL | NULL | spidataout<4>.XOR | 0 | 7 | ALU_F
+NODE | spidataout<4>.D | 4487 | ? | 0 | 0 | spidataout<4> | NULL | NULL | spidataout<4>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidataout<4>.CLKF | 4315 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<4>.CLKF | 4490 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidataout<4>.CE | 4316 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<4>.CE | 4491 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidataout<4>.Q | 4317 | ? | 0 | 0 | spidataout<4> | NULL | NULL | spidataout<4>.REG | 0 | 8 | SRFF_Q
+NODE | spidataout<4>.Q | 4492 | ? | 0 | 0 | spidataout<4> | NULL | NULL | spidataout<4>.REG | 0 | 8 | SRFF_Q
 
-INPUT_INSTANCE | 0 | 0 | NULL | N2899 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | N3027 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_d<5> | 4051 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<5> | 0 | 6 | OI_OUT
+NODE | cpu_d<5> | 4217 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<5> | 0 | 6 | OI_OUT
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | N2899 | 4040 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2899 | 0 | 5 | II_IMUX
+NODE | N3027 | 4203 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3027 | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<5> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<5> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<5> | 4018 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
+NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2899 | 4040 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2899 | 0 | 5 | II_IMUX
+NODE | N3027 | 4203 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3027 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidataout<5> | 4018 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
+NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | spidataout<5>.SI | spidataout<5> | 0 | 8 | 4
+SIGNAL_INSTANCE | spidataout<5>.SI | spidataout<5> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<5> | 4018 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
+NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2899 | 4040 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2899 | 0 | 5 | II_IMUX
+NODE | N3027 | 4203 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3027 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidataout<5>.D1 | 4319 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidataout<5>.D1 | 4494 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidataout<5>.D2 | 4320 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<5> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2899
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<5> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2899
+SIGNAL | NODE | spidataout<5>.D2 | 4495 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<5> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3027
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<5> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3027
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidataout<5>.CLKF | 4321 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<5>.CLKF | 4496 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidataout<5>.CE | 4322 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<5>.CE | 4497 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | spidataout<5>.REG | spidataout<5> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidataout<5>.D | 4318 | ? | 0 | 0 | spidataout<5> | NULL | NULL | spidataout<5>.XOR | 0 | 7 | ALU_F
+NODE | spidataout<5>.D | 4493 | ? | 0 | 0 | spidataout<5> | NULL | NULL | spidataout<5>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidataout<5>.CLKF | 4321 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<5>.CLKF | 4496 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidataout<5>.CE | 4322 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<5>.CE | 4497 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidataout<5>.Q | 4323 | ? | 0 | 0 | spidataout<5> | NULL | NULL | spidataout<5>.REG | 0 | 8 | SRFF_Q
+NODE | spidataout<5>.Q | 4498 | ? | 0 | 0 | spidataout<5> | NULL | NULL | spidataout<5>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<6> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<6> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<6> | 4019 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
+NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2901 | 4038 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2901 | 0 | 5 | II_IMUX
+NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidataout<6> | 4019 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
+NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | spidataout<6>.SI | spidataout<6> | 0 | 8 | 4
+SIGNAL_INSTANCE | spidataout<6>.SI | spidataout<6> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<6> | 4019 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
+NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2901 | 4038 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2901 | 0 | 5 | II_IMUX
+NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidataout<6>.D1 | 4325 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidataout<6>.D1 | 4500 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidataout<6>.D2 | 4326 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<6> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2901
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<6> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2901
+SIGNAL | NODE | spidataout<6>.D2 | 4501 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<6> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3029
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<6> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3029
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidataout<6>.CLKF | 4327 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<6>.CLKF | 4502 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidataout<6>.CE | 4328 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<6>.CE | 4503 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | spidataout<6>.REG | spidataout<6> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidataout<6>.D | 4324 | ? | 0 | 0 | spidataout<6> | NULL | NULL | spidataout<6>.XOR | 0 | 7 | ALU_F
+NODE | spidataout<6>.D | 4499 | ? | 0 | 0 | spidataout<6> | NULL | NULL | spidataout<6>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidataout<6>.CLKF | 4327 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<6>.CLKF | 4502 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidataout<6>.CE | 4328 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<6>.CE | 4503 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidataout<6>.Q | 4329 | ? | 0 | 0 | spidataout<6> | NULL | NULL | spidataout<6>.REG | 0 | 8 | SRFF_Q
+NODE | spidataout<6>.Q | 4504 | ? | 0 | 0 | spidataout<6> | NULL | NULL | spidataout<6>.REG | 0 | 8 | SRFF_Q
 
-INPUT_INSTANCE | 0 | 0 | NULL | N2903 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | N3031 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | cpu_d<7> | 4053 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<7> | 0 | 6 | OI_OUT
+NODE | cpu_d<7> | 4219 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<7> | 0 | 6 | OI_OUT
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | N2903 | 4039 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2903 | 0 | 5 | II_IMUX
+NODE | N3031 | 4202 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3031 | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<7> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<7> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<7> | 4020 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
+NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2903 | 4039 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2903 | 0 | 5 | II_IMUX
+NODE | N3031 | 4202 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3031 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | spidataout<7> | 4020 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
+NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | spidataout<7>.SI | spidataout<7> | 0 | 8 | 4
+SIGNAL_INSTANCE | spidataout<7>.SI | spidataout<7> | 0 | 7 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<7> | 4020 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
+NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | N2903 | 4039 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N2903 | 0 | 5 | II_IMUX
+NODE | N3031 | 4202 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3031 | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | spidataout<7>.D1 | 4331 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | spidataout<7>.D1 | 4506 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | spidataout<7>.D2 | 4332 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<7> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N2903
-SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<7> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N2903
+SIGNAL | NODE | spidataout<7>.D2 | 4507 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<7> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3031
+SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<7> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3031
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | spidataout<7>.CLKF | 4333 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<7>.CLKF | 4508 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
-SIGNAL | NODE | spidataout<7>.CE | 4334 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<7>.CE | 4509 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 
 SRFF_INSTANCE | spidataout<7>.REG | spidataout<7> | 0 | 3 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | spidataout<7>.D | 4330 | ? | 0 | 0 | spidataout<7> | NULL | NULL | spidataout<7>.XOR | 0 | 7 | ALU_F
+NODE | spidataout<7>.D | 4505 | ? | 0 | 0 | spidataout<7> | NULL | NULL | spidataout<7>.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | spidataout<7>.CLKF | 4333 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF
+SIGNAL | NODE | spidataout<7>.CLKF | 4508 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | Ncs2_IBUF
 INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
-SIGNAL | NODE | spidataout<7>.CE | 4334 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 10 | 9 | MC_SI_CE
+SIGNAL | NODE | spidataout<7>.CE | 4509 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 10 | 9 | MC_SI_CE
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | spidataout<7>.Q | 4335 | ? | 0 | 0 | spidataout<7> | NULL | NULL | spidataout<7>.REG | 0 | 8 | SRFF_Q
+NODE | spidataout<7>.Q | 4510 | ? | 0 | 0 | spidataout<7> | NULL | NULL | spidataout<7>.REG | 0 | 8 | SRFF_Q
 
-MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<0> | spi6502b_COPY_0_COPY_0 | 2155888640 | 10 | 2
+INPUT_INSTANCE | 0 | 0 | NULL | nio_sel_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | nio_sel | 4243 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | OptxMapped | ng_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 3 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<0> | 3988 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
+NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<0> | 3984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_dout<0> | 4021 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.Q | int_dout<0> | 0 | 0 | MC_Q
-OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_dout<0>$OE | 4022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.BUFOE.OUT | int_dout<0> | 2 | 0 | MC_OE
+NODE | ng_OBUF | 4182 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ng_OBUF.Q | ng_OBUF | 0 | 0 | MC_Q
 
-SIGNAL_INSTANCE | int_dout<0>.SI | int_dout<0> | 0 | 10 | 3
+SIGNAL_INSTANCE | ng_OBUF.SI | ng_OBUF | 0 | 3 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<0> | 3988 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
+NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<0> | 3984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_dout<0>.D1 | 4337 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ng_OBUF.D1 | 4512 | ? | 0 | 4096 | ng_OBUF | NULL | NULL | ng_OBUF.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_dout<0>.D2 | 4338 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<0> | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | ng_OBUF.D2 | 4513 | ? | 0 | 4096 | ng_OBUF | NULL | NULL | ng_OBUF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 3 | IV_TRUE | Ncs2_IBUF | IV_TRUE | nio_stb_IBUF | IV_TRUE | nio_sel_IBUF
+
+SRFF_INSTANCE | ng_OBUF.REG | ng_OBUF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | ng_OBUF.D | 4511 | ? | 0 | 0 | ng_OBUF | NULL | NULL | ng_OBUF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | ng_OBUF.Q | 4514 | ? | 0 | 0 | ng_OBUF | NULL | NULL | ng_OBUF.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<0> | spi6502b_COPY_0_COPY_0 | 2155888640 | 9 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | int_dout<0> | 4183 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.Q | int_dout<0> | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | int_dout<0>$OE | 4184 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.BUFOE.OUT | int_dout<0> | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | int_dout<0>.SI | int_dout<0> | 0 | 9 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_dout<0>.D1 | 4516 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | int_dout<0>.D2 | 4517 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<0> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_dout<0>.TRST | 4340 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<0>.TRST | 4519 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 
 SRFF_INSTANCE | int_dout<0>.REG | int_dout<0> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_dout<0>.D | 4336 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.XOR | 0 | 7 | ALU_F
+NODE | int_dout<0>.D | 4515 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_dout<0>.Q | 4341 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.REG | 0 | 8 | SRFF_Q
+NODE | int_dout<0>.Q | 4520 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_dout<0>.BUFOE | int_dout<0> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_dout<0>.TRST | 4340 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<0>.TRST | 4519 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_dout<0>.BUFOE.OUT | 4339 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.BUFOE | 0 | 10 | BUF_OUT
+NODE | int_dout<0>.BUFOE.OUT | 4518 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.BUFOE | 0 | 10 | BUF_OUT
 
-MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<1> | spi6502b_COPY_0_COPY_0 | 2155888640 | 9 | 2
+MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<1> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<1> | 3989 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpol | 3977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<1> | 3985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
+NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_dout<1> | 4023 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.Q | int_dout<1> | 0 | 0 | MC_Q
+NODE | int_dout<1> | 4185 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.Q | int_dout<1> | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_dout<1>$OE | 4024 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.BUFOE.OUT | int_dout<1> | 2 | 0 | MC_OE
+NODE | int_dout<1>$OE | 4186 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.BUFOE.OUT | int_dout<1> | 2 | 0 | MC_OE
 
-SIGNAL_INSTANCE | int_dout<1>.SI | int_dout<1> | 0 | 9 | 3
+SIGNAL_INSTANCE | int_dout<1>.SI | int_dout<1> | 0 | 8 | 3
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<1> | 3989 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpol | 3977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<1> | 3985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
+NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_dout<1>.D1 | 4343 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_dout<1>.D1 | 4522 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_dout<1>.D2 | 4344 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<1> | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<1>.D2 | 4523 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<1> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_dout<1>.TRST | 4346 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<1>.TRST | 4525 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 
 SRFF_INSTANCE | int_dout<1>.REG | int_dout<1> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_dout<1>.D | 4342 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.XOR | 0 | 7 | ALU_F
+NODE | int_dout<1>.D | 4521 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_dout<1>.Q | 4347 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.REG | 0 | 8 | SRFF_Q
+NODE | int_dout<1>.Q | 4526 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_dout<1>.BUFOE | int_dout<1> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_dout<1>.TRST | 4346 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<1>.TRST | 4525 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_dout<1>.BUFOE.OUT | 4345 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.BUFOE | 0 | 10 | BUF_OUT
+NODE | int_dout<1>.BUFOE.OUT | 4524 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.BUFOE | 0 | 10 | BUF_OUT
 
-MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<2> | spi6502b_COPY_0_COPY_0 | 2155888640 | 9 | 2
+MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<2> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<2> | 3990 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ece | 3978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<2> | 3986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
+NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_dout<2> | 4025 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.Q | int_dout<2> | 0 | 0 | MC_Q
+NODE | int_dout<2> | 4187 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.Q | int_dout<2> | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_dout<2>$OE | 4026 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.BUFOE.OUT | int_dout<2> | 2 | 0 | MC_OE
+NODE | int_dout<2>$OE | 4188 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.BUFOE.OUT | int_dout<2> | 2 | 0 | MC_OE
 
-SIGNAL_INSTANCE | int_dout<2>.SI | int_dout<2> | 0 | 9 | 3
+SIGNAL_INSTANCE | int_dout<2>.SI | int_dout<2> | 0 | 8 | 3
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<2> | 3990 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ece | 3978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | divisor<2> | 3986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
+NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_dout<2>.D1 | 4349 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_dout<2>.D1 | 4528 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_dout<2>.D2 | 4350 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<2> | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<2>.D2 | 4529 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<2> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_dout<2>.TRST | 4352 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<2>.TRST | 4531 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 
 SRFF_INSTANCE | int_dout<2>.REG | int_dout<2> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_dout<2>.D | 4348 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.XOR | 0 | 7 | ALU_F
+NODE | int_dout<2>.D | 4527 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_dout<2>.Q | 4353 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.REG | 0 | 8 | SRFF_Q
+NODE | int_dout<2>.Q | 4532 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_dout<2>.BUFOE | int_dout<2> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_dout<2>.TRST | 4352 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<2>.TRST | 4531 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_dout<2>.BUFOE.OUT | 4351 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.BUFOE | 0 | 10 | BUF_OUT
+NODE | int_dout<2>.BUFOE.OUT | 4530 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.BUFOE | 0 | 10 | BUF_OUT
 
 INPUT_INSTANCE | 0 | 0 | NULL | spi_int_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | spi_int | 4070 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | spi_int | 4246 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | spi_int_IBUF | 4041 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
+NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
 
-MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<4> | spi6502b_COPY_0_COPY_0 | 2155888640 | 10 | 2
+MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<4> | spi6502b_COPY_0_COPY_0 | 2155888640 | 9 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<4> | 3992 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spi_int_IBUF | 4041 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
+NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | frx | 3980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slaveinten | 3982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
+NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | int_dout<4> | 4027 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.Q | int_dout<4> | 0 | 0 | MC_Q
+NODE | int_dout<4> | 4189 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.Q | int_dout<4> | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | int_dout<4>$OE | 4028 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.BUFOE.OUT | int_dout<4> | 2 | 0 | MC_OE
+NODE | int_dout<4>$OE | 4190 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.BUFOE.OUT | int_dout<4> | 2 | 0 | MC_OE
 
-SIGNAL_INSTANCE | int_dout<4>.SI | int_dout<4> | 0 | 10 | 3
+SIGNAL_INSTANCE | int_dout<4>.SI | int_dout<4> | 0 | 9 | 3
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_rnw_IBUF | 3974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
+NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidatain<4> | 3992 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
+NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_1_IBUF | 3997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
+NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cs1_IBUF | 4029 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | Ncs2_IBUF | 4030 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_a_0_IBUF | 4031 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spi_int_IBUF | 4041 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
+NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | frx | 3980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slaveinten | 3982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
+NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | int_dout<4>.D1 | 4355 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | int_dout<4>.D1 | 4534 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | int_dout<4>.D2 | 4356 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<4> | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
-SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | spi_int_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<4>.D2 | 4535 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<4> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | spi_int_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | int_dout<4>.TRST | 4358 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<4>.TRST | 4537 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 
 SRFF_INSTANCE | int_dout<4>.REG | int_dout<4> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | int_dout<4>.D | 4354 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.XOR | 0 | 7 | ALU_F
+NODE | int_dout<4>.D | 4533 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | int_dout<4>.Q | 4359 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.REG | 0 | 8 | SRFF_Q
+NODE | int_dout<4>.Q | 4538 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | int_dout<4>.BUFOE | int_dout<4> | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | int_dout<4>.TRST | 4358 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 4 | 9 | MC_SI_TRST
-SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF
+SIGNAL | NODE | int_dout<4>.TRST | 4537 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | int_dout<4>.BUFOE.OUT | 4357 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.BUFOE | 0 | 10 | BUF_OUT
+NODE | int_dout<4>.BUFOE.OUT | 4536 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.BUFOE | 0 | 10 | BUF_OUT
 
 MACROCELL_INSTANCE | PrldLow+OptxMapped | shifting2 | spi6502b_COPY_0_COPY_0 | 2155873280 | 8 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<6> | 4019 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
+NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
-NODE | shifting2.EXP | 4390 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT
+NODE | shifting2.EXP | 4589 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT
 
 SIGNAL_INSTANCE | shifting2.SI | shifting2 | 0 | 8 | 4
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<6> | 4019 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
+NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | shifting2.D1 | 4361 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | shifting2.D1 | 4540 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | shifting2.D2 | 4362 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | shifting2.D2 | 4541 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 2 | IV_FALSE | shiftdone | IV_TRUE | start_shifting
 OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
-SIGNAL | NODE | shifting2.CLKF | 4363 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shifting2.CLKF | 4542 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
-SIGNAL | NODE | shifting2.EXP | 4388 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.SI | 7 | 9 | MC_SI_EXPORT
-SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<6> | IV_TRUE | shifting2
+SIGNAL | NODE | shifting2.EXP | 4587 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<1> | IV_TRUE | shifting2
 
 SRFF_INSTANCE | shifting2.REG | shifting2 | 0 | 2 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | shifting2.D | 4360 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.XOR | 0 | 7 | ALU_F
+NODE | shifting2.D | 4539 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.XOR | 0 | 7 | ALU_F
 INPUT_NODE_TYPE | 1 | 8 | SRFF_C
-SIGNAL | NODE | shifting2.CLKF | 4363 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 3 | 9 | MC_SI_CLKF
-SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM
+SIGNAL | NODE | shifting2.CLKF | 4542 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | shifting2.Q | 4364 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.REG | 0 | 8 | SRFF_Q
+NODE | shifting2.Q | 4543 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.REG | 0 | 8 | SRFF_Q
 
-INPUT_INSTANCE | 0 | 0 | NULL | extclk_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_INSTANCE | 0 | 0 | NULL | extclk_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 2
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | extclk | 4072 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | extclk | 4245 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | extclk_IBUF | 4043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX
+NODE | extclk_IBUF | 4193 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 3 | 5 | II_FCLK
+NODE | FCLKIO_0 | 4194 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 3 | 5 | II_FCLK
+
+MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | add_dec/XLXN_11 | spi6502b_COPY_0_COPY_0 | 2155873536 | 5 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | FCLKIO_0 | 4194 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 3 | 5 | II_FCLK
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | add_dec/XLXN_11 | 4195 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | add_dec/XLXN_11.Q | add_dec/XLXN_11 | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | add_dec/XLXN_11.SI | add_dec/XLXN_11 | 0 | 4 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | add_dec/XLXN_11.D1 | 4545 | ? | 0 | 4096 | add_dec/XLXN_11 | NULL | NULL | add_dec/XLXN_11.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | add_dec/XLXN_11.D2 | 4546 | ? | 0 | 4096 | add_dec/XLXN_11 | NULL | NULL | add_dec/XLXN_11.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_FALSE | nio_stb_IBUF | IV_TRUE | a9_IBUF | IV_TRUE | a8_IBUF | IV_TRUE | a10_IBUF
+
+SRFF_INSTANCE | add_dec/XLXN_11.REG | add_dec/XLXN_11 | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | add_dec/XLXN_11.D | 4544 | ? | 0 | 0 | add_dec/XLXN_11 | NULL | NULL | add_dec/XLXN_11.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+NODE | FCLKIO_0 | 4194 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 3 | 5 | II_FCLK
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | add_dec/XLXN_11.Q | 4547 | ? | 0 | 0 | add_dec/XLXN_11 | NULL | NULL | add_dec/XLXN_11.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | OptxMapped | b10_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 2 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | b10_OBUF | 4206 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b10_OBUF.Q | b10_OBUF | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | b10_OBUF.SI | b10_OBUF | 0 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | b10_OBUF.D1 | 4549 | ? | 0 | 4096 | b10_OBUF | NULL | NULL | b10_OBUF.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | b10_OBUF.D2 | 4550 | ? | 0 | 4096 | b10_OBUF | NULL | NULL | b10_OBUF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_TRUE | a10_IBUF | IV_TRUE | nio_sel_IBUF
+
+SRFF_INSTANCE | b10_OBUF.REG | b10_OBUF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | b10_OBUF.D | 4548 | ? | 0 | 0 | b10_OBUF | NULL | NULL | b10_OBUF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | b10_OBUF.Q | 4551 | ? | 0 | 0 | b10_OBUF | NULL | NULL | b10_OBUF.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | OptxMapped | b8_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 2 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | b8_OBUF | 4207 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b8_OBUF.Q | b8_OBUF | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | b8_OBUF.SI | b8_OBUF | 0 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | b8_OBUF.D1 | 4553 | ? | 0 | 4096 | b8_OBUF | NULL | NULL | b8_OBUF.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | b8_OBUF.D2 | 4554 | ? | 0 | 4096 | b8_OBUF | NULL | NULL | b8_OBUF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_TRUE | a8_IBUF | IV_TRUE | nio_sel_IBUF
+
+SRFF_INSTANCE | b8_OBUF.REG | b8_OBUF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | b8_OBUF.D | 4552 | ? | 0 | 0 | b8_OBUF | NULL | NULL | b8_OBUF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | b8_OBUF.Q | 4555 | ? | 0 | 0 | b8_OBUF | NULL | NULL | b8_OBUF.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | OptxMapped | b9_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 2 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | b9_OBUF | 4208 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b9_OBUF.Q | b9_OBUF | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | b9_OBUF.SI | b9_OBUF | 0 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | b9_OBUF.D1 | 4557 | ? | 0 | 4096 | b9_OBUF | NULL | NULL | b9_OBUF.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | b9_OBUF.D2 | 4558 | ? | 0 | 4096 | b9_OBUF | NULL | NULL | b9_OBUF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_TRUE | a9_IBUF | IV_TRUE | nio_sel_IBUF
+
+SRFF_INSTANCE | b9_OBUF.REG | b9_OBUF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | b9_OBUF.D | 4556 | ? | 0 | 0 | b9_OBUF | NULL | NULL | b9_OBUF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | b9_OBUF.Q | 4559 | ? | 0 | 0 | b9_OBUF | NULL | NULL | b9_OBUF.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | OptxMapped | led_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 3 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | led_OBUF | 4044 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | led_OBUF.Q | led_OBUF | 0 | 0 | MC_Q
+NODE | led_OBUF | 4209 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | led_OBUF.Q | led_OBUF | 0 | 0 | MC_Q
 
 SIGNAL_INSTANCE | led_OBUF.SI | led_OBUF | 0 | 3 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slavesel | 3976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
+NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | led_OBUF.D1 | 4366 | ? | 0 | 4096 | led_OBUF | NULL | NULL | led_OBUF.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | led_OBUF.D1 | 4561 | ? | 0 | 4096 | led_OBUF | NULL | NULL | led_OBUF.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | led_OBUF.D2 | 4367 | ? | 0 | 4096 | led_OBUF | NULL | NULL | led_OBUF.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | led_OBUF.D2 | 4562 | ? | 0 | 4096 | led_OBUF | NULL | NULL | led_OBUF.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 3 | IV_TRUE | slavesel | IV_FALSE | start_shifting | IV_FALSE | shifting2
 
 SRFF_INSTANCE | led_OBUF.REG | led_OBUF | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | led_OBUF.D | 4365 | ? | 0 | 0 | led_OBUF | NULL | NULL | led_OBUF.XOR | 0 | 7 | ALU_F
+NODE | led_OBUF.D | 4560 | ? | 0 | 0 | led_OBUF | NULL | NULL | led_OBUF.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | led_OBUF.Q | 4368 | ? | 0 | 0 | led_OBUF | NULL | NULL | led_OBUF.REG | 0 | 8 | SRFF_Q
+NODE | led_OBUF.Q | 4563 | ? | 0 | 0 | led_OBUF | NULL | NULL | led_OBUF.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | Inv+OptxMapped | noe_OBUF | spi6502b_COPY_0_COPY_0 | 2155872512 | 3 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | add_dec/XLXN_11 | 4195 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | add_dec/XLXN_11.Q | add_dec/XLXN_11 | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | noe_OBUF | 4210 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | noe_OBUF.Q | noe_OBUF | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | noe_OBUF.SI | noe_OBUF | 0 | 3 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | add_dec/XLXN_11 | 4195 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | add_dec/XLXN_11.Q | add_dec/XLXN_11 | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | noe_OBUF.D1 | 4565 | ? | 0 | 4096 | noe_OBUF | NULL | NULL | noe_OBUF.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | noe_OBUF.D2 | 4566 | ? | 0 | 4096 | noe_OBUF | NULL | NULL | noe_OBUF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_FALSE | nio_stb_IBUF | IV_TRUE | add_dec/XLXN_11
+SPPTERM | 2 | IV_FALSE | nio_sel_IBUF | IV_TRUE | add_dec/XLXN_11
+
+SRFF_INSTANCE | noe_OBUF.REG | noe_OBUF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | noe_OBUF.D | 4564 | ? | 0 | 0 | noe_OBUF | NULL | NULL | noe_OBUF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | noe_OBUF.Q | 4567 | ? | 0 | 0 | noe_OBUF | NULL | NULL | noe_OBUF.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | FbkInv+PinTrst+Merge+OptxMapped | cpu_Nirq_OBUFE | spi6502b_COPY_0_COPY_0 | 2155923456 | 1 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4062 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM
+NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4233 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
-NODE | cpu_Nirq_OBUFE$Q | 4045 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.Q | cpu_Nirq_OBUFE | 0 | 0 | MC_Q
+NODE | cpu_Nirq_OBUFE$Q | 4211 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.Q | cpu_Nirq_OBUFE | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
-NODE | cpu_Nirq_OBUFE$OE | 4046 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.BUFOE.OUT | cpu_Nirq_OBUFE | 2 | 0 | MC_OE
+NODE | cpu_Nirq_OBUFE$OE | 4212 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.BUFOE.OUT | cpu_Nirq_OBUFE | 2 | 0 | MC_OE
 
 SIGNAL_INSTANCE | cpu_Nirq_OBUFE.SI | cpu_Nirq_OBUFE | 0 | 1 | 3
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4062 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM
+NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4233 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | cpu_Nirq_OBUFE.D1 | 4370 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | cpu_Nirq_OBUFE.D1 | 4569 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | cpu_Nirq_OBUFE.D2 | 4371 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | cpu_Nirq_OBUFE.D2 | 4570 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
-SIGNAL | NODE | cpu_Nirq_OBUFE.TRST | 4373 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | cpu_Nirq_OBUFE.TRST | 4572 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 4 | 9 | MC_SI_TRST
 SPPTERM | 1 | IV_TRUE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM
 
 SRFF_INSTANCE | cpu_Nirq_OBUFE.REG | cpu_Nirq_OBUFE | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | cpu_Nirq_OBUFE.D | 4369 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.XOR | 0 | 7 | ALU_F
+NODE | cpu_Nirq_OBUFE.D | 4568 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | cpu_Nirq_OBUFE.Q | 4374 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.REG | 0 | 8 | SRFF_Q
+NODE | cpu_Nirq_OBUFE.Q | 4573 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.REG | 0 | 8 | SRFF_Q
 
 BUF_INSTANCE | cpu_Nirq_OBUFE.BUFOE | cpu_Nirq_OBUFE | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
-SIGNAL | NODE | cpu_Nirq_OBUFE.TRST | 4373 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | cpu_Nirq_OBUFE.TRST | 4572 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 4 | 9 | MC_SI_TRST
 SPPTERM | 1 | IV_TRUE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM
 OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
-NODE | cpu_Nirq_OBUFE.BUFOE.OUT | 4372 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.BUFOE | 0 | 10 | BUF_OUT
+NODE | cpu_Nirq_OBUFE.BUFOE.OUT | 4571 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.BUFOE | 0 | 10 | BUF_OUT
 
 OUTPUT_INSTANCE | 0 | spi_mosi | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_mosi | 3972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.Q | int_mosi | 0 | 0 | MC_Q
+NODE | int_mosi | 4127 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.Q | int_mosi | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_mosi$OE | 3973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.BUFOE.OUT | int_mosi | 2 | 0 | MC_OE
+NODE | int_mosi$OE | 4128 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.BUFOE.OUT | int_mosi | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | spi_mosi | 4047 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_mosi | 0 | 6 | OI_OUT
+NODE | spi_mosi | 4213 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_mosi | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | spi_Nsel | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | slavesel$Q | 3975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 0 | 0 | MC_Q
+NODE | slavesel$Q | 4131 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | spi_Nsel | 4048 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_Nsel | 0 | 6 | OI_OUT
+NODE | spi_Nsel | 4214 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_Nsel | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | spi_sclk | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_sclk | 3996 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_sclk.Q | int_sclk | 0 | 0 | MC_Q
+NODE | int_sclk | 4156 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_sclk.Q | int_sclk | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | spi_sclk | 4049 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_sclk | 0 | 6 | OI_OUT
+NODE | spi_sclk | 4215 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_sclk | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_d<3> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_dout<3> | 3998 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.Q | int_dout<3> | 0 | 0 | MC_Q
+NODE | int_dout<3> | 4158 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.Q | int_dout<3> | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_dout<3>$OE | 3999 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.BUFOE.OUT | int_dout<3> | 2 | 0 | MC_OE
+NODE | int_dout<3>$OE | 4159 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.BUFOE.OUT | int_dout<3> | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_d<3> | 4050 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<3> | 0 | 6 | OI_OUT
+NODE | cpu_d<3> | 4216 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<3> | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_d<5> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_dout<5> | 4000 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.Q | int_dout<5> | 0 | 0 | MC_Q
+NODE | int_dout<5> | 4160 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.Q | int_dout<5> | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_dout<5>$OE | 4001 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.BUFOE.OUT | int_dout<5> | 2 | 0 | MC_OE
+NODE | int_dout<5>$OE | 4161 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.BUFOE.OUT | int_dout<5> | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_d<5> | 4051 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<5> | 0 | 6 | OI_OUT
+NODE | cpu_d<5> | 4217 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<5> | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_d<6> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_dout<6> | 4002 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.Q | int_dout<6> | 0 | 0 | MC_Q
+NODE | int_dout<6> | 4162 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.Q | int_dout<6> | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_dout<6>$OE | 4003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.BUFOE.OUT | int_dout<6> | 2 | 0 | MC_OE
+NODE | int_dout<6>$OE | 4163 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.BUFOE.OUT | int_dout<6> | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_d<6> | 4052 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<6> | 0 | 6 | OI_OUT
+NODE | cpu_d<6> | 4218 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<6> | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_d<7> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_dout<7> | 4004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.Q | int_dout<7> | 0 | 0 | MC_Q
+NODE | int_dout<7> | 4164 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.Q | int_dout<7> | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_dout<7>$OE | 4005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.BUFOE.OUT | int_dout<7> | 2 | 0 | MC_OE
+NODE | int_dout<7>$OE | 4165 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.BUFOE.OUT | int_dout<7> | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_d<7> | 4053 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<7> | 0 | 6 | OI_OUT
+NODE | cpu_d<7> | 4219 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<7> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | ng | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | ng_OBUF | 4182 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ng_OBUF.Q | ng_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | ng | 4220 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | ng | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_d<0> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_dout<0> | 4021 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.Q | int_dout<0> | 0 | 0 | MC_Q
+NODE | int_dout<0> | 4183 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.Q | int_dout<0> | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_dout<0>$OE | 4022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.BUFOE.OUT | int_dout<0> | 2 | 0 | MC_OE
+NODE | int_dout<0>$OE | 4184 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.BUFOE.OUT | int_dout<0> | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_d<0> | 4054 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<0> | 0 | 6 | OI_OUT
+NODE | cpu_d<0> | 4221 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<0> | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_d<1> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_dout<1> | 4023 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.Q | int_dout<1> | 0 | 0 | MC_Q
+NODE | int_dout<1> | 4185 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.Q | int_dout<1> | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_dout<1>$OE | 4024 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.BUFOE.OUT | int_dout<1> | 2 | 0 | MC_OE
+NODE | int_dout<1>$OE | 4186 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.BUFOE.OUT | int_dout<1> | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_d<1> | 4055 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<1> | 0 | 6 | OI_OUT
+NODE | cpu_d<1> | 4222 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<1> | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_d<2> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_dout<2> | 4025 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.Q | int_dout<2> | 0 | 0 | MC_Q
+NODE | int_dout<2> | 4187 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.Q | int_dout<2> | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_dout<2>$OE | 4026 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.BUFOE.OUT | int_dout<2> | 2 | 0 | MC_OE
+NODE | int_dout<2>$OE | 4188 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.BUFOE.OUT | int_dout<2> | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_d<2> | 4056 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<2> | 0 | 6 | OI_OUT
+NODE | cpu_d<2> | 4223 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<2> | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_d<4> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | int_dout<4> | 4027 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.Q | int_dout<4> | 0 | 0 | MC_Q
+NODE | int_dout<4> | 4189 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.Q | int_dout<4> | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | int_dout<4>$OE | 4028 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.BUFOE.OUT | int_dout<4> | 2 | 0 | MC_OE
+NODE | int_dout<4>$OE | 4190 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.BUFOE.OUT | int_dout<4> | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_d<4> | 4057 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<4> | 0 | 6 | OI_OUT
+NODE | cpu_d<4> | 4224 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<4> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | b10 | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | b10_OBUF | 4206 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b10_OBUF.Q | b10_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | b10 | 4225 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | b10 | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | b8 | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | b8_OBUF | 4207 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b8_OBUF.Q | b8_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | b8 | 4226 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | b8 | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | b9 | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | b9_OBUF | 4208 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b9_OBUF.Q | b9_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | b9 | 4227 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | b9 | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | led | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | led_OBUF | 4044 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | led_OBUF.Q | led_OBUF | 0 | 0 | MC_Q
+NODE | led_OBUF | 4209 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | led_OBUF.Q | led_OBUF | 0 | 0 | MC_Q
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | led | 4058 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | led | 0 | 6 | OI_OUT
+NODE | led | 4228 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | led | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | noe | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | noe_OBUF | 4210 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | noe_OBUF.Q | noe_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | noe | 4229 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | noe | 0 | 6 | OI_OUT
 
 OUTPUT_INSTANCE | 0 | cpu_Nirq | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1
 INPUT_NODE_TYPE | 0 | 6 | OI_IN
-NODE | cpu_Nirq_OBUFE$Q | 4045 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.Q | cpu_Nirq_OBUFE | 0 | 0 | MC_Q
+NODE | cpu_Nirq_OBUFE$Q | 4211 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.Q | cpu_Nirq_OBUFE | 0 | 0 | MC_Q
 INPUT_NODE_TYPE | 2 | 6 | OI_OE
-NODE | cpu_Nirq_OBUFE$OE | 4046 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.BUFOE.OUT | cpu_Nirq_OBUFE | 2 | 0 | MC_OE
+NODE | cpu_Nirq_OBUFE$OE | 4212 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.BUFOE.OUT | cpu_Nirq_OBUFE | 2 | 0 | MC_OE
 OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
-NODE | cpu_Nirq | 4059 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nirq | 0 | 6 | OI_OUT
+NODE | cpu_Nirq | 4230 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nirq | 0 | 6 | OI_OUT
 
-MACROCELL_INSTANCE | SoftPfbk | $OpTx$INV$22__$INT | spi6502b_COPY_0_COPY_0 | 2181038080 | 5 | 1
+MACROCELL_INSTANCE | SoftPfbk | $OpTx$INV$24__$INT | spi6502b_COPY_0_COPY_0 | 2181038080 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ece | 3978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
+NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | extclk_IBUF | 4043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX
+NODE | extclk_IBUF | 4193 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | $OpTx$INV$22__$INT.UIM | 4060 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM
+NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM
 
-SIGNAL_INSTANCE | $OpTx$INV$22__$INT.SI | $OpTx$INV$22__$INT | 0 | 5 | 2
+SIGNAL_INSTANCE | $OpTx$INV$24__$INT.SI | $OpTx$INV$24__$INT | 0 | 5 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ece | 3978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
+NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nphi2_IBUF | 4042 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | extclk_IBUF | 4043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX
+NODE | extclk_IBUF | 4193 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | start_shifting | 4011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
+NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | $OpTx$INV$22__$INT.D1 | 4376 | ? | 0 | 4096 | $OpTx$INV$22__$INT | NULL | NULL | $OpTx$INV$22__$INT.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | $OpTx$INV$24__$INT.D1 | 4575 | ? | 0 | 4096 | $OpTx$INV$24__$INT | NULL | NULL | $OpTx$INV$24__$INT.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | $OpTx$INV$22__$INT.D2 | 4377 | ? | 0 | 4096 | $OpTx$INV$22__$INT | NULL | NULL | $OpTx$INV$22__$INT.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | $OpTx$INV$24__$INT.D2 | 4576 | ? | 0 | 4096 | $OpTx$INV$24__$INT | NULL | NULL | $OpTx$INV$24__$INT.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 2 | IV_TRUE | ece | IV_FALSE | extclk_IBUF
 SPPTERM | 2 | IV_FALSE | ece | IV_FALSE | cpu_Nphi2_IBUF
 SPPTERM | 2 | IV_FALSE | start_shifting | IV_FALSE | shifting2
 
-SRFF_INSTANCE | $OpTx$INV$22__$INT.REG | $OpTx$INV$22__$INT | 0 | 1 | 1
+SRFF_INSTANCE | $OpTx$INV$24__$INT.REG | $OpTx$INV$24__$INT | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | $OpTx$INV$22__$INT.D | 4375 | ? | 0 | 0 | $OpTx$INV$22__$INT | NULL | NULL | $OpTx$INV$22__$INT.XOR | 0 | 7 | ALU_F
+NODE | $OpTx$INV$24__$INT.D | 4574 | ? | 0 | 0 | $OpTx$INV$24__$INT | NULL | NULL | $OpTx$INV$24__$INT.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | $OpTx$INV$22__$INT.Q | 4378 | ? | 0 | 0 | $OpTx$INV$22__$INT | NULL | NULL | $OpTx$INV$22__$INT.REG | 0 | 8 | SRFF_Q
+NODE | $OpTx$INV$24__$INT.Q | 4577 | ? | 0 | 0 | $OpTx$INV$24__$INT | NULL | NULL | $OpTx$INV$24__$INT.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | SoftPfbk | start_shifting/start_shifting_RSTF__$INT | spi6502b_COPY_0_COPY_0 | 2181038080 | 2 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4061 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM
+NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4232 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | start_shifting/start_shifting_RSTF__$INT.SI | start_shifting/start_shifting_RSTF__$INT | 0 | 2 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
+NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.D1 | 4380 | ? | 0 | 4096 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.D1 | 4579 | ? | 0 | 4096 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.D2 | 4381 | ? | 0 | 4096 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.D2 | 4580 | ? | 0 | 4096 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | shiftdone
 
 SRFF_INSTANCE | start_shifting/start_shifting_RSTF__$INT.REG | start_shifting/start_shifting_RSTF__$INT | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | start_shifting/start_shifting_RSTF__$INT.D | 4379 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.XOR | 0 | 7 | ALU_F
+NODE | start_shifting/start_shifting_RSTF__$INT.D | 4578 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | start_shifting/start_shifting_RSTF__$INT.Q | 4382 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.REG | 0 | 8 | SRFF_Q
+NODE | start_shifting/start_shifting_RSTF__$INT.Q | 4581 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | SoftPfbk | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | spi6502b_COPY_0_COPY_0 | 2181038080 | 4 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ier | 3981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
+NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tc | 4012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
+NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slaveinten | 3982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
+NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spi_int_IBUF | 4041 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
+NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
-NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4062 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM
+NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4233 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM
 
 SIGNAL_INSTANCE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 0 | 4 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | ier | 3981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
+NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | tc | 4012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
+NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | slaveinten | 3982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
+NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spi_int_IBUF | 4041 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
+NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
-SIGNAL | NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D1 | 4384 | ? | 0 | 4096 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D1 | 4583 | ? | 0 | 4096 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
-SIGNAL | NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D2 | 4385 | ? | 0 | 4096 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D2 | 4584 | ? | 0 | 4096 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | 2 | 9 | MC_SI_D2
 SPPTERM | 2 | IV_TRUE | ier | IV_TRUE | tc
 SPPTERM | 2 | IV_TRUE | slaveinten | IV_FALSE | spi_int_IBUF
 
 SRFF_INSTANCE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.REG | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 0 | 1 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
-NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D | 4383 | ? | 0 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.XOR | 0 | 7 | ALU_F
+NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D | 4582 | ? | 0 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.XOR | 0 | 7 | ALU_F
 OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
-NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | 4386 | ? | 0 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.REG | 0 | 8 | SRFF_Q
+NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | 4585 | ? | 0 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.REG | 0 | 8 | SRFF_Q
 
 MACROCELL_INSTANCE | NULL | EXP6_ | spi6502b_COPY_0_COPY_0 | 2147483648 | 10 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<0> | 4013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
+NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<2> | 4015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
+NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<3> | 4016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
+NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<4> | 4017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
+NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<7> | 4020 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
+NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
-NODE | EXP6_.EXP | 4389 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT
+NODE | EXP6_.EXP | 4588 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT
 
 SIGNAL_INSTANCE | EXP6_.SI | EXP6_ | 0 | 10 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<3> | 4006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
+NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<2> | 4007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
+NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<1> | 4009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
+NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
+NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<0> | 4013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM
+NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
+NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<2> | 4015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM
+NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<3> | 4016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM
+NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<4> | 4017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM
+NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | spidataout<7> | 4020 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
+NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM
 OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
-SIGNAL | NODE | EXP6_.EXP | 4387 | ? | 0 | 0 | EXP6_ | NULL | NULL | EXP6_.SI | 7 | 9 | MC_SI_EXPORT
-SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<0> | IV_TRUE | shifting2
+SIGNAL | NODE | EXP6_.EXP | 4586 | ? | 0 | 0 | EXP6_ | NULL | NULL | EXP6_.SI | 7 | 9 | MC_SI_EXPORT
 SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<2> | IV_TRUE | shifting2
 SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<3> | IV_TRUE | shifting2
-SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<4> | IV_TRUE | shifting2
+SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<5> | IV_TRUE | shifting2
+SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<6> | IV_TRUE | shifting2
 SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<7> | IV_TRUE | shifting2
 
-MACROCELL_INSTANCE | NULL | EXP7_ | spi6502b_COPY_0_COPY_0 | 2147483648 | 5 | 1
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
-OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
-NODE | EXP7_.EXP | 4392 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP7_.EXP | EXP7_ | 4 | 0 | MC_EXPORT
-
-SIGNAL_INSTANCE | EXP7_.SI | EXP7_ | 0 | 5 | 1
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpu_Nres_IBUF | 3971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | cpha | 3979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftcnt<0> | 4008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shiftdone | 4010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM
-INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | shifting2 | 4032 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM
-OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
-SIGNAL | NODE | EXP7_.EXP | 4391 | ? | 0 | 0 | EXP7_ | NULL | NULL | EXP7_.SI | 7 | 9 | MC_SI_EXPORT
-SPPTERM | 5 | IV_TRUE | cpu_Nres_IBUF | IV_TRUE | cpha | IV_FALSE | shiftcnt<0> | IV_FALSE | shiftdone | IV_TRUE | shifting2
-
 FB_INSTANCE | FOOBAR1_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 1 | spidataout<3> | 1 | NULL | 0 | NULL | 0
 FBPIN | 2 | spidataout<2> | 1 | NULL | 0 | NULL | 0 | 1 | 49152
 FBPIN | 3 | spidataout<1> | 1 | NULL | 0 | NULL | 0
 FBPIN | 4 | spidataout<0> | 1 | NULL | 0 | NULL | 0
-FBPIN | 5 | int_dout<0> | 1 | N2889 | 1 | cpu_d<0> | 1 | 2 | 49152
-FBPIN | 6 | int_dout<1> | 1 | N2891 | 1 | cpu_d<1> | 1 | 3 | 49152
+FBPIN | 5 | int_dout<0> | 1 | N3017 | 1 | cpu_d<0> | 1 | 2 | 49152
+FBPIN | 6 | int_dout<1> | 1 | N3019 | 1 | cpu_d<1> | 1 | 3 | 49152
 FBPIN | 7 | tmo | 1 | NULL | 0 | NULL | 0
-FBPIN | 8 | int_dout<2> | 1 | N2893 | 1 | cpu_d<2> | 1 | 4 | 49152
+FBPIN | 8 | int_dout<2> | 1 | N3021 | 1 | cpu_d<2> | 1 | 4 | 49152
 FBPIN | 9 | slaveinten | 1 | cpu_Nphi2_IBUF | 0 | NULL | 0 | 5 | 57344
 FBPIN | 10 | frx | 1 | NULL | 0 | NULL | 0
 FBPIN | 11 | ece | 1 | extclk_IBUF | 0 | NULL | 0 | 6 | 57344
 FBPIN | 12 | divisor<2> | 1 | NULL | 0 | NULL | 0
 FBPIN | 13 | divisor<1> | 1 | NULL | 0 | NULL | 0
 FBPIN | 14 | divisor<0> | 1 | cpu_rnw_IBUF | 0 | NULL | 0 | 7 | 57344
-FBPIN | 15 | int_dout<3> | 1 | N2895 | 1 | cpu_d<3> | 1 | 8 | 49152
+FBPIN | 15 | int_dout<3> | 1 | N3023 | 1 | cpu_d<3> | 1 | 8 | 49152
 FBPIN | 16 | cpol | 1 | NULL | 0 | NULL | 0
-FBPIN | 17 | int_dout<4> | 1 | N2897 | 1 | cpu_d<4> | 1 | 9 | 49152
+FBPIN | 17 | int_dout<4> | 1 | N3025 | 1 | cpu_d<4> | 1 | 9 | 49152
 FBPIN | 18 | cpha | 1 | NULL | 0 | NULL | 0
 
 FB_INSTANCE | FOOBAR2_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0
 FBPIN | 1 | EXP6_ | 1 | NULL | 0 | NULL | 0
 FBPIN | 2 | int_mosi | 1 | NULL | 0 | spi_mosi | 1 | 35 | 49152
 FBPIN | 3 | shifting2 | 1 | NULL | 0 | NULL | 0
-FBPIN | 4 | shiftdone | 1 | NULL | 0 | NULL | 0
-FBPIN | 5 | shiftcnt<0> | 1 | NULL | 0 | NULL | 0 | 36 | 49152
-FBPIN | 6 | $OpTx$INV$22__$INT | 1 | NULL | 0 | NULL | 0 | 37 | 49152
+FBPIN | 4 | tc | 1 | NULL | 0 | NULL | 0
+FBPIN | 5 | shiftcnt<0> | 1 | a8_IBUF | 0 | NULL | 0 | 36 | 49152
+FBPIN | 6 | $OpTx$INV$24__$INT | 1 | a9_IBUF | 0 | NULL | 0 | 37 | 49152
 FBPIN | 7 | spidatain<7> | 1 | NULL | 0 | NULL | 0
-FBPIN | 8 | spidatain<6> | 1 | NULL | 0 | NULL | 0 | 38 | 49152
-FBPIN | 9 | spidatain<5> | 1 | NULL | 0 | NULL | 0 | 39 | 51200
-FBPIN | 10 | spidatain<4> | 1 | NULL | 0 | NULL | 0
-FBPIN | 11 | spidatain<3> | 1 | NULL | 0 | NULL | 0 | 40 | 53248
-FBPIN | 12 | spidatain<2> | 1 | NULL | 0 | NULL | 0
-FBPIN | 13 | spidatain<1> | 1 | NULL | 0 | NULL | 0
-FBPIN | 14 | spidatain<0> | 1 | spi_int_IBUF | 0 | NULL | 0 | 42 | 53248
-FBPIN | 15 | shiftcnt<3> | 1 | NULL | 0 | NULL | 0 | 43 | 49152
-FBPIN | 16 | shiftcnt<2> | 1 | NULL | 0 | NULL | 0
-FBPIN | 17 | shiftcnt<1> | 1 | spi_miso_IBUF | 0 | NULL | 0 | 44 | 49152
+FBPIN | 8 | spidatain<6> | 1 | a10_IBUF | 0 | NULL | 0 | 38 | 49152
+FBPIN | 9 | cpu_Nirq_OBUFE | 1 | NULL | 0 | cpu_Nirq | 1 | 39 | 51200
+FBPIN | 10 | spidatain<5> | 1 | NULL | 0 | NULL | 0
+FBPIN | 11 | spidatain<4> | 1 | nio_sel_IBUF | 0 | NULL | 0 | 40 | 53248
+FBPIN | 12 | spidatain<3> | 1 | NULL | 0 | NULL | 0
+FBPIN | 13 | spidatain<2> | 1 | NULL | 0 | NULL | 0
+FBPIN | 14 | NULL | 0 | spi_int_IBUF | 0 | NULL | 0 | 42 | 53248
+FBPIN | 15 | NULL | 0 | nio_stb_IBUF | 0 | NULL | 0 | 43 | 49152
+FBPIN | 17 | NULL | 0 | spi_miso_IBUF | 0 | NULL | 0 | 44 | 49152
 FBPIN | 18 | start_shifting/start_shifting_RSTF__$INT | 1 | NULL | 0 | NULL | 0
 
 FB_INSTANCE | FOOBAR3_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0
-FBPIN | 2 | int_dout<5> | 1 | N2899 | 1 | cpu_d<5> | 1 | 11 | 49152
-FBPIN | 5 | int_dout<6> | 1 | N2901 | 1 | cpu_d<6> | 1 | 12 | 49152
-FBPIN | 8 | int_dout<7> | 1 | N2903 | 1 | cpu_d<7> | 1 | 13 | 49152
-FBPIN | 9 | cpu_Nirq_OBUFE | 1 | NULL | 0 | cpu_Nirq | 1 | 14 | 49152
+FBPIN | 2 | int_dout<5> | 1 | N3027 | 1 | cpu_d<5> | 1 | 11 | 49152
+FBPIN | 5 | int_dout<6> | 1 | N3029 | 1 | cpu_d<6> | 1 | 12 | 49152
+FBPIN | 8 | int_dout<7> | 1 | N3031 | 1 | cpu_d<7> | 1 | 13 | 49152
+FBPIN | 9 | noe_OBUF | 1 | NULL | 0 | noe | 1 | 14 | 49152
 FBPIN | 11 | NULL | 0 | Ncs2_IBUF | 0 | NULL | 0 | 18 | 49152
 FBPIN | 14 | NULL | 0 | cpu_Nres_IBUF | 0 | NULL | 0 | 19 | 49152
-FBPIN | 15 | NULL | 0 | cs1_IBUF | 0 | NULL | 0 | 20 | 49152
+FBPIN | 15 | ng_OBUF | 1 | NULL | 0 | ng | 1 | 20 | 49152
 FBPIN | 16 | NULL | 0 | cpu_a_1_IBUF | 0 | NULL | 0 | 24 | 49152
-FBPIN | 17 | NULL | 0 | cpu_a_0_IBUF | 0 | NULL | 0 | 22 | 49152
+FBPIN | 17 | add_dec/XLXN_11 | 1 | cpu_a_0_IBUF | 0 | NULL | 0 | 22 | 49152
+FBPIN | 18 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | NULL | 0 | NULL | 0
 
 FB_INSTANCE | FOOBAR4_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0
-FBPIN | 1 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | NULL | 0 | NULL | 0
-FBPIN | 2 | tc | 1 | NULL | 0 | NULL | 0 | 25 | 49152
+FBPIN | 1 | shiftdone | 1 | NULL | 0 | NULL | 0
+FBPIN | 2 | b8_OBUF | 1 | NULL | 0 | b8 | 1 | 25 | 49152
 FBPIN | 3 | start_shifting | 1 | NULL | 0 | NULL | 0
 FBPIN | 4 | spidataout<7> | 1 | NULL | 0 | NULL | 0
-FBPIN | 5 | spidataout<6> | 1 | NULL | 0 | NULL | 0 | 26 | 49152
-FBPIN | 6 | spidataout<5> | 1 | NULL | 0 | NULL | 0
-FBPIN | 7 | spidataout<4> | 1 | NULL | 0 | NULL | 0
-FBPIN | 8 | spidataout<3> | 1 | NULL | 0 | NULL | 0 | 27 | 49152
-FBPIN | 9 | ier | 1 | NULL | 0 | NULL | 0
+FBPIN | 5 | b9_OBUF | 1 | NULL | 0 | b9 | 1 | 26 | 49152
+FBPIN | 6 | spidataout<6> | 1 | NULL | 0 | NULL | 0
+FBPIN | 7 | spidataout<5> | 1 | NULL | 0 | NULL | 0
+FBPIN | 8 | b10_OBUF | 1 | NULL | 0 | b10 | 1 | 27 | 49152
+FBPIN | 9 | spidataout<4> | 1 | NULL | 0 | NULL | 0
+FBPIN | 10 | spidatain<1> | 1 | NULL | 0 | NULL | 0
 FBPIN | 11 | slavesel | 1 | NULL | 0 | spi_Nsel | 1 | 28 | 49152
+FBPIN | 12 | spidatain<0> | 1 | NULL | 0 | NULL | 0
+FBPIN | 13 | shiftcnt<3> | 1 | NULL | 0 | NULL | 0
 FBPIN | 14 | led_OBUF | 1 | NULL | 0 | led | 1 | 29 | 49152
-FBPIN | 16 | EXP7_ | 1 | NULL | 0 | NULL | 0
+FBPIN | 15 | shiftcnt<2> | 1 | NULL | 0 | NULL | 0 | 33 | 49152
+FBPIN | 16 | shiftcnt<1> | 1 | NULL | 0 | NULL | 0
 FBPIN | 17 | int_sclk | 1 | NULL | 0 | spi_sclk | 1 | 34 | 49152
+FBPIN | 18 | ier | 1 | NULL | 0 | NULL | 0
 
 FB_INSTANCE | INPUTPINS_FOOBAR5_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0
 
 BUSINFO | CPU_A<1:0> | 2 | 0 | 0 | cpu_a<0> | 1 | cpu_a<1> | 0
 BUSINFO | CPU_D<7:0> | 8 | 0 | 2 | cpu_d<0> | 7 | cpu_d<1> | 6 | cpu_d<2> | 5 | cpu_d<3> | 4 | cpu_d<4> | 3 | cpu_d<5> | 2 | cpu_d<6> | 1 | cpu_d<7> | 0
 
-FB_ORDER_OF_INPUTS | FOOBAR1_ | 0 | cpu_rnw | 7 | 1 | spidataout<2> | NULL | 3 | spidataout<0> | NULL | 5 | Ncs2 | 18 | 6 | tmo | NULL
-FB_ORDER_OF_INPUTS | FOOBAR1_ | 8 | spi_int | 42 | 9 | spidatain<4> | NULL | 10 | slavesel | NULL | 11 | spidatain<2> | NULL | 13 | cpu_a<0> | 22
-FB_ORDER_OF_INPUTS | FOOBAR1_ | 15 | cpol | NULL | 17 | cpu_Nres | 19 | 19 | cpu_d<2> | 4 | 20 | cpu_d<0> | 2 | 21 | spidatain<3> | NULL
-FB_ORDER_OF_INPUTS | FOOBAR1_ | 24 | cs1 | 20 | 26 | divisor<1> | NULL | 28 | slaveinten | NULL | 29 | spidatain<0> | NULL | 30 | divisor<0> | NULL
-FB_ORDER_OF_INPUTS | FOOBAR1_ | 33 | cpu_d<1> | 3 | 36 | spidatain<1> | NULL | 37 | spidataout<1> | NULL | 38 | divisor<2> | NULL | 39 | cpu_a<1> | 24
-FB_ORDER_OF_INPUTS | FOOBAR1_ | 43 | cpha | NULL | 44 | cpu_d<4> | 9 | 45 | frx | NULL | 50 | ece | NULL | 51 | cpu_Nphi2 | 5
-FB_ORDER_OF_INPUTS | FOOBAR1_ | 53 | cpu_d<3> | 8
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 0 | spidataout<3> | NULL | 1 | spidataout<2> | NULL | 2 | spidataout<1> | NULL | 3 | spidataout<0> | NULL | 4 | cpu_d<3> | 8
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 6 | tmo | NULL | 8 | slaveinten | NULL | 9 | spidatain<1> | NULL | 10 | ece | NULL | 11 | divisor<2> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 12 | divisor<1> | NULL | 13 | divisor<0> | NULL | 17 | cpu_Nres | 19 | 21 | spidatain<4> | NULL | 22 | spi_int | 42
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 29 | cpu_d<0> | 2 | 31 | cpu_rnw | 7 | 32 | cpu_d<4> | 9 | 33 | cpu_d<1> | 3 | 36 | cpu_a<0> | 22
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 39 | cpu_a<1> | 24 | 40 | cpu_d<2> | 4 | 41 | spidatain<2> | NULL | 42 | slavesel | NULL | 43 | cpha | NULL
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 44 | spidatain<0> | NULL | 45 | frx | NULL | 47 | Ncs2 | 18 | 50 | spidatain<3> | NULL | 52 | cpol | NULL
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 53 | cpu_Nphi2 | 5
 
-FB_IMUX_INDEX | FOOBAR1_ | 126 | 1 | -1 | 3 | -1 | 131 | 6 | -1 | 98 | 27 | 64 | 29 | -1 | 121 | -1 | 15 | -1 | 125 | -1 | 114 | 108 | 28 | -1 | -1 | 123 | -1 | 12 | -1 | 8 | 31 | 13 | -1 | -1 | 110 | -1 | -1 | 30 | 2 | 11 | 111 | -1 | -1 | -1 | 17 | 132 | 9 | -1 | -1 | -1 | -1 | 10 | 120 | -1 | 130
+FB_IMUX_INDEX | FOOBAR1_ | 0 | 1 | 2 | 3 | 130 | -1 | 6 | -1 | 8 | 63 | 10 | 11 | 12 | 13 | -1 | -1 | -1 | 125 | -1 | -1 | -1 | 28 | 98 | -1 | -1 | -1 | -1 | -1 | -1 | 108 | -1 | 126 | 132 | 110 | -1 | -1 | 121 | -1 | -1 | 111 | 114 | 30 | 64 | 17 | 65 | 9 | -1 | 131 | -1 | -1 | 29 | -1 | 15 | 120
 
 
-FB_ORDER_OF_INPUTS | FOOBAR2_ | 1 | spidataout<2> | NULL | 2 | start_shifting | NULL | 3 | spidataout<7> | NULL | 4 | spidataout<6> | NULL | 5 | spidataout<5> | NULL
-FB_ORDER_OF_INPUTS | FOOBAR2_ | 6 | tmo | NULL | 7 | spidataout<3> | NULL | 9 | spidatain<4> | NULL | 10 | slavesel | NULL | 11 | spidatain<2> | NULL
-FB_ORDER_OF_INPUTS | FOOBAR2_ | 13 | spidatain<0> | NULL | 14 | shiftcnt<3> | NULL | 16 | shiftcnt<1> | NULL | 17 | cpu_Nres | 19 | 18 | shiftdone | NULL
-FB_ORDER_OF_INPUTS | FOOBAR2_ | 19 | spi_miso | 44 | 20 | shiftcnt<0> | NULL | 21 | spidatain<3> | NULL | 24 | spidatain<6> | NULL | 25 | shifting2 | NULL
-FB_ORDER_OF_INPUTS | FOOBAR2_ | 26 | $OpTx$INV$22__$INT.UIM | NULL | 29 | spidataout<1> | NULL | 32 | spidatain<5> | NULL | 36 | spidatain<1> | NULL | 39 | spidataout<4> | NULL
-FB_ORDER_OF_INPUTS | FOOBAR2_ | 44 | shiftcnt<2> | NULL | 46 | spidataout<0> | NULL | 48 | extclk | 6 | 50 | ece | NULL | 51 | cpu_Nphi2 | 5
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 0 | shiftdone | NULL | 2 | start_shifting | NULL | 3 | spidataout<7> | NULL | 5 | spidataout<6> | NULL | 7 | spidatain<6> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 9 | spidatain<5> | NULL | 10 | spidatain<4> | NULL | 11 | spidatain<3> | NULL | 12 | spidatain<2> | NULL | 14 | extclk | 6
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 15 | shiftcnt<1> | NULL | 17 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | NULL | 18 | cpu_a<1> | 24 | 27 | shiftcnt<2> | NULL | 28 | cpu_Nres | 19
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 31 | $OpTx$INV$24__$INT.UIM | NULL | 33 | spidataout<3> | NULL | 36 | spidataout<4> | NULL | 37 | spidataout<1> | NULL | 38 | spidatain<1> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 39 | tmo | NULL | 40 | shiftcnt<0> | NULL | 43 | cpu_a<0> | 22 | 44 | spidataout<2> | NULL | 46 | spidataout<0> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 47 | Ncs2 | 18 | 48 | shifting2 | NULL | 49 | spidataout<5> | NULL | 50 | ece | NULL | 51 | shiftcnt<3> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 53 | cpu_Nphi2 | 5
 
-FB_IMUX_INDEX | FOOBAR2_ | -1 | 1 | 56 | 57 | 58 | 59 | 6 | 61 | -1 | 27 | 64 | 29 | -1 | 31 | 32 | -1 | 34 | 125 | 21 | 104 | 22 | 28 | -1 | -1 | 25 | 20 | 23 | -1 | -1 | 2 | -1 | -1 | 26 | -1 | -1 | -1 | 30 | -1 | -1 | 60 | -1 | -1 | -1 | -1 | 33 | -1 | 3 | -1 | 122 | -1 | 10 | 120 | -1 | -1
+FB_IMUX_INDEX | FOOBAR2_ | 54 | -1 | 56 | 57 | -1 | 59 | -1 | 25 | -1 | 27 | 28 | 29 | 30 | -1 | 122 | 69 | -1 | 53 | 111 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 68 | 125 | -1 | -1 | 23 | -1 | 0 | -1 | -1 | 62 | 2 | 63 | 6 | 22 | -1 | -1 | 121 | 1 | -1 | 3 | 131 | 20 | 60 | 10 | 66 | -1 | 120
 
 
-FB_ORDER_OF_INPUTS | FOOBAR3_ | 0 | cpu_rnw | 7 | 1 | tc | NULL | 2 | start_shifting | NULL | 5 | Ncs2 | 18 | 6 | spidatain<7> | NULL
-FB_ORDER_OF_INPUTS | FOOBAR3_ | 7 | spidatain<6> | NULL | 13 | cpu_a<0> | 22 | 24 | cs1 | 20 | 25 | shifting2 | NULL | 32 | spidatain<5> | NULL
-FB_ORDER_OF_INPUTS | FOOBAR3_ | 33 | ier | NULL | 37 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | NULL | 39 | cpu_a<1> | 24 | 51 | cpu_Nphi2 | 5
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 0 | cpu_rnw | 7 | 2 | shifting2 | NULL | 3 | tc | NULL | 5 | Ncs2 | 18 | 6 | spidatain<7> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 8 | a8 | 36 | 10 | a9 | 37 | 12 | a10 | 38 | 16 | add_dec/XLXN_11 | NULL | 17 | ier | NULL
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 18 | cpu_a<1> | 24 | 22 | spi_int | 42 | 28 | spidatain<6> | NULL | 36 | cpu_a<0> | 22 | 41 | slaveinten | NULL
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 43 | start_shifting | NULL | 45 | nio_stb | 43 | 50 | nio_sel | 40 | 52 | spidatain<5> | NULL | 53 | cpu_Nphi2 | 5
 
-FB_IMUX_INDEX | FOOBAR3_ | 126 | 55 | 56 | -1 | -1 | 131 | 24 | 25 | -1 | -1 | -1 | -1 | -1 | 121 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 123 | 20 | -1 | -1 | -1 | -1 | -1 | -1 | 26 | 62 | -1 | -1 | -1 | 54 | -1 | 111 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 120 | -1 | -1
+FB_IMUX_INDEX | FOOBAR3_ | 126 | -1 | 20 | 21 | -1 | 131 | 24 | -1 | 80 | -1 | 82 | -1 | 84 | -1 | -1 | -1 | 52 | 71 | 111 | -1 | -1 | -1 | 98 | -1 | -1 | -1 | -1 | -1 | 25 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 121 | -1 | -1 | -1 | -1 | 8 | -1 | 56 | -1 | 102 | -1 | -1 | -1 | -1 | 92 | -1 | 27 | 120
 
 
-FB_ORDER_OF_INPUTS | FOOBAR4_ | 0 | cpu_rnw | 7 | 1 | tc | NULL | 2 | start_shifting | NULL | 3 | spidataout<7> | NULL | 4 | spidataout<6> | NULL
-FB_ORDER_OF_INPUTS | FOOBAR4_ | 5 | Ncs2 | 18 | 6 | spidataout<4> | NULL | 7 | spidataout<3> | NULL | 8 | spi_int | 42 | 9 | frx | NULL
-FB_ORDER_OF_INPUTS | FOOBAR4_ | 10 | slavesel | NULL | 13 | cpu_a<0> | 22 | 15 | cpol | NULL | 16 | cpu_d<7> | 13 | 17 | cpu_Nres | 19
-FB_ORDER_OF_INPUTS | FOOBAR4_ | 18 | shiftdone | NULL | 20 | cpu_d<0> | 2 | 21 | cpu_d<6> | 12 | 24 | cs1 | 20 | 25 | shifting2 | NULL
-FB_ORDER_OF_INPUTS | FOOBAR4_ | 26 | $OpTx$INV$22__$INT.UIM | NULL | 28 | slaveinten | NULL | 30 | spidataout<5> | NULL | 33 | ier | NULL | 39 | cpu_a<1> | 24
-FB_ORDER_OF_INPUTS | FOOBAR4_ | 40 | shiftcnt<0> | NULL | 42 | cpu_d<5> | 11 | 43 | cpha | NULL | 44 | cpu_d<4> | 9 | 49 | start_shifting/start_shifting_RSTF__$INT.UIM | NULL
-FB_ORDER_OF_INPUTS | FOOBAR4_ | 53 | cpu_d<3> | 8
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 0 | shiftdone | NULL | 2 | shifting2 | NULL | 3 | spidataout<7> | NULL | 4 | shiftcnt<0> | NULL | 5 | Ncs2 | 18
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 6 | spidataout<5> | NULL | 8 | spidataout<4> | NULL | 9 | frx | NULL | 10 | slavesel | NULL | 11 | spidatain<0> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 12 | shiftcnt<3> | NULL | 13 | cpu_a<0> | 22 | 14 | shiftcnt<2> | NULL | 15 | cpol | NULL | 16 | cpu_d<7> | 13
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 17 | cpha | NULL | 19 | spi_miso | 44 | 21 | cpu_d<6> | 12 | 23 | a8 | 36 | 26 | $OpTx$INV$24__$INT.UIM | NULL
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 28 | a9 | 37 | 29 | cpu_d<0> | 2 | 30 | spidataout<6> | NULL | 31 | cpu_rnw | 7 | 32 | a10 | 38
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 35 | shiftcnt<1> | NULL | 39 | cpu_a<1> | 24 | 42 | cpu_d<5> | 11 | 43 | start_shifting | NULL | 44 | cpu_d<4> | 9
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 46 | cpu_Nres | 19 | 47 | ier | NULL | 50 | nio_sel | 40 | 53 | start_shifting/start_shifting_RSTF__$INT.UIM | NULL
 
-FB_IMUX_INDEX | FOOBAR4_ | 126 | 55 | 56 | 57 | 58 | 131 | 60 | 61 | 98 | 9 | 64 | -1 | -1 | 121 | -1 | 15 | 142 | 125 | 21 | -1 | 108 | 138 | -1 | -1 | 123 | 20 | 23 | -1 | 8 | -1 | 59 | -1 | -1 | 62 | -1 | -1 | -1 | -1 | -1 | 111 | 22 | -1 | 134 | 17 | 132 | -1 | -1 | -1 | -1 | 35 | -1 | -1 | -1 | 130
+FB_IMUX_INDEX | FOOBAR4_ | 54 | -1 | 20 | 57 | 22 | 131 | 60 | -1 | 62 | 9 | 64 | 65 | 66 | 121 | 68 | 15 | 142 | 17 | -1 | 104 | -1 | 138 | -1 | 80 | -1 | -1 | 23 | -1 | 82 | 108 | 59 | 126 | 84 | -1 | -1 | 69 | -1 | -1 | -1 | 111 | -1 | -1 | 134 | 56 | 132 | -1 | 125 | 71 | -1 | -1 | 92 | -1 | -1 | 35
 
+
+GLOBAL_FCLK | extclk | 1 | 1
diff --git a/spi6502b.xml b/spi6502b.xml
index b769fc7..8efeb2e 100644
--- a/spi6502b.xml
+++ b/spi6502b.xml
@@ -1,3 +1,3 @@
 <?xml version='1.0' encoding='utf-8' ?>
 <!DOCTYPE document SYSTEM "file:///C:/Xilinx/xc9500xl/data/xmlReport9kxl.dtd">
-<document><ascFile>spi6502b.rpt</ascFile><devFile>C:/Xilinx/xc9500xl/data/xc9572xl.chp</devFile><mfdFile>spi6502b.mfd</mfdFile><htmlFile logo="xc9500xl_logo.jpg" pin_legend="pinlegend.htm" logic_legend="logiclegend.htm"/><header pkg="PC44" date=" 5- 6-2017" time="  5:47PM" speed="-10" design="spi6502b" device="XC9572XL" status="1" eqnType="1" version="1.0" statusStr="Successful" swVersion="G.38"/><inputs id="cpu_Nres"/><inputs id="cpu_rnw"/><inputs id="Ncs2"/><inputs id="cs1"/><inputs id="cpu_d0PIN_SPECSIG"/><inputs id="cpu_a0_SPECSIG"/><inputs id="cpu_a1_SPECSIG"/><inputs id="cpu_d1PIN_SPECSIG"/><inputs id="cpu_d2PIN_SPECSIG"/><inputs id="cpu_d4PIN_SPECSIG"/><inputs id="cpu_d6PIN_SPECSIG"/><inputs id="cpu_d3PIN_SPECSIG"/><inputs id="spi_miso"/><inputs id="cpu_Nphi2"/><inputs id="cpu_d5PIN_SPECSIG"/><inputs id="cpu_d7PIN_SPECSIG"/><inputs id="spi_int"/><inputs id="extclk"/><pin id="FB1_MC2_PIN1" use="b_SPECSIG" pinnum="1" signal="spidataout2_SPECSIG"/><pin id="FB1_MC5_PIN2" use="IO_SPECSIG" pinnum="2" signal="cpu_d0_SPECSIG"/><pin id="FB1_MC6_PIN3" use="IO_SPECSIG" pinnum="3" signal="cpu_d1_SPECSIG"/><pin id="FB1_MC8_PIN4" use="IO_SPECSIG" pinnum="4" signal="cpu_d2_SPECSIG"/><pin id="FB1_MC9_PIN5" use="I" pinnum="5" signal="cpu_Nphi2"/><pin id="FB1_MC11_PIN6" use="I" pinnum="6" signal="extclk"/><pin id="FB1_MC14_PIN7" use="I" pinnum="7" signal="cpu_rnw"/><pin id="FB1_MC15_PIN8" use="IO_SPECSIG" pinnum="8" signal="cpu_d3_SPECSIG"/><pin id="FB1_MC17_PIN9" use="IO_SPECSIG" pinnum="9" signal="cpu_d4_SPECSIG"/><pin id="FB2_MC2_PIN35" use="O" pinnum="35" signal="spi_mosi"/><pin id="FB2_MC5_PIN36" use="b_SPECSIG" pinnum="36" signal="shiftcnt0_SPECSIG"/><pin id="FB2_MC6_PIN37" use="b_SPECSIG" pinnum="37" signal="OpTxINV22__INT_SPECSIG"/><pin id="FB2_MC8_PIN38" use="b_SPECSIG" pinnum="38" signal="spidatain6_SPECSIG"/><pin id="FB2_MC9_PIN39" use="b_SPECSIG" pinnum="39" signal="spidatain5_SPECSIG"/><pin id="FB2_MC11_PIN40" use="b_SPECSIG" pinnum="40" signal="spidatain3_SPECSIG"/><pin id="FB2_MC14_PIN42" use="I" pinnum="42" signal="spi_int"/><pin id="FB2_MC15_PIN43" use="b_SPECSIG" pinnum="43" signal="shiftcnt3_SPECSIG"/><pin id="FB2_MC17_PIN44" use="I" pinnum="44" signal="spi_miso"/><pin id="FB3_MC2_PIN11" use="IO_SPECSIG" pinnum="11" signal="cpu_d5_SPECSIG"/><pin id="FB3_MC5_PIN12" use="IO_SPECSIG" pinnum="12" signal="cpu_d6_SPECSIG"/><pin id="FB3_MC8_PIN13" use="IO_SPECSIG" pinnum="13" signal="cpu_d7_SPECSIG"/><pin id="FB3_MC9_PIN14" use="O" pinnum="14" signal="cpu_Nirq"/><pin id="FB3_MC11_PIN18" use="I" pinnum="18" signal="Ncs2"/><pin id="FB3_MC14_PIN19" use="I" pinnum="19" signal="cpu_Nres"/><pin id="FB3_MC15_PIN20" use="I" pinnum="20" signal="cs1"/><pin id="FB3_MC16_PIN24" use="I" pinnum="24" signal="cpu_a1_SPECSIG"/><pin id="FB3_MC17_PIN22" use="I" pinnum="22" signal="cpu_a0_SPECSIG"/><pin id="FB4_MC2_PIN25" use="b_SPECSIG" pinnum="25" signal="tc"/><pin id="FB4_MC5_PIN26" use="b_SPECSIG" pinnum="26" signal="spidataout6_SPECSIG"/><pin id="FB4_MC8_PIN27" use="b_SPECSIG" pinnum="27" signal="spidataout3_SPECSIG"/><pin id="FB4_MC11_PIN28" use="O" pinnum="28" signal="spi_Nsel"/><pin id="FB4_MC14_PIN29" use="O" pinnum="29" signal="led"/><pin id="FB4_MC15_PIN33" pinnum="33"/><pin id="FB4_MC17_PIN34" use="O" pinnum="34" signal="spi_sclk"/><fblock id="FB1" pinUse="8" inputUse="31"><macrocell id="FB1_MC1"/><macrocell id="FB1_MC2" pin="FB1_MC2_PIN1" sigUse="8" signal="spidataout2_SPECSIG"><pterms pt1="FB1_2_1" pt2="FB1_2_2" pt3="FB1_2_3" pt4="FB1_2_4"/></macrocell><macrocell id="FB1_MC3" sigUse="8" signal="spidataout1_SPECSIG"><pterms pt1="FB1_3_1" pt2="FB1_3_2" pt3="FB1_3_3" pt4="FB1_3_4"/></macrocell><macrocell id="FB1_MC4" sigUse="8" signal="spidataout0_SPECSIG"><pterms pt1="FB1_4_1" pt2="FB1_4_2" pt3="FB1_4_3" pt4="FB1_4_4"/></macrocell><macrocell id="FB1_MC5" pin="FB1_MC5_PIN2" sigUse="10" signal="cpu_d0_SPECSIG"><pterms pt1="FB1_5_1" pt2="FB1_5_2" pt3="FB1_5_3" pt4="FB1_5_4" pt5="FB1_5_5"/></macrocell><macrocell id="FB1_MC6" pin="FB1_MC6_PIN3" sigUse="9" signal="cpu_d1_SPECSIG"><pterms pt1="FB1_6_1" pt2="FB1_6_2" pt3="FB1_6_3" pt4="FB1_6_4"/></macrocell><macrocell id="FB1_MC7" sigUse="8" signal="tmo"><pterms pt1="FB1_7_1" pt2="FB1_7_2" pt3="FB1_7_3" pt4="FB1_7_4" pt5="FB1_7_5"/></macrocell><macrocell id="FB1_MC8" pin="FB1_MC8_PIN4" sigUse="9" signal="cpu_d2_SPECSIG"><pterms pt1="FB1_8_1" pt2="FB1_8_2" pt3="FB1_8_3" pt4="FB1_8_4"/></macrocell><macrocell id="FB1_MC9" pin="FB1_MC9_PIN5" sigUse="8" signal="slaveinten"><pterms pt1="FB1_9_1" pt2="FB1_9_2" pt3="FB1_9_3" pt4="FB1_9_4" pt5="FB1_9_5"/></macrocell><macrocell id="FB1_MC10" sigUse="8" signal="frx"><pterms pt1="FB1_10_1" pt2="FB1_10_2" pt3="FB1_10_3" pt4="FB1_10_4" pt5="FB1_10_5"/></macrocell><macrocell id="FB1_MC11" pin="FB1_MC11_PIN6" sigUse="8" signal="ece"><pterms pt1="FB1_11_1" pt2="FB1_11_2" pt3="FB1_11_3" pt4="FB1_11_4" pt5="FB1_11_5"/></macrocell><macrocell id="FB1_MC12" sigUse="8" signal="divisor2_SPECSIG"><pterms pt1="FB1_12_1" pt2="FB1_12_2" pt3="FB1_12_3" pt4="FB1_12_4" pt5="FB1_12_5"/></macrocell><macrocell id="FB1_MC13" sigUse="8" signal="divisor1_SPECSIG"><pterms pt1="FB1_13_1" pt2="FB1_13_2" pt3="FB1_13_3" pt4="FB1_13_4" pt5="FB1_13_5"/></macrocell><macrocell id="FB1_MC14" pin="FB1_MC14_PIN7" sigUse="8" signal="divisor0_SPECSIG"><pterms pt1="FB1_14_1" pt2="FB1_14_2" pt3="FB1_14_3" pt4="FB1_14_4" pt5="FB1_14_5"/></macrocell><macrocell id="FB1_MC15" pin="FB1_MC15_PIN8" sigUse="8" signal="cpu_d3_SPECSIG"><pterms pt1="FB1_15_1" pt2="FB1_15_2" pt3="FB1_15_3"/></macrocell><macrocell id="FB1_MC16" sigUse="8" signal="cpol"><pterms pt1="FB1_16_1" pt2="FB1_16_2" pt3="FB1_16_3" pt4="FB1_16_4" pt5="FB1_16_5"/></macrocell><macrocell id="FB1_MC17" pin="FB1_MC17_PIN9" sigUse="10" signal="cpu_d4_SPECSIG"><pterms pt1="FB1_17_1" pt2="FB1_17_2" pt3="FB1_17_3" pt4="FB1_17_4" pt5="FB1_17_5"/></macrocell><macrocell id="FB1_MC18" sigUse="8" signal="cpha"><pterms pt1="FB1_18_1" pt2="FB1_18_2" pt3="FB1_18_3" pt4="FB1_18_4" pt5="FB1_18_5"/></macrocell><fbinput id="FB1_I1" fbk="PIN" signal="cpu_d0PIN_SPECSIG"/><fbinput id="FB1_I2" fbk="PIN" signal="cpu_d1PIN_SPECSIG"/><fbinput id="FB1_I3" fbk="PIN" signal="cpu_d2PIN_SPECSIG"/><fbinput id="FB1_I4" fbk="PIN" signal="cpu_d3PIN_SPECSIG"/><fbinput id="FB1_I5" fbk="PIN" signal="cpu_d4PIN_SPECSIG"/><fbinput id="FB1_I6" signal="Ncs2"/><fbinput id="FB1_I7" signal="cpha"/><fbinput id="FB1_I8" signal="cpol"/><fbinput id="FB1_I9" signal="cpu_Nphi2"/><fbinput id="FB1_I10" signal="cpu_Nres"/><fbinput id="FB1_I11" signal="cpu_a0_SPECSIG"/><fbinput id="FB1_I12" signal="cpu_a1_SPECSIG"/><fbinput id="FB1_I13" signal="cpu_rnw"/><fbinput id="FB1_I14" signal="cs1"/><fbinput id="FB1_I15" signal="divisor0_SPECSIG"/><fbinput id="FB1_I16" signal="divisor1_SPECSIG"/><fbinput id="FB1_I17" signal="divisor2_SPECSIG"/><fbinput id="FB1_I18" signal="ece"/><fbinput id="FB1_I19" signal="frx"/><fbinput id="FB1_I20" signal="slaveinten"/><fbinput id="FB1_I21" signal="spi_Nsel"/><fbinput id="FB1_I22" signal="spi_int"/><fbinput id="FB1_I23" signal="spidatain0_SPECSIG"/><fbinput id="FB1_I24" signal="spidatain1_SPECSIG"/><fbinput id="FB1_I25" signal="spidatain2_SPECSIG"/><fbinput id="FB1_I26" signal="spidatain3_SPECSIG"/><fbinput id="FB1_I27" signal="spidatain4_SPECSIG"/><fbinput id="FB1_I28" signal="spidataout0_SPECSIG"/><fbinput id="FB1_I29" signal="spidataout1_SPECSIG"/><fbinput id="FB1_I30" signal="spidataout2_SPECSIG"/><fbinput id="FB1_I31" signal="tmo"/><pterm id="FB1_2_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout2_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_2_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout2_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_2_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_2_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_3_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_3_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_3_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_3_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_4_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout0_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_4_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout0_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_4_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_4_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_5_1"><signal id="cpu_rnw"/><signal id="spi_Nsel"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_2"><signal id="cpu_rnw"/><signal id="cpha"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_3"><signal id="cpu_rnw"/><signal id="divisor0_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_4"><signal id="cpu_rnw"/><signal id="spidatain0_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_5"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_1"><signal id="cpu_rnw"/><signal id="cpol"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_2"><signal id="cpu_rnw"/><signal id="divisor1_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_3"><signal id="cpu_rnw"/><signal id="spidatain1_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_4"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_7_1"><signal id="tmo"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d3PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_7_2"><signal id="tmo" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d3PIN_SPECSIG"/></pterm><pterm id="FB1_7_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_7_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_7_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_8_1"><signal id="cpu_rnw"/><signal id="ece"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_2"><signal id="cpu_rnw"/><signal id="divisor2_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_3"><signal id="cpu_rnw"/><signal id="spidatain2_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_4"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_9_1"><signal id="slaveinten"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_9_2"><signal id="slaveinten" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB1_9_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_9_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_9_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_10_1"><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_10_2"><signal id="frx" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB1_10_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_10_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_10_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_11_1"><signal id="ece"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_11_2"><signal id="ece" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_11_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_11_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_11_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_12_1"><signal id="divisor2_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_12_2"><signal id="divisor2_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_12_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_12_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_12_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_13_1"><signal id="divisor1_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_13_2"><signal id="divisor1_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_13_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_13_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_13_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_14_1"><signal id="divisor0_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_14_2"><signal id="divisor0_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_14_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_14_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_14_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_15_1"><signal id="cpu_rnw"/><signal id="tmo"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_15_2"><signal id="cpu_rnw"/><signal id="spidatain3_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_15_3"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_16_1"><signal id="cpol"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_16_2"><signal id="cpol" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_16_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_16_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_16_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_17_1"><signal id="cpu_rnw"/><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_2"><signal id="cpu_rnw"/><signal id="slaveinten"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_3"><signal id="cpu_rnw"/><signal id="spidatain4_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_4"><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="spi_int" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_5"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_18_1"><signal id="cpha"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_18_2"><signal id="cpha" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_18_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_18_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_18_5"><signal id="cpu_rnw" negated="ON"/></pterm><equation id="spidataout2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_2_1"/><eq_pterm ptindx="FB1_2_2"/></d2><clk><eq_pterm ptindx="FB1_2_3"/></clk><ce><eq_pterm ptindx="FB1_2_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout1_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_3_1"/><eq_pterm ptindx="FB1_3_2"/></d2><clk><eq_pterm ptindx="FB1_3_3"/></clk><ce><eq_pterm ptindx="FB1_3_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_4_1"/><eq_pterm ptindx="FB1_4_2"/></d2><clk><eq_pterm ptindx="FB1_4_3"/></clk><ce><eq_pterm ptindx="FB1_4_4"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d0_SPECSIG"><d2><eq_pterm ptindx="FB1_5_1"/><eq_pterm ptindx="FB1_5_2"/><eq_pterm ptindx="FB1_5_3"/><eq_pterm ptindx="FB1_5_4"/></d2><oe><eq_pterm ptindx="FB1_5_5"/></oe></equation><equation id="cpu_d1_SPECSIG"><d2><eq_pterm ptindx="FB1_6_1"/><eq_pterm ptindx="FB1_6_2"/><eq_pterm ptindx="FB1_6_3"/></d2><oe><eq_pterm ptindx="FB1_6_4"/></oe></equation><equation id="tmo" regUse="T"><d2><eq_pterm ptindx="FB1_7_1"/><eq_pterm ptindx="FB1_7_2"/></d2><clk><eq_pterm ptindx="FB1_7_4"/></clk><reset><eq_pterm ptindx="FB1_7_3"/></reset><ce><eq_pterm ptindx="FB1_7_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d2_SPECSIG"><d2><eq_pterm ptindx="FB1_8_1"/><eq_pterm ptindx="FB1_8_2"/><eq_pterm ptindx="FB1_8_3"/></d2><oe><eq_pterm ptindx="FB1_8_4"/></oe></equation><equation id="slaveinten" regUse="T"><d2><eq_pterm ptindx="FB1_9_1"/><eq_pterm ptindx="FB1_9_2"/></d2><clk><eq_pterm ptindx="FB1_9_4"/></clk><reset><eq_pterm ptindx="FB1_9_3"/></reset><ce><eq_pterm ptindx="FB1_9_5"/></ce><prld ptindx="GND"/></equation><equation id="frx" regUse="T"><d2><eq_pterm ptindx="FB1_10_1"/><eq_pterm ptindx="FB1_10_2"/></d2><clk><eq_pterm ptindx="FB1_10_4"/></clk><reset><eq_pterm ptindx="FB1_10_3"/></reset><ce><eq_pterm ptindx="FB1_10_5"/></ce><prld ptindx="GND"/></equation><equation id="ece" regUse="T"><d2><eq_pterm ptindx="FB1_11_1"/><eq_pterm ptindx="FB1_11_2"/></d2><clk><eq_pterm ptindx="FB1_11_4"/></clk><reset><eq_pterm ptindx="FB1_11_3"/></reset><ce><eq_pterm ptindx="FB1_11_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_12_1"/><eq_pterm ptindx="FB1_12_2"/></d2><clk><eq_pterm ptindx="FB1_12_4"/></clk><reset><eq_pterm ptindx="FB1_12_3"/></reset><ce><eq_pterm ptindx="FB1_12_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor1_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_13_1"/><eq_pterm ptindx="FB1_13_2"/></d2><clk><eq_pterm ptindx="FB1_13_4"/></clk><reset><eq_pterm ptindx="FB1_13_3"/></reset><ce><eq_pterm ptindx="FB1_13_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_14_1"/><eq_pterm ptindx="FB1_14_2"/></d2><clk><eq_pterm ptindx="FB1_14_4"/></clk><reset><eq_pterm ptindx="FB1_14_3"/></reset><ce><eq_pterm ptindx="FB1_14_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d3_SPECSIG"><d2><eq_pterm ptindx="FB1_15_1"/><eq_pterm ptindx="FB1_15_2"/></d2><oe><eq_pterm ptindx="FB1_15_3"/></oe></equation><equation id="cpol" regUse="T"><d2><eq_pterm ptindx="FB1_16_1"/><eq_pterm ptindx="FB1_16_2"/></d2><clk><eq_pterm ptindx="FB1_16_4"/></clk><reset><eq_pterm ptindx="FB1_16_3"/></reset><ce><eq_pterm ptindx="FB1_16_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d4_SPECSIG"><d2><eq_pterm ptindx="FB1_17_1"/><eq_pterm ptindx="FB1_17_2"/><eq_pterm ptindx="FB1_17_3"/><eq_pterm ptindx="FB1_17_4"/></d2><oe><eq_pterm ptindx="FB1_17_5"/></oe></equation><equation id="cpha" regUse="T"><d2><eq_pterm ptindx="FB1_18_1"/><eq_pterm ptindx="FB1_18_2"/></d2><clk><eq_pterm ptindx="FB1_18_4"/></clk><reset><eq_pterm ptindx="FB1_18_3"/></reset><ce><eq_pterm ptindx="FB1_18_5"/></ce><prld ptindx="GND"/></equation></fblock><fblock id="FB2" pinUse="3" inputUse="30"><macrocell id="FB2_MC1"><pterms pt1="FB2_1_1" pt2="FB2_1_2" pt3="FB2_1_3" pt4="FB2_1_4" pt5="FB2_1_5"/></macrocell><macrocell id="FB2_MC2" pin="FB2_MC2_PIN35" sigUse="16" signal="spi_mosi"><pterms pt1="FB2_2_1" pt2="FB2_2_2" pt3="FB2_2_3" pt4="FB2_2_4" pt5="FB2_2_5"/></macrocell><macrocell id="FB2_MC3" sigUse="3" signal="shifting2"><pterms pt1="FB2_3_1" pt2="FB2_3_2" pt3="FB2_3_3"/></macrocell><macrocell id="FB2_MC4" sigUse="6" signal="shiftdone"><pterms pt1="FB2_4_1" pt2="FB2_4_2" pt3="FB2_4_3"/></macrocell><macrocell id="FB2_MC5" pin="FB2_MC5_PIN36" sigUse="4" signal="shiftcnt0_SPECSIG"><pterms pt1="FB2_5_1" pt2="FB2_5_2" pt3="FB2_5_3"/></macrocell><macrocell id="FB2_MC6" pin="FB2_MC6_PIN37" sigUse="5" signal="OpTxINV22__INT_SPECSIG"><pterms pt1="FB2_6_1" pt2="FB2_6_2" pt3="FB2_6_3"/></macrocell><macrocell id="FB2_MC7" sigUse="5" signal="spidatain7_SPECSIG"><pterms pt1="FB2_7_1" pt2="FB2_7_2" pt3="FB2_7_3" pt4="FB2_7_4"/></macrocell><macrocell id="FB2_MC8" pin="FB2_MC8_PIN38" sigUse="5" signal="spidatain6_SPECSIG"><pterms pt1="FB2_8_1" pt2="FB2_8_2" pt3="FB2_8_3" pt4="FB2_8_4"/></macrocell><macrocell id="FB2_MC9" pin="FB2_MC9_PIN39" sigUse="5" signal="spidatain5_SPECSIG"><pterms pt1="FB2_9_1" pt2="FB2_9_2" pt3="FB2_9_3" pt4="FB2_9_4"/></macrocell><macrocell id="FB2_MC10" sigUse="5" signal="spidatain4_SPECSIG"><pterms pt1="FB2_10_1" pt2="FB2_10_2" pt3="FB2_10_3" pt4="FB2_10_4"/></macrocell><macrocell id="FB2_MC11" pin="FB2_MC11_PIN40" sigUse="5" signal="spidatain3_SPECSIG"><pterms pt1="FB2_11_1" pt2="FB2_11_2" pt3="FB2_11_3" pt4="FB2_11_4"/></macrocell><macrocell id="FB2_MC12" sigUse="5" signal="spidatain2_SPECSIG"><pterms pt1="FB2_12_1" pt2="FB2_12_2" pt3="FB2_12_3" pt4="FB2_12_4"/></macrocell><macrocell id="FB2_MC13" sigUse="5" signal="spidatain1_SPECSIG"><pterms pt1="FB2_13_1" pt2="FB2_13_2" pt3="FB2_13_3" pt4="FB2_13_4"/></macrocell><macrocell id="FB2_MC14" pin="FB2_MC14_PIN42" sigUse="6" signal="spidatain0_SPECSIG"><pterms pt1="FB2_14_1" pt2="FB2_14_2" pt3="FB2_14_3" pt4="FB2_14_4"/></macrocell><macrocell id="FB2_MC15" pin="FB2_MC15_PIN43" sigUse="7" signal="shiftcnt3_SPECSIG"><pterms pt1="FB2_15_1" pt2="FB2_15_2" pt3="FB2_15_3" pt4="FB2_15_4"/></macrocell><macrocell id="FB2_MC16" sigUse="6" signal="shiftcnt2_SPECSIG"><pterms pt1="FB2_16_1" pt2="FB2_16_2" pt3="FB2_16_3" pt4="FB2_16_4"/></macrocell><macrocell id="FB2_MC17" pin="FB2_MC17_PIN44" sigUse="5" signal="shiftcnt1_SPECSIG"><pterms pt1="FB2_17_1" pt2="FB2_17_2" pt3="FB2_17_3" pt4="FB2_17_4"/></macrocell><macrocell id="FB2_MC18" sigUse="2" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"><pterms pt1="FB2_18_1"/></macrocell><fbinput id="FB2_I1" signal="OpTxINV22__INT_SPECSIG"/><fbinput id="FB2_I2" signal="cpu_Nphi2"/><fbinput id="FB2_I3" signal="cpu_Nres"/><fbinput id="FB2_I4" signal="ece"/><fbinput id="FB2_I5" signal="extclk"/><fbinput id="FB2_I6" signal="shiftcnt0_SPECSIG"/><fbinput id="FB2_I7" signal="shiftcnt1_SPECSIG"/><fbinput id="FB2_I8" signal="shiftcnt2_SPECSIG"/><fbinput id="FB2_I9" signal="shiftcnt3_SPECSIG"/><fbinput id="FB2_I10" signal="shiftdone"/><fbinput id="FB2_I11" signal="shifting2"/><fbinput id="FB2_I12" signal="spi_Nsel"/><fbinput id="FB2_I13" signal="spi_miso"/><fbinput id="FB2_I14" signal="spidatain0_SPECSIG"/><fbinput id="FB2_I15" signal="spidatain1_SPECSIG"/><fbinput id="FB2_I16" signal="spidatain2_SPECSIG"/><fbinput id="FB2_I17" signal="spidatain3_SPECSIG"/><fbinput id="FB2_I18" signal="spidatain4_SPECSIG"/><fbinput id="FB2_I19" signal="spidatain5_SPECSIG"/><fbinput id="FB2_I20" signal="spidatain6_SPECSIG"/><fbinput id="FB2_I21" signal="spidataout0_SPECSIG"/><fbinput id="FB2_I22" signal="spidataout1_SPECSIG"/><fbinput id="FB2_I23" signal="spidataout2_SPECSIG"/><fbinput id="FB2_I24" signal="spidataout3_SPECSIG"/><fbinput id="FB2_I25" signal="spidataout4_SPECSIG"/><fbinput id="FB2_I26" signal="spidataout5_SPECSIG"/><fbinput id="FB2_I27" signal="spidataout6_SPECSIG"/><fbinput id="FB2_I28" signal="spidataout7_SPECSIG"/><fbinput id="FB2_I29" signal="start_shifting"/><fbinput id="FB2_I30" signal="tmo"/><pterm id="FB2_1_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout0_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_2"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout2_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_3"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout3_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_4"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout4_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_5"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout7_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout1_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_2"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout5_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_2_4"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_2_5"><signal id="tmo" negated="ON"/></pterm><pterm id="FB2_3_1"><signal id="shiftdone" negated="ON"/><signal id="start_shifting"/></pterm><pterm id="FB2_3_2"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_3_3"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout6_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_4_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/></pterm><pterm id="FB2_4_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_4_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_5_1"><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_5_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_5_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_6_1"><signal id="ece"/><signal id="extclk" negated="ON"/></pterm><pterm id="FB2_6_2"><signal id="ece" negated="ON"/><signal id="cpu_Nphi2" negated="ON"/></pterm><pterm id="FB2_6_3"><signal id="start_shifting" negated="ON"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB2_7_1"><signal id="spidatain6_SPECSIG"/></pterm><pterm id="FB2_7_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_7_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_7_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_8_1"><signal id="spidatain5_SPECSIG"/></pterm><pterm id="FB2_8_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_8_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_8_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_9_1"><signal id="spidatain4_SPECSIG"/></pterm><pterm id="FB2_9_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_9_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_9_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_10_1"><signal id="spidatain3_SPECSIG"/></pterm><pterm id="FB2_10_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_10_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_10_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_11_1"><signal id="spidatain2_SPECSIG"/></pterm><pterm id="FB2_11_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_11_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_11_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_12_1"><signal id="spidatain1_SPECSIG"/></pterm><pterm id="FB2_12_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_12_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_12_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_13_1"><signal id="spidatain0_SPECSIG"/></pterm><pterm id="FB2_13_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_13_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_13_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_14_1"><signal id="spi_Nsel" negated="ON"/><signal id="spi_miso"/></pterm><pterm id="FB2_14_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_14_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_14_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_15_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB2_15_2"><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_15_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_15_4"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_16_1"><signal id="shiftcnt2_SPECSIG"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB2_16_2"><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_16_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_16_4"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_17_1"><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_17_2"><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_17_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_17_4"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_18_1"><signal id="cpu_Nres"/><signal id="shiftdone" negated="ON"/></pterm><equation id="spi_mosi" regUse="D" negated="ON"><d2><eq_pterm ptindx="FB2_2_1"/><eq_pterm ptindx="FB2_2_2"/><eq_pterm import="1" ptindx="FB2_1_1"/><eq_pterm import="1" ptindx="FB2_1_2"/><eq_pterm import="1" ptindx="FB2_1_3"/><eq_pterm import="1" ptindx="FB2_1_4"/><eq_pterm import="1" ptindx="FB2_1_5"/><eq_pterm import="1" ptindx="FB2_3_3"/></d2><clk><eq_pterm ptindx="FB2_2_4"/></clk><set><eq_pterm ptindx="FB2_2_3"/></set><oe><eq_pterm ptindx="FB2_2_5"/></oe><prld ptindx="GND"/></equation><equation id="shifting2" regUse="D"><d2><eq_pterm ptindx="FB2_3_1"/></d2><clk><eq_pterm ptindx="FB2_3_2"/></clk><prld ptindx="GND"/></equation><equation id="shiftdone" regUse="D"><d2><eq_pterm ptindx="FB2_4_1"/></d2><clk><eq_pterm ptindx="FB2_4_3"/></clk><reset><eq_pterm ptindx="FB2_4_2"/></reset><prld ptindx="GND"/></equation><equation id="shiftcnt0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_5_1"/></d2><clk><eq_pterm ptindx="FB2_5_3"/></clk><reset><eq_pterm ptindx="FB2_5_2"/></reset><prld ptindx="GND"/></equation><equation id="OpTxINV22__INT_SPECSIG"><d2><eq_pterm ptindx="FB2_6_1"/><eq_pterm ptindx="FB2_6_2"/><eq_pterm ptindx="FB2_6_3"/></d2></equation><equation id="spidatain7_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_7_1"/></d2><clk><eq_pterm ptindx="FB2_7_3"/></clk><reset><eq_pterm ptindx="FB2_7_2"/></reset><ce><eq_pterm ptindx="FB2_7_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain6_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_8_1"/></d2><clk><eq_pterm ptindx="FB2_8_3"/></clk><reset><eq_pterm ptindx="FB2_8_2"/></reset><ce><eq_pterm ptindx="FB2_8_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain5_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_9_1"/></d2><clk><eq_pterm ptindx="FB2_9_3"/></clk><reset><eq_pterm ptindx="FB2_9_2"/></reset><ce><eq_pterm ptindx="FB2_9_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain4_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_10_1"/></d2><clk><eq_pterm ptindx="FB2_10_3"/></clk><reset><eq_pterm ptindx="FB2_10_2"/></reset><ce><eq_pterm ptindx="FB2_10_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain3_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_11_1"/></d2><clk><eq_pterm ptindx="FB2_11_3"/></clk><reset><eq_pterm ptindx="FB2_11_2"/></reset><ce><eq_pterm ptindx="FB2_11_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain2_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_12_1"/></d2><clk><eq_pterm ptindx="FB2_12_3"/></clk><reset><eq_pterm ptindx="FB2_12_2"/></reset><ce><eq_pterm ptindx="FB2_12_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_13_1"/></d2><clk><eq_pterm ptindx="FB2_13_3"/></clk><reset><eq_pterm ptindx="FB2_13_2"/></reset><ce><eq_pterm ptindx="FB2_13_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_14_1"/></d2><clk><eq_pterm ptindx="FB2_14_3"/></clk><reset><eq_pterm ptindx="FB2_14_2"/></reset><ce><eq_pterm ptindx="FB2_14_4"/></ce><prld ptindx="GND"/></equation><equation id="shiftcnt3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_15_1"/><eq_pterm ptindx="FB2_15_2"/></d2><clk><eq_pterm ptindx="FB2_15_4"/></clk><reset><eq_pterm ptindx="FB2_15_3"/></reset><prld ptindx="GND"/></equation><equation id="shiftcnt2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_16_1"/><eq_pterm ptindx="FB2_16_2"/></d2><clk><eq_pterm ptindx="FB2_16_4"/></clk><reset><eq_pterm ptindx="FB2_16_3"/></reset><prld ptindx="GND"/></equation><equation id="shiftcnt1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_17_1"/><eq_pterm ptindx="FB2_17_2"/></d2><clk><eq_pterm ptindx="FB2_17_4"/></clk><reset><eq_pterm ptindx="FB2_17_3"/></reset><prld ptindx="GND"/></equation><equation id="start_shiftingstart_shifting_RSTF__INT_SPECSIG"><d2><eq_pterm ptindx="FB2_18_1"/></d2></equation></fblock><fblock id="FB3" pinUse="9" inputUse="14"><macrocell id="FB3_MC1"/><macrocell id="FB3_MC2" pin="FB3_MC2_PIN11" sigUse="9" signal="cpu_d5_SPECSIG"><pterms pt1="FB3_2_1" pt2="FB3_2_2" pt3="FB3_2_3" pt4="FB3_2_4"/></macrocell><macrocell id="FB3_MC3"/><macrocell id="FB3_MC4"/><macrocell id="FB3_MC5" pin="FB3_MC5_PIN12" sigUse="8" signal="cpu_d6_SPECSIG"><pterms pt1="FB3_5_1" pt2="FB3_5_2" pt3="FB3_5_3"/></macrocell><macrocell id="FB3_MC6"/><macrocell id="FB3_MC7"/><macrocell id="FB3_MC8" pin="FB3_MC8_PIN13" sigUse="8" signal="cpu_d7_SPECSIG"><pterms pt1="FB3_8_1" pt2="FB3_8_2" pt3="FB3_8_3"/></macrocell><macrocell id="FB3_MC9" pin="FB3_MC9_PIN14" sigUse="1" signal="cpu_Nirq"><pterms pt1="FB3_9_1"/></macrocell><macrocell id="FB3_MC10"/><macrocell id="FB3_MC11" pin="FB3_MC11_PIN18"/><macrocell id="FB3_MC12"/><macrocell id="FB3_MC13"/><macrocell id="FB3_MC14" pin="FB3_MC14_PIN19"/><macrocell id="FB3_MC15" pin="FB3_MC15_PIN20"/><macrocell id="FB3_MC16" pin="FB3_MC16_PIN24"/><macrocell id="FB3_MC17" pin="FB3_MC17_PIN22"/><macrocell id="FB3_MC18"/><fbinput id="FB3_I1" signal="Ncs2"/><fbinput id="FB3_I2" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/><fbinput id="FB3_I3" signal="cpu_Nphi2"/><fbinput id="FB3_I4" signal="cpu_a0_SPECSIG"/><fbinput id="FB3_I5" signal="cpu_a1_SPECSIG"/><fbinput id="FB3_I6" signal="cpu_rnw"/><fbinput id="FB3_I7" signal="cs1"/><fbinput id="FB3_I8" signal="ier"/><fbinput id="FB3_I9" signal="shifting2"/><fbinput id="FB3_I10" signal="spidatain5_SPECSIG"/><fbinput id="FB3_I11" signal="spidatain6_SPECSIG"/><fbinput id="FB3_I12" signal="spidatain7_SPECSIG"/><fbinput id="FB3_I13" signal="start_shifting"/><fbinput id="FB3_I14" signal="tc"/><pterm id="FB3_2_1"><signal id="cpu_rnw"/><signal id="spidatain5_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_2"><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_3"><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="shifting2"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_4"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_1"><signal id="cpu_rnw"/><signal id="ier"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_2"><signal id="cpu_rnw"/><signal id="spidatain6_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_3"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_1"><signal id="cpu_rnw"/><signal id="spidatain7_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_2"><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="tc"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_3"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_9_1"><signal id="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/></pterm><equation id="cpu_d5_SPECSIG"><d2><eq_pterm ptindx="FB3_2_1"/><eq_pterm ptindx="FB3_2_2"/><eq_pterm ptindx="FB3_2_3"/></d2><oe><eq_pterm ptindx="FB3_2_4"/></oe></equation><equation id="cpu_d6_SPECSIG"><d2><eq_pterm ptindx="FB3_5_1"/><eq_pterm ptindx="FB3_5_2"/></d2><oe><eq_pterm ptindx="FB3_5_3"/></oe></equation><equation id="cpu_d7_SPECSIG"><d2><eq_pterm ptindx="FB3_8_1"/><eq_pterm ptindx="FB3_8_2"/></d2><oe><eq_pterm ptindx="FB3_8_3"/></oe></equation><equation id="cpu_Nirq"><d2><eq_pterm ptindx="GND"/></d2><oe><eq_pterm ptindx="FB3_9_1"/></oe></equation></fblock><fblock id="FB4" pinUse="3" inputUse="31"><macrocell id="FB4_MC1" sigUse="4" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"><pterms pt1="FB4_1_1" pt2="FB4_1_2"/></macrocell><macrocell id="FB4_MC2" pin="FB4_MC2_PIN25" sigUse="5" signal="tc"><pterms pt1="FB4_2_1" pt2="FB4_2_2" pt3="FB4_2_3"/></macrocell><macrocell id="FB4_MC3" sigUse="8" signal="start_shifting"><pterms pt1="FB4_3_1" pt2="FB4_3_2" pt3="FB4_3_3" pt4="FB4_3_4"/></macrocell><macrocell id="FB4_MC4" sigUse="8" signal="spidataout7_SPECSIG"><pterms pt1="FB4_4_1" pt2="FB4_4_2" pt3="FB4_4_3" pt4="FB4_4_4"/></macrocell><macrocell id="FB4_MC5" pin="FB4_MC5_PIN26" sigUse="8" signal="spidataout6_SPECSIG"><pterms pt1="FB4_5_1" pt2="FB4_5_2" pt3="FB4_5_3" pt4="FB4_5_4"/></macrocell><macrocell id="FB4_MC6" sigUse="8" signal="spidataout5_SPECSIG"><pterms pt1="FB4_6_1" pt2="FB4_6_2" pt3="FB4_6_3" pt4="FB4_6_4"/></macrocell><macrocell id="FB4_MC7" sigUse="8" signal="spidataout4_SPECSIG"><pterms pt1="FB4_7_1" pt2="FB4_7_2" pt3="FB4_7_3" pt4="FB4_7_4"/></macrocell><macrocell id="FB4_MC8" pin="FB4_MC8_PIN27" sigUse="8" signal="spidataout3_SPECSIG"><pterms pt1="FB4_8_1" pt2="FB4_8_2" pt3="FB4_8_3" pt4="FB4_8_4"/></macrocell><macrocell id="FB4_MC9" sigUse="8" signal="ier"><pterms pt1="FB4_9_1" pt2="FB4_9_2" pt3="FB4_9_3" pt4="FB4_9_4" pt5="FB4_9_5"/></macrocell><macrocell id="FB4_MC10"/><macrocell id="FB4_MC11" pin="FB4_MC11_PIN28" sigUse="8" signal="spi_Nsel"><pterms pt1="FB4_11_1" pt2="FB4_11_2" pt3="FB4_11_3" pt4="FB4_11_4" pt5="FB4_11_5"/></macrocell><macrocell id="FB4_MC12"/><macrocell id="FB4_MC13"/><macrocell id="FB4_MC14" pin="FB4_MC14_PIN29" sigUse="3" signal="led"><pterms pt1="FB4_14_1"/></macrocell><macrocell id="FB4_MC15" pin="FB4_MC15_PIN33"/><macrocell id="FB4_MC16"><pterms pt1="FB4_16_1"/></macrocell><macrocell id="FB4_MC17" pin="FB4_MC17_PIN34" sigUse="7" signal="spi_sclk"><pterms pt1="FB4_17_1" pt2="FB4_17_2" pt3="FB4_17_3" pt4="FB4_17_4" pt5="FB4_17_5"/></macrocell><macrocell id="FB4_MC18"/><fbinput id="FB4_I1" signal="OpTxINV22__INT_SPECSIG"/><fbinput id="FB4_I2" fbk="PIN" signal="cpu_d0PIN_SPECSIG"/><fbinput id="FB4_I3" fbk="PIN" signal="cpu_d3PIN_SPECSIG"/><fbinput id="FB4_I4" fbk="PIN" signal="cpu_d4PIN_SPECSIG"/><fbinput id="FB4_I5" fbk="PIN" signal="cpu_d5PIN_SPECSIG"/><fbinput id="FB4_I6" fbk="PIN" signal="cpu_d6PIN_SPECSIG"/><fbinput id="FB4_I7" fbk="PIN" signal="cpu_d7PIN_SPECSIG"/><fbinput id="FB4_I8" signal="Ncs2"/><fbinput id="FB4_I9" signal="cpha"/><fbinput id="FB4_I10" signal="cpol"/><fbinput id="FB4_I11" signal="cpu_Nres"/><fbinput id="FB4_I12" signal="cpu_a0_SPECSIG"/><fbinput id="FB4_I13" signal="cpu_a1_SPECSIG"/><fbinput id="FB4_I14" signal="cpu_rnw"/><fbinput id="FB4_I15" signal="cs1"/><fbinput id="FB4_I16" signal="frx"/><fbinput id="FB4_I17" signal="ier"/><fbinput id="FB4_I18" signal="shiftcnt0_SPECSIG"/><fbinput id="FB4_I19" signal="shiftdone"/><fbinput id="FB4_I20" signal="shifting2"/><fbinput id="FB4_I21" signal="slaveinten"/><fbinput id="FB4_I22" signal="spi_Nsel"/><fbinput id="FB4_I23" signal="spi_int"/><fbinput id="FB4_I24" signal="spidataout3_SPECSIG"/><fbinput id="FB4_I25" signal="spidataout4_SPECSIG"/><fbinput id="FB4_I26" signal="spidataout5_SPECSIG"/><fbinput id="FB4_I27" signal="spidataout6_SPECSIG"/><fbinput id="FB4_I28" signal="spidataout7_SPECSIG"/><fbinput id="FB4_I29" signal="start_shifting"/><fbinput id="FB4_I30" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"/><fbinput id="FB4_I31" signal="tc"/><pterm id="FB4_1_1"><signal id="ier"/><signal id="tc"/></pterm><pterm id="FB4_1_2"><signal id="slaveinten"/><signal id="spi_int" negated="ON"/></pterm><pterm id="FB4_2_1"><signal id="shiftdone"/></pterm><pterm id="FB4_2_2"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_2_3"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_1"><signal id="cpu_rnw" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_2"><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_3"><signal id="start_shiftingstart_shifting_RSTF__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_4_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout7_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d7PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_4_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout7_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d7PIN_SPECSIG"/></pterm><pterm id="FB4_4_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_4_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_5_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout6_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d6PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_5_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout6_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d6PIN_SPECSIG"/></pterm><pterm id="FB4_5_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_5_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_6_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout5_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d5PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_6_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout5_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d5PIN_SPECSIG"/></pterm><pterm id="FB4_6_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_6_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_7_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout4_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_7_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout4_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB4_7_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_7_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_8_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout3_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d3PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_8_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout3_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d3PIN_SPECSIG"/></pterm><pterm id="FB4_8_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_8_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_9_1"><signal id="ier"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d6PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_9_2"><signal id="ier" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d6PIN_SPECSIG"/></pterm><pterm id="FB4_9_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_9_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_9_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_11_1"><signal id="spi_Nsel"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_11_2"><signal id="spi_Nsel" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB4_11_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_11_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_11_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_14_1"><signal id="spi_Nsel"/><signal id="start_shifting" negated="ON"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB4_16_1"><signal id="cpu_Nres"/><signal id="cpha"/><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB4_17_1"><signal id="cpol"/></pterm><pterm id="FB4_17_2"><signal id="cpu_Nres"/><signal id="cpha" negated="ON"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB4_17_3"><signal id="cpu_Nres" negated="ON"/><signal id="cpol" negated="ON"/></pterm><pterm id="FB4_17_4"><signal id="cpu_Nres" negated="ON"/><signal id="cpol"/></pterm><pterm id="FB4_17_5"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><equation id="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"><d2><eq_pterm ptindx="FB4_1_1"/><eq_pterm ptindx="FB4_1_2"/></d2></equation><equation id="tc" regUse="D"><d2><eq_pterm ptindx="GND"/></d2><clk><eq_pterm ptindx="FB4_2_2"/></clk><set><eq_pterm ptindx="FB4_2_1"/></set><ce><eq_pterm ptindx="FB4_2_3"/></ce><prld ptindx="GND"/></equation><equation id="start_shifting" regUse="T"><d2><eq_pterm ptindx="FB4_3_1"/><eq_pterm ptindx="FB4_3_2"/></d2><clk><eq_pterm ptindx="FB4_3_4"/></clk><reset><eq_pterm ptindx="FB4_3_3"/></reset><prld ptindx="GND"/></equation><equation id="spidataout7_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_4_1"/><eq_pterm ptindx="FB4_4_2"/></d2><clk><eq_pterm ptindx="FB4_4_3"/></clk><ce><eq_pterm ptindx="FB4_4_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout6_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_5_1"/><eq_pterm ptindx="FB4_5_2"/></d2><clk><eq_pterm ptindx="FB4_5_3"/></clk><ce><eq_pterm ptindx="FB4_5_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout5_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_6_1"/><eq_pterm ptindx="FB4_6_2"/></d2><clk><eq_pterm ptindx="FB4_6_3"/></clk><ce><eq_pterm ptindx="FB4_6_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout4_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_7_1"/><eq_pterm ptindx="FB4_7_2"/></d2><clk><eq_pterm ptindx="FB4_7_3"/></clk><ce><eq_pterm ptindx="FB4_7_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_8_1"/><eq_pterm ptindx="FB4_8_2"/></d2><clk><eq_pterm ptindx="FB4_8_3"/></clk><ce><eq_pterm ptindx="FB4_8_4"/></ce><prld ptindx="GND"/></equation><equation id="ier" regUse="T"><d2><eq_pterm ptindx="FB4_9_1"/><eq_pterm ptindx="FB4_9_2"/></d2><clk><eq_pterm ptindx="FB4_9_4"/></clk><reset><eq_pterm ptindx="FB4_9_3"/></reset><ce><eq_pterm ptindx="FB4_9_5"/></ce><prld ptindx="GND"/></equation><equation id="spi_Nsel" regUse="T"><d2><eq_pterm ptindx="FB4_11_1"/><eq_pterm ptindx="FB4_11_2"/></d2><clk><eq_pterm ptindx="FB4_11_4"/></clk><set><eq_pterm ptindx="FB4_11_3"/></set><ce><eq_pterm ptindx="FB4_11_5"/></ce><prld ptindx="GND"/></equation><equation id="led"><d2><eq_pterm ptindx="FB4_14_1"/></d2></equation><equation id="spi_sclk" regUse="D"><d1><eq_pterm ptindx="FB4_17_1"/></d1><d2><eq_pterm ptindx="FB4_17_2"/><eq_pterm import="1" ptindx="FB4_16_1"/></d2><clk><eq_pterm ptindx="FB4_17_5"/></clk><set><eq_pterm ptindx="FB4_17_4"/></set><reset><eq_pterm ptindx="FB4_17_3"/></reset><prld ptindx="GND"/></equation></fblock><vcc/><gnd/><compOpts loc="ON" part="xc9572xl-10-PC44" prld="LOW" slew="FAST" mlopt="ON" power="STD" gsropt="ON" gtsopt="ON" inputs="54" keepio="OFF" pterms="25" unused="FLOAT" exhaust="OFF" gclkopt="ON" wysiwyg="OFF" ignorets="OFF" optimize="SPEED" terminate="KEEPER"/><specSig value="cpu_d&lt;0&gt;.PIN" signal="cpu_d0PIN_SPECSIG"/><specSig value="cpu_a&lt;0&gt;" signal="cpu_a0_SPECSIG"/><specSig value="cpu_a&lt;1&gt;" signal="cpu_a1_SPECSIG"/><specSig value="cpu_d&lt;1&gt;.PIN" signal="cpu_d1PIN_SPECSIG"/><specSig value="cpu_d&lt;2&gt;.PIN" signal="cpu_d2PIN_SPECSIG"/><specSig value="cpu_d&lt;4&gt;.PIN" signal="cpu_d4PIN_SPECSIG"/><specSig value="cpu_d&lt;6&gt;.PIN" signal="cpu_d6PIN_SPECSIG"/><specSig value="cpu_d&lt;3&gt;.PIN" signal="cpu_d3PIN_SPECSIG"/><specSig value="cpu_d&lt;5&gt;.PIN" signal="cpu_d5PIN_SPECSIG"/><specSig value="cpu_d&lt;7&gt;.PIN" signal="cpu_d7PIN_SPECSIG"/><specSig value="(b)" signal="b_SPECSIG"/><specSig value="spidataout&lt;2&gt;" signal="spidataout2_SPECSIG"/><specSig value="I/O" signal="IO_SPECSIG"/><specSig value="cpu_d&lt;0&gt;" signal="cpu_d0_SPECSIG"/><specSig value="cpu_d&lt;1&gt;" signal="cpu_d1_SPECSIG"/><specSig value="cpu_d&lt;2&gt;" signal="cpu_d2_SPECSIG"/><specSig value="cpu_d&lt;3&gt;" signal="cpu_d3_SPECSIG"/><specSig value="cpu_d&lt;4&gt;" signal="cpu_d4_SPECSIG"/><specSig value="shiftcnt&lt;0&gt;" signal="shiftcnt0_SPECSIG"/><specSig value="$OpTx$INV$22__$INT" signal="OpTxINV22__INT_SPECSIG"/><specSig value="spidatain&lt;6&gt;" signal="spidatain6_SPECSIG"/><specSig value="spidatain&lt;5&gt;" signal="spidatain5_SPECSIG"/><specSig value="spidatain&lt;3&gt;" signal="spidatain3_SPECSIG"/><specSig value="shiftcnt&lt;3&gt;" signal="shiftcnt3_SPECSIG"/><specSig value="cpu_d&lt;5&gt;" signal="cpu_d5_SPECSIG"/><specSig value="cpu_d&lt;6&gt;" signal="cpu_d6_SPECSIG"/><specSig value="cpu_d&lt;7&gt;" signal="cpu_d7_SPECSIG"/><specSig value="spidataout&lt;6&gt;" signal="spidataout6_SPECSIG"/><specSig value="spidataout&lt;3&gt;" signal="spidataout3_SPECSIG"/><specSig value="spidataout&lt;1&gt;" signal="spidataout1_SPECSIG"/><specSig value="spidataout&lt;0&gt;" signal="spidataout0_SPECSIG"/><specSig value="divisor&lt;2&gt;" signal="divisor2_SPECSIG"/><specSig value="divisor&lt;1&gt;" signal="divisor1_SPECSIG"/><specSig value="divisor&lt;0&gt;" signal="divisor0_SPECSIG"/><specSig value="spidatain&lt;0&gt;" signal="spidatain0_SPECSIG"/><specSig value="spidatain&lt;1&gt;" signal="spidatain1_SPECSIG"/><specSig value="spidatain&lt;2&gt;" signal="spidatain2_SPECSIG"/><specSig value="spidatain&lt;4&gt;" signal="spidatain4_SPECSIG"/><specSig value="spidatain&lt;7&gt;" signal="spidatain7_SPECSIG"/><specSig value="shiftcnt&lt;2&gt;" signal="shiftcnt2_SPECSIG"/><specSig value="shiftcnt&lt;1&gt;" signal="shiftcnt1_SPECSIG"/><specSig value="start_shifting/start_shifting_RSTF__$INT" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"/><specSig value="spidataout&lt;4&gt;" signal="spidataout4_SPECSIG"/><specSig value="spidataout&lt;5&gt;" signal="spidataout5_SPECSIG"/><specSig value="spidataout&lt;7&gt;" signal="spidataout7_SPECSIG"/><specSig value="cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/></document>
+<document><ascFile>spi6502b.rpt</ascFile><devFile>C:/Xilinx/xc9500xl/data/xc9572xl.chp</devFile><mfdFile>spi6502b.mfd</mfdFile><htmlFile logo="xc9500xl_logo.jpg" pin_legend="pinlegend.htm" logic_legend="logiclegend.htm"/><header pkg="PC44" date=" 5-11-2017" time="  2:09AM" speed="-10" design="spi6502b" device="XC9572XL" status="1" eqnType="1" version="1.0" statusStr="Successful" swVersion="G.38"/><inputs id="cpu_Nres"/><inputs id="Ncs2"/><inputs id="cpu_rnw"/><inputs id="cpu_d0PIN_SPECSIG"/><inputs id="cpu_a0_SPECSIG"/><inputs id="cpu_a1_SPECSIG"/><inputs id="cpu_d1PIN_SPECSIG"/><inputs id="cpu_d2PIN_SPECSIG"/><inputs id="cpu_d4PIN_SPECSIG"/><inputs id="cpu_d6PIN_SPECSIG"/><inputs id="cpu_d3PIN_SPECSIG"/><inputs id="spi_miso"/><inputs id="nio_stb"/><inputs id="a9"/><inputs id="a8"/><inputs id="a10"/><inputs id="cpu_Nphi2"/><inputs id="cpu_d5PIN_SPECSIG"/><inputs id="cpu_d7PIN_SPECSIG"/><inputs id="nio_sel"/><inputs id="spi_int"/><global_inputs id="extclk" use="GCK2"/><pin id="FB1_MC2_PIN1" use="b_SPECSIG" pinnum="1" signal="spidataout2_SPECSIG"/><pin id="FB1_MC5_PIN2" use="IO_SPECSIG" pinnum="2" signal="cpu_d0_SPECSIG"/><pin id="FB1_MC6_PIN3" use="IO_SPECSIG" pinnum="3" signal="cpu_d1_SPECSIG"/><pin id="FB1_MC8_PIN4" use="IO_SPECSIG" pinnum="4" signal="cpu_d2_SPECSIG"/><pin id="FB1_MC9_PIN5" use="I" pinnum="5" signal="cpu_Nphi2"/><pin id="FB1_MC11_PIN6" use="GCKI_SPECSIG" pinnum="6" signal="extclk"/><pin id="FB1_MC14_PIN7" use="I" pinnum="7" signal="cpu_rnw"/><pin id="FB1_MC15_PIN8" use="IO_SPECSIG" pinnum="8" signal="cpu_d3_SPECSIG"/><pin id="FB1_MC17_PIN9" use="IO_SPECSIG" pinnum="9" signal="cpu_d4_SPECSIG"/><pin id="FB2_MC2_PIN35" use="O" pinnum="35" signal="spi_mosi"/><pin id="FB2_MC5_PIN36" use="I" pinnum="36" signal="a8"/><pin id="FB2_MC6_PIN37" use="I" pinnum="37" signal="a9"/><pin id="FB2_MC8_PIN38" use="I" pinnum="38" signal="a10"/><pin id="FB2_MC9_PIN39" use="O" pinnum="39" signal="cpu_Nirq"/><pin id="FB2_MC11_PIN40" use="I" pinnum="40" signal="nio_sel"/><pin id="FB2_MC14_PIN42" use="I" pinnum="42" signal="spi_int"/><pin id="FB2_MC15_PIN43" use="I" pinnum="43" signal="nio_stb"/><pin id="FB2_MC17_PIN44" use="I" pinnum="44" signal="spi_miso"/><pin id="FB3_MC2_PIN11" use="IO_SPECSIG" pinnum="11" signal="cpu_d5_SPECSIG"/><pin id="FB3_MC5_PIN12" use="IO_SPECSIG" pinnum="12" signal="cpu_d6_SPECSIG"/><pin id="FB3_MC8_PIN13" use="IO_SPECSIG" pinnum="13" signal="cpu_d7_SPECSIG"/><pin id="FB3_MC9_PIN14" use="O" pinnum="14" signal="noe"/><pin id="FB3_MC11_PIN18" use="I" pinnum="18" signal="Ncs2"/><pin id="FB3_MC14_PIN19" use="I" pinnum="19" signal="cpu_Nres"/><pin id="FB3_MC15_PIN20" use="O" pinnum="20" signal="ng"/><pin id="FB3_MC16_PIN24" use="I" pinnum="24" signal="cpu_a1_SPECSIG"/><pin id="FB3_MC17_PIN22" use="I" pinnum="22" signal="cpu_a0_SPECSIG"/><pin id="FB4_MC2_PIN25" use="O" pinnum="25" signal="b8"/><pin id="FB4_MC5_PIN26" use="O" pinnum="26" signal="b9"/><pin id="FB4_MC8_PIN27" use="O" pinnum="27" signal="b10"/><pin id="FB4_MC11_PIN28" use="O" pinnum="28" signal="spi_Nsel"/><pin id="FB4_MC14_PIN29" use="O" pinnum="29" signal="led"/><pin id="FB4_MC15_PIN33" use="b_SPECSIG" pinnum="33" signal="shiftcnt2_SPECSIG"/><pin id="FB4_MC17_PIN34" use="O" pinnum="34" signal="spi_sclk"/><fblock id="FB1" pinUse="8" inputUse="31"><macrocell id="FB1_MC1" sigUse="7" signal="spidataout3_SPECSIG"><pterms pt1="FB1_1_1" pt2="FB1_1_2" pt3="FB1_1_3" pt4="FB1_1_4"/></macrocell><macrocell id="FB1_MC2" pin="FB1_MC2_PIN1" sigUse="7" signal="spidataout2_SPECSIG"><pterms pt1="FB1_2_1" pt2="FB1_2_2" pt3="FB1_2_3" pt4="FB1_2_4"/></macrocell><macrocell id="FB1_MC3" sigUse="7" signal="spidataout1_SPECSIG"><pterms pt1="FB1_3_1" pt2="FB1_3_2" pt3="FB1_3_3" pt4="FB1_3_4"/></macrocell><macrocell id="FB1_MC4" sigUse="7" signal="spidataout0_SPECSIG"><pterms pt1="FB1_4_1" pt2="FB1_4_2" pt3="FB1_4_3" pt4="FB1_4_4"/></macrocell><macrocell id="FB1_MC5" pin="FB1_MC5_PIN2" sigUse="9" signal="cpu_d0_SPECSIG"><pterms pt1="FB1_5_1" pt2="FB1_5_2" pt3="FB1_5_3" pt4="FB1_5_4" pt5="FB1_5_5"/></macrocell><macrocell id="FB1_MC6" pin="FB1_MC6_PIN3" sigUse="8" signal="cpu_d1_SPECSIG"><pterms pt1="FB1_6_1" pt2="FB1_6_2" pt3="FB1_6_3" pt4="FB1_6_4"/></macrocell><macrocell id="FB1_MC7" sigUse="7" signal="tmo"><pterms pt1="FB1_7_1" pt2="FB1_7_2" pt3="FB1_7_3" pt4="FB1_7_4" pt5="FB1_7_5"/></macrocell><macrocell id="FB1_MC8" pin="FB1_MC8_PIN4" sigUse="8" signal="cpu_d2_SPECSIG"><pterms pt1="FB1_8_1" pt2="FB1_8_2" pt3="FB1_8_3" pt4="FB1_8_4"/></macrocell><macrocell id="FB1_MC9" pin="FB1_MC9_PIN5" sigUse="7" signal="slaveinten"><pterms pt1="FB1_9_1" pt2="FB1_9_2" pt3="FB1_9_3" pt4="FB1_9_4" pt5="FB1_9_5"/></macrocell><macrocell id="FB1_MC10" sigUse="7" signal="frx"><pterms pt1="FB1_10_1" pt2="FB1_10_2" pt3="FB1_10_3" pt4="FB1_10_4" pt5="FB1_10_5"/></macrocell><macrocell id="FB1_MC11" pin="FB1_MC11_PIN6" sigUse="7" signal="ece"><pterms pt1="FB1_11_1" pt2="FB1_11_2" pt3="FB1_11_3" pt4="FB1_11_4" pt5="FB1_11_5"/></macrocell><macrocell id="FB1_MC12" sigUse="7" signal="divisor2_SPECSIG"><pterms pt1="FB1_12_1" pt2="FB1_12_2" pt3="FB1_12_3" pt4="FB1_12_4" pt5="FB1_12_5"/></macrocell><macrocell id="FB1_MC13" sigUse="7" signal="divisor1_SPECSIG"><pterms pt1="FB1_13_1" pt2="FB1_13_2" pt3="FB1_13_3" pt4="FB1_13_4" pt5="FB1_13_5"/></macrocell><macrocell id="FB1_MC14" pin="FB1_MC14_PIN7" sigUse="7" signal="divisor0_SPECSIG"><pterms pt1="FB1_14_1" pt2="FB1_14_2" pt3="FB1_14_3" pt4="FB1_14_4" pt5="FB1_14_5"/></macrocell><macrocell id="FB1_MC15" pin="FB1_MC15_PIN8" sigUse="7" signal="cpu_d3_SPECSIG"><pterms pt1="FB1_15_1" pt2="FB1_15_2" pt3="FB1_15_3"/></macrocell><macrocell id="FB1_MC16" sigUse="7" signal="cpol"><pterms pt1="FB1_16_1" pt2="FB1_16_2" pt3="FB1_16_3" pt4="FB1_16_4" pt5="FB1_16_5"/></macrocell><macrocell id="FB1_MC17" pin="FB1_MC17_PIN9" sigUse="9" signal="cpu_d4_SPECSIG"><pterms pt1="FB1_17_1" pt2="FB1_17_2" pt3="FB1_17_3" pt4="FB1_17_4" pt5="FB1_17_5"/></macrocell><macrocell id="FB1_MC18" sigUse="7" signal="cpha"><pterms pt1="FB1_18_1" pt2="FB1_18_2" pt3="FB1_18_3" pt4="FB1_18_4" pt5="FB1_18_5"/></macrocell><fbinput id="FB1_I1" fbk="PIN" signal="cpu_d0PIN_SPECSIG"/><fbinput id="FB1_I2" fbk="PIN" signal="cpu_d1PIN_SPECSIG"/><fbinput id="FB1_I3" fbk="PIN" signal="cpu_d2PIN_SPECSIG"/><fbinput id="FB1_I4" fbk="PIN" signal="cpu_d3PIN_SPECSIG"/><fbinput id="FB1_I5" fbk="PIN" signal="cpu_d4PIN_SPECSIG"/><fbinput id="FB1_I6" signal="Ncs2"/><fbinput id="FB1_I7" signal="cpha"/><fbinput id="FB1_I8" signal="cpol"/><fbinput id="FB1_I9" signal="cpu_Nphi2"/><fbinput id="FB1_I10" signal="cpu_Nres"/><fbinput id="FB1_I11" signal="cpu_a0_SPECSIG"/><fbinput id="FB1_I12" signal="cpu_a1_SPECSIG"/><fbinput id="FB1_I13" signal="cpu_rnw"/><fbinput id="FB1_I14" signal="divisor0_SPECSIG"/><fbinput id="FB1_I15" signal="divisor1_SPECSIG"/><fbinput id="FB1_I16" signal="divisor2_SPECSIG"/><fbinput id="FB1_I17" signal="ece"/><fbinput id="FB1_I18" signal="frx"/><fbinput id="FB1_I19" signal="slaveinten"/><fbinput id="FB1_I20" signal="spi_Nsel"/><fbinput id="FB1_I21" signal="spi_int"/><fbinput id="FB1_I22" signal="spidatain0_SPECSIG"/><fbinput id="FB1_I23" signal="spidatain1_SPECSIG"/><fbinput id="FB1_I24" signal="spidatain2_SPECSIG"/><fbinput id="FB1_I25" signal="spidatain3_SPECSIG"/><fbinput id="FB1_I26" signal="spidatain4_SPECSIG"/><fbinput id="FB1_I27" signal="spidataout0_SPECSIG"/><fbinput id="FB1_I28" signal="spidataout1_SPECSIG"/><fbinput id="FB1_I29" signal="spidataout2_SPECSIG"/><fbinput id="FB1_I30" signal="spidataout3_SPECSIG"/><fbinput id="FB1_I31" signal="tmo"/><pterm id="FB1_1_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout3_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d3PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_1_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout3_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d3PIN_SPECSIG"/></pterm><pterm id="FB1_1_3"><signal id="Ncs2"/></pterm><pterm id="FB1_1_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_2_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout2_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_2_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout2_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_2_3"><signal id="Ncs2"/></pterm><pterm id="FB1_2_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_3_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_3_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_3_3"><signal id="Ncs2"/></pterm><pterm id="FB1_3_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_4_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout0_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_4_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout0_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_4_3"><signal id="Ncs2"/></pterm><pterm id="FB1_4_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_5_1"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spi_Nsel"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_2"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpha"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_3"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="divisor0_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_4"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spidatain0_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_5"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_1"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpol"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_2"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="divisor1_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_3"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spidatain1_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_4"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_7_1"><signal id="tmo"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d3PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_7_2"><signal id="tmo" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d3PIN_SPECSIG"/></pterm><pterm id="FB1_7_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_7_4"><signal id="Ncs2"/></pterm><pterm id="FB1_7_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_8_1"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="ece"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_2"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="divisor2_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_3"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spidatain2_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_4"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_9_1"><signal id="slaveinten"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_9_2"><signal id="slaveinten" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB1_9_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_9_4"><signal id="Ncs2"/></pterm><pterm id="FB1_9_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_10_1"><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_10_2"><signal id="frx" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB1_10_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_10_4"><signal id="Ncs2"/></pterm><pterm id="FB1_10_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_11_1"><signal id="ece"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_11_2"><signal id="ece" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_11_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_11_4"><signal id="Ncs2"/></pterm><pterm id="FB1_11_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_12_1"><signal id="divisor2_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_12_2"><signal id="divisor2_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_12_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_12_4"><signal id="Ncs2"/></pterm><pterm id="FB1_12_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_13_1"><signal id="divisor1_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_13_2"><signal id="divisor1_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_13_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_13_4"><signal id="Ncs2"/></pterm><pterm id="FB1_13_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_14_1"><signal id="divisor0_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_14_2"><signal id="divisor0_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_14_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_14_4"><signal id="Ncs2"/></pterm><pterm id="FB1_14_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_15_1"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="tmo"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_15_2"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spidatain3_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_15_3"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_16_1"><signal id="cpol"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_16_2"><signal id="cpol" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_16_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_16_4"><signal id="Ncs2"/></pterm><pterm id="FB1_16_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_17_1"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_2"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="slaveinten"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_3"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spidatain4_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_4"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="spi_int" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_5"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_18_1"><signal id="cpha"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_18_2"><signal id="cpha" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_18_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_18_4"><signal id="Ncs2"/></pterm><pterm id="FB1_18_5"><signal id="cpu_rnw" negated="ON"/></pterm><equation id="spidataout3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_1_1"/><eq_pterm ptindx="FB1_1_2"/></d2><clk><eq_pterm ptindx="FB1_1_3"/></clk><ce><eq_pterm ptindx="FB1_1_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_2_1"/><eq_pterm ptindx="FB1_2_2"/></d2><clk><eq_pterm ptindx="FB1_2_3"/></clk><ce><eq_pterm ptindx="FB1_2_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout1_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_3_1"/><eq_pterm ptindx="FB1_3_2"/></d2><clk><eq_pterm ptindx="FB1_3_3"/></clk><ce><eq_pterm ptindx="FB1_3_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_4_1"/><eq_pterm ptindx="FB1_4_2"/></d2><clk><eq_pterm ptindx="FB1_4_3"/></clk><ce><eq_pterm ptindx="FB1_4_4"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d0_SPECSIG"><d2><eq_pterm ptindx="FB1_5_1"/><eq_pterm ptindx="FB1_5_2"/><eq_pterm ptindx="FB1_5_3"/><eq_pterm ptindx="FB1_5_4"/></d2><oe><eq_pterm ptindx="FB1_5_5"/></oe></equation><equation id="cpu_d1_SPECSIG"><d2><eq_pterm ptindx="FB1_6_1"/><eq_pterm ptindx="FB1_6_2"/><eq_pterm ptindx="FB1_6_3"/></d2><oe><eq_pterm ptindx="FB1_6_4"/></oe></equation><equation id="tmo" regUse="T"><d2><eq_pterm ptindx="FB1_7_1"/><eq_pterm ptindx="FB1_7_2"/></d2><clk><eq_pterm ptindx="FB1_7_4"/></clk><reset><eq_pterm ptindx="FB1_7_3"/></reset><ce><eq_pterm ptindx="FB1_7_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d2_SPECSIG"><d2><eq_pterm ptindx="FB1_8_1"/><eq_pterm ptindx="FB1_8_2"/><eq_pterm ptindx="FB1_8_3"/></d2><oe><eq_pterm ptindx="FB1_8_4"/></oe></equation><equation id="slaveinten" regUse="T"><d2><eq_pterm ptindx="FB1_9_1"/><eq_pterm ptindx="FB1_9_2"/></d2><clk><eq_pterm ptindx="FB1_9_4"/></clk><reset><eq_pterm ptindx="FB1_9_3"/></reset><ce><eq_pterm ptindx="FB1_9_5"/></ce><prld ptindx="GND"/></equation><equation id="frx" regUse="T"><d2><eq_pterm ptindx="FB1_10_1"/><eq_pterm ptindx="FB1_10_2"/></d2><clk><eq_pterm ptindx="FB1_10_4"/></clk><reset><eq_pterm ptindx="FB1_10_3"/></reset><ce><eq_pterm ptindx="FB1_10_5"/></ce><prld ptindx="GND"/></equation><equation id="ece" regUse="T"><d2><eq_pterm ptindx="FB1_11_1"/><eq_pterm ptindx="FB1_11_2"/></d2><clk><eq_pterm ptindx="FB1_11_4"/></clk><reset><eq_pterm ptindx="FB1_11_3"/></reset><ce><eq_pterm ptindx="FB1_11_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_12_1"/><eq_pterm ptindx="FB1_12_2"/></d2><clk><eq_pterm ptindx="FB1_12_4"/></clk><reset><eq_pterm ptindx="FB1_12_3"/></reset><ce><eq_pterm ptindx="FB1_12_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor1_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_13_1"/><eq_pterm ptindx="FB1_13_2"/></d2><clk><eq_pterm ptindx="FB1_13_4"/></clk><reset><eq_pterm ptindx="FB1_13_3"/></reset><ce><eq_pterm ptindx="FB1_13_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_14_1"/><eq_pterm ptindx="FB1_14_2"/></d2><clk><eq_pterm ptindx="FB1_14_4"/></clk><reset><eq_pterm ptindx="FB1_14_3"/></reset><ce><eq_pterm ptindx="FB1_14_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d3_SPECSIG"><d2><eq_pterm ptindx="FB1_15_1"/><eq_pterm ptindx="FB1_15_2"/></d2><oe><eq_pterm ptindx="FB1_15_3"/></oe></equation><equation id="cpol" regUse="T"><d2><eq_pterm ptindx="FB1_16_1"/><eq_pterm ptindx="FB1_16_2"/></d2><clk><eq_pterm ptindx="FB1_16_4"/></clk><reset><eq_pterm ptindx="FB1_16_3"/></reset><ce><eq_pterm ptindx="FB1_16_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d4_SPECSIG"><d2><eq_pterm ptindx="FB1_17_1"/><eq_pterm ptindx="FB1_17_2"/><eq_pterm ptindx="FB1_17_3"/><eq_pterm ptindx="FB1_17_4"/></d2><oe><eq_pterm ptindx="FB1_17_5"/></oe></equation><equation id="cpha" regUse="T"><d2><eq_pterm ptindx="FB1_18_1"/><eq_pterm ptindx="FB1_18_2"/></d2><clk><eq_pterm ptindx="FB1_18_4"/></clk><reset><eq_pterm ptindx="FB1_18_3"/></reset><ce><eq_pterm ptindx="FB1_18_5"/></ce><prld ptindx="GND"/></equation></fblock><fblock id="FB2" pinUse="9" inputUse="31"><macrocell id="FB2_MC1"><pterms pt1="FB2_1_1" pt2="FB2_1_2" pt3="FB2_1_3" pt4="FB2_1_4" pt5="FB2_1_5"/></macrocell><macrocell id="FB2_MC2" pin="FB2_MC2_PIN35" sigUse="16" signal="spi_mosi"><pterms pt1="FB2_2_1" pt2="FB2_2_2" pt3="FB2_2_3" pt4="FB2_2_4" pt5="FB2_2_5"/></macrocell><macrocell id="FB2_MC3" sigUse="3" signal="shifting2"><pterms pt1="FB2_3_1" pt2="FB2_3_2" pt3="FB2_3_3"/></macrocell><macrocell id="FB2_MC4" sigUse="4" signal="tc"><pterms pt1="FB2_4_1" pt2="FB2_4_2" pt3="FB2_4_3"/></macrocell><macrocell id="FB2_MC5" pin="FB2_MC5_PIN36" sigUse="4" signal="shiftcnt0_SPECSIG"><pterms pt1="FB2_5_1" pt2="FB2_5_2" pt3="FB2_5_3"/></macrocell><macrocell id="FB2_MC6" pin="FB2_MC6_PIN37" sigUse="5" signal="OpTxINV24__INT_SPECSIG"><pterms pt1="FB2_6_1" pt2="FB2_6_2" pt3="FB2_6_3"/></macrocell><macrocell id="FB2_MC7" sigUse="5" signal="spidatain7_SPECSIG"><pterms pt1="FB2_7_1" pt2="FB2_7_2" pt3="FB2_7_3" pt4="FB2_7_4"/></macrocell><macrocell id="FB2_MC8" pin="FB2_MC8_PIN38" sigUse="5" signal="spidatain6_SPECSIG"><pterms pt1="FB2_8_1" pt2="FB2_8_2" pt3="FB2_8_3" pt4="FB2_8_4"/></macrocell><macrocell id="FB2_MC9" pin="FB2_MC9_PIN39" sigUse="1" signal="cpu_Nirq"><pterms pt1="FB2_9_1"/></macrocell><macrocell id="FB2_MC10" sigUse="5" signal="spidatain5_SPECSIG"><pterms pt1="FB2_10_1" pt2="FB2_10_2" pt3="FB2_10_3" pt4="FB2_10_4"/></macrocell><macrocell id="FB2_MC11" pin="FB2_MC11_PIN40" sigUse="5" signal="spidatain4_SPECSIG"><pterms pt1="FB2_11_1" pt2="FB2_11_2" pt3="FB2_11_3" pt4="FB2_11_4"/></macrocell><macrocell id="FB2_MC12" sigUse="5" signal="spidatain3_SPECSIG"><pterms pt1="FB2_12_1" pt2="FB2_12_2" pt3="FB2_12_3" pt4="FB2_12_4"/></macrocell><macrocell id="FB2_MC13" sigUse="5" signal="spidatain2_SPECSIG"><pterms pt1="FB2_13_1" pt2="FB2_13_2" pt3="FB2_13_3" pt4="FB2_13_4"/></macrocell><macrocell id="FB2_MC14" pin="FB2_MC14_PIN42"/><macrocell id="FB2_MC15" pin="FB2_MC15_PIN43"/><macrocell id="FB2_MC16"/><macrocell id="FB2_MC17" pin="FB2_MC17_PIN44"/><macrocell id="FB2_MC18" sigUse="2" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"><pterms pt1="FB2_18_1"/></macrocell><fbinput id="FB2_I1" signal="OpTxINV24__INT_SPECSIG"/><fbinput id="FB2_I2" signal="Ncs2"/><fbinput id="FB2_I3" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/><fbinput id="FB2_I4" signal="cpu_Nphi2"/><fbinput id="FB2_I5" signal="cpu_Nres"/><fbinput id="FB2_I6" signal="cpu_a0_SPECSIG"/><fbinput id="FB2_I7" signal="cpu_a1_SPECSIG"/><fbinput id="FB2_I8" signal="ece"/><fbinput id="FB2_I9" signal="extclk"/><fbinput id="FB2_I10" signal="shiftcnt0_SPECSIG"/><fbinput id="FB2_I11" signal="shiftcnt1_SPECSIG"/><fbinput id="FB2_I12" signal="shiftcnt2_SPECSIG"/><fbinput id="FB2_I13" signal="shiftcnt3_SPECSIG"/><fbinput id="FB2_I14" signal="shiftdone"/><fbinput id="FB2_I15" signal="shifting2"/><fbinput id="FB2_I16" signal="spidatain1_SPECSIG"/><fbinput id="FB2_I17" signal="spidatain2_SPECSIG"/><fbinput id="FB2_I18" signal="spidatain3_SPECSIG"/><fbinput id="FB2_I19" signal="spidatain4_SPECSIG"/><fbinput id="FB2_I20" signal="spidatain5_SPECSIG"/><fbinput id="FB2_I21" signal="spidatain6_SPECSIG"/><fbinput id="FB2_I22" signal="spidataout0_SPECSIG"/><fbinput id="FB2_I23" signal="spidataout1_SPECSIG"/><fbinput id="FB2_I24" signal="spidataout2_SPECSIG"/><fbinput id="FB2_I25" signal="spidataout3_SPECSIG"/><fbinput id="FB2_I26" signal="spidataout4_SPECSIG"/><fbinput id="FB2_I27" signal="spidataout5_SPECSIG"/><fbinput id="FB2_I28" signal="spidataout6_SPECSIG"/><fbinput id="FB2_I29" signal="spidataout7_SPECSIG"/><fbinput id="FB2_I30" signal="start_shifting"/><fbinput id="FB2_I31" signal="tmo"/><pterm id="FB2_1_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout2_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_2"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout3_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_3"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout5_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_4"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout6_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_5"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout7_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout0_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_2"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout4_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_2_4"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_2_5"><signal id="tmo" negated="ON"/></pterm><pterm id="FB2_3_1"><signal id="shiftdone" negated="ON"/><signal id="start_shifting"/></pterm><pterm id="FB2_3_2"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_3_3"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout1_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_4_1"><signal id="shiftdone"/></pterm><pterm id="FB2_4_2"><signal id="Ncs2"/></pterm><pterm id="FB2_4_3"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB2_5_1"><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_5_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_5_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_6_1"><signal id="ece"/><signal id="extclk" negated="ON"/></pterm><pterm id="FB2_6_2"><signal id="ece" negated="ON"/><signal id="cpu_Nphi2" negated="ON"/></pterm><pterm id="FB2_6_3"><signal id="start_shifting" negated="ON"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB2_7_1"><signal id="spidatain6_SPECSIG"/></pterm><pterm id="FB2_7_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_7_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_7_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_8_1"><signal id="spidatain5_SPECSIG"/></pterm><pterm id="FB2_8_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_8_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_8_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_9_1"><signal id="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/></pterm><pterm id="FB2_10_1"><signal id="spidatain4_SPECSIG"/></pterm><pterm id="FB2_10_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_10_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_10_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_11_1"><signal id="spidatain3_SPECSIG"/></pterm><pterm id="FB2_11_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_11_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_11_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_12_1"><signal id="spidatain2_SPECSIG"/></pterm><pterm id="FB2_12_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_12_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_12_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_13_1"><signal id="spidatain1_SPECSIG"/></pterm><pterm id="FB2_13_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_13_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_13_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_18_1"><signal id="cpu_Nres"/><signal id="shiftdone" negated="ON"/></pterm><equation id="spi_mosi" regUse="D" negated="ON"><d2><eq_pterm ptindx="FB2_2_1"/><eq_pterm ptindx="FB2_2_2"/><eq_pterm import="1" ptindx="FB2_1_1"/><eq_pterm import="1" ptindx="FB2_1_2"/><eq_pterm import="1" ptindx="FB2_1_3"/><eq_pterm import="1" ptindx="FB2_1_4"/><eq_pterm import="1" ptindx="FB2_1_5"/><eq_pterm import="1" ptindx="FB2_3_3"/></d2><clk><eq_pterm ptindx="FB2_2_4"/></clk><set><eq_pterm ptindx="FB2_2_3"/></set><oe><eq_pterm ptindx="FB2_2_5"/></oe><prld ptindx="GND"/></equation><equation id="shifting2" regUse="D"><d2><eq_pterm ptindx="FB2_3_1"/></d2><clk><eq_pterm ptindx="FB2_3_2"/></clk><prld ptindx="GND"/></equation><equation id="tc" regUse="D"><d2><eq_pterm ptindx="GND"/></d2><clk><eq_pterm ptindx="FB2_4_2"/></clk><set><eq_pterm ptindx="FB2_4_1"/></set><ce><eq_pterm ptindx="FB2_4_3"/></ce><prld ptindx="GND"/></equation><equation id="shiftcnt0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_5_1"/></d2><clk><eq_pterm ptindx="FB2_5_3"/></clk><reset><eq_pterm ptindx="FB2_5_2"/></reset><prld ptindx="GND"/></equation><equation id="OpTxINV24__INT_SPECSIG"><d2><eq_pterm ptindx="FB2_6_1"/><eq_pterm ptindx="FB2_6_2"/><eq_pterm ptindx="FB2_6_3"/></d2></equation><equation id="spidatain7_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_7_1"/></d2><clk><eq_pterm ptindx="FB2_7_3"/></clk><reset><eq_pterm ptindx="FB2_7_2"/></reset><ce><eq_pterm ptindx="FB2_7_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain6_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_8_1"/></d2><clk><eq_pterm ptindx="FB2_8_3"/></clk><reset><eq_pterm ptindx="FB2_8_2"/></reset><ce><eq_pterm ptindx="FB2_8_4"/></ce><prld ptindx="GND"/></equation><equation id="cpu_Nirq"><d2><eq_pterm ptindx="GND"/></d2><oe><eq_pterm ptindx="FB2_9_1"/></oe></equation><equation id="spidatain5_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_10_1"/></d2><clk><eq_pterm ptindx="FB2_10_3"/></clk><reset><eq_pterm ptindx="FB2_10_2"/></reset><ce><eq_pterm ptindx="FB2_10_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain4_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_11_1"/></d2><clk><eq_pterm ptindx="FB2_11_3"/></clk><reset><eq_pterm ptindx="FB2_11_2"/></reset><ce><eq_pterm ptindx="FB2_11_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain3_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_12_1"/></d2><clk><eq_pterm ptindx="FB2_12_3"/></clk><reset><eq_pterm ptindx="FB2_12_2"/></reset><ce><eq_pterm ptindx="FB2_12_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain2_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_13_1"/></d2><clk><eq_pterm ptindx="FB2_13_3"/></clk><reset><eq_pterm ptindx="FB2_13_2"/></reset><ce><eq_pterm ptindx="FB2_13_4"/></ce><prld ptindx="GND"/></equation><equation id="start_shiftingstart_shifting_RSTF__INT_SPECSIG"><d2><eq_pterm ptindx="FB2_18_1"/></d2></equation></fblock><fblock id="FB3" pinUse="9" inputUse="20"><macrocell id="FB3_MC1"/><macrocell id="FB3_MC2" pin="FB3_MC2_PIN11" sigUse="8" signal="cpu_d5_SPECSIG"><pterms pt1="FB3_2_1" pt2="FB3_2_2" pt3="FB3_2_3" pt4="FB3_2_4"/></macrocell><macrocell id="FB3_MC3"/><macrocell id="FB3_MC4"/><macrocell id="FB3_MC5" pin="FB3_MC5_PIN12" sigUse="7" signal="cpu_d6_SPECSIG"><pterms pt1="FB3_5_1" pt2="FB3_5_2" pt3="FB3_5_3"/></macrocell><macrocell id="FB3_MC6"/><macrocell id="FB3_MC7"/><macrocell id="FB3_MC8" pin="FB3_MC8_PIN13" sigUse="7" signal="cpu_d7_SPECSIG"><pterms pt1="FB3_8_1" pt2="FB3_8_2" pt3="FB3_8_3"/></macrocell><macrocell id="FB3_MC9" pin="FB3_MC9_PIN14" sigUse="3" signal="noe"><pterms pt1="FB3_9_1" pt2="FB3_9_2"/></macrocell><macrocell id="FB3_MC10"/><macrocell id="FB3_MC11" pin="FB3_MC11_PIN18"/><macrocell id="FB3_MC12"/><macrocell id="FB3_MC13"/><macrocell id="FB3_MC14" pin="FB3_MC14_PIN19"/><macrocell id="FB3_MC15" pin="FB3_MC15_PIN20" sigUse="3" signal="ng"><pterms pt1="FB3_15_1"/></macrocell><macrocell id="FB3_MC16" pin="FB3_MC16_PIN24"/><macrocell id="FB3_MC17" pin="FB3_MC17_PIN22" sigUse="4" signal="add_decXLXN_11_SPECSIG"><pterms pt1="FB3_17_1"/></macrocell><macrocell id="FB3_MC18" sigUse="4" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"><pterms pt1="FB3_18_1" pt2="FB3_18_2"/></macrocell><fbinput id="FB3_I1" signal="Ncs2"/><fbinput id="FB3_I2" signal="a10"/><fbinput id="FB3_I3" signal="a8"/><fbinput id="FB3_I4" signal="a9"/><fbinput id="FB3_I5" signal="add_decXLXN_11_SPECSIG"/><fbinput id="FB3_I6" signal="cpu_Nphi2"/><fbinput id="FB3_I7" signal="cpu_a0_SPECSIG"/><fbinput id="FB3_I8" signal="cpu_a1_SPECSIG"/><fbinput id="FB3_I9" signal="cpu_rnw"/><fbinput id="FB3_I10" signal="ier"/><fbinput id="FB3_I11" signal="nio_sel"/><fbinput id="FB3_I12" signal="nio_stb"/><fbinput id="FB3_I13" signal="shifting2"/><fbinput id="FB3_I14" signal="slaveinten"/><fbinput id="FB3_I15" signal="spi_int"/><fbinput id="FB3_I16" signal="spidatain5_SPECSIG"/><fbinput id="FB3_I17" signal="spidatain6_SPECSIG"/><fbinput id="FB3_I18" signal="spidatain7_SPECSIG"/><fbinput id="FB3_I19" signal="start_shifting"/><fbinput id="FB3_I20" signal="tc"/><pterm id="FB3_2_1"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spidatain5_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_2"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_3"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="shifting2"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_4"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_1"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="ier"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_2"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spidatain6_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_3"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_1"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="spidatain7_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_2"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="tc"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_3"><signal id="Ncs2" negated="ON"/><signal id="cpu_rnw"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_9_1"><signal id="nio_stb" negated="ON"/><signal id="add_decXLXN_11_SPECSIG"/></pterm><pterm id="FB3_9_2"><signal id="nio_sel" negated="ON"/><signal id="add_decXLXN_11_SPECSIG"/></pterm><pterm id="FB3_15_1"><signal id="Ncs2"/><signal id="nio_stb"/><signal id="nio_sel"/></pterm><pterm id="FB3_17_1"><signal id="nio_stb" negated="ON"/><signal id="a9"/><signal id="a8"/><signal id="a10"/></pterm><pterm id="FB3_18_1"><signal id="ier"/><signal id="tc"/></pterm><pterm id="FB3_18_2"><signal id="slaveinten"/><signal id="spi_int" negated="ON"/></pterm><equation id="cpu_d5_SPECSIG"><d2><eq_pterm ptindx="FB3_2_1"/><eq_pterm ptindx="FB3_2_2"/><eq_pterm ptindx="FB3_2_3"/></d2><oe><eq_pterm ptindx="FB3_2_4"/></oe></equation><equation id="cpu_d6_SPECSIG"><d2><eq_pterm ptindx="FB3_5_1"/><eq_pterm ptindx="FB3_5_2"/></d2><oe><eq_pterm ptindx="FB3_5_3"/></oe></equation><equation id="cpu_d7_SPECSIG"><d2><eq_pterm ptindx="FB3_8_1"/><eq_pterm ptindx="FB3_8_2"/></d2><oe><eq_pterm ptindx="FB3_8_3"/></oe></equation><equation id="noe" negated="ON"><d2><eq_pterm ptindx="FB3_9_1"/><eq_pterm ptindx="FB3_9_2"/></d2></equation><equation id="ng"><d2><eq_pterm ptindx="FB3_15_1"/></d2></equation><equation id="add_decXLXN_11_SPECSIG" regUse="D" negated="ON"><d2><eq_pterm ptindx="FB3_17_1"/></d2><clk><fastsig signal="extclk"/></clk><prld ptindx="GND"/></equation><equation id="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"><d2><eq_pterm ptindx="FB3_18_1"/><eq_pterm ptindx="FB3_18_2"/></d2></equation></fblock><fblock id="FB4" pinUse="6" inputUse="34"><macrocell id="FB4_MC1" sigUse="6" signal="shiftdone"><pterms pt1="FB4_1_1" pt2="FB4_1_2" pt3="FB4_1_3"/></macrocell><macrocell id="FB4_MC2" pin="FB4_MC2_PIN25" sigUse="2" signal="b8"><pterms pt1="FB4_2_1"/></macrocell><macrocell id="FB4_MC3" sigUse="7" signal="start_shifting"><pterms pt1="FB4_3_1" pt2="FB4_3_2" pt3="FB4_3_3" pt4="FB4_3_4"/></macrocell><macrocell id="FB4_MC4" sigUse="7" signal="spidataout7_SPECSIG"><pterms pt1="FB4_4_1" pt2="FB4_4_2" pt3="FB4_4_3" pt4="FB4_4_4"/></macrocell><macrocell id="FB4_MC5" pin="FB4_MC5_PIN26" sigUse="2" signal="b9"><pterms pt1="FB4_5_1"/></macrocell><macrocell id="FB4_MC6" sigUse="7" signal="spidataout6_SPECSIG"><pterms pt1="FB4_6_1" pt2="FB4_6_2" pt3="FB4_6_3" pt4="FB4_6_4"/></macrocell><macrocell id="FB4_MC7" sigUse="7" signal="spidataout5_SPECSIG"><pterms pt1="FB4_7_1" pt2="FB4_7_2" pt3="FB4_7_3" pt4="FB4_7_4"/></macrocell><macrocell id="FB4_MC8" pin="FB4_MC8_PIN27" sigUse="2" signal="b10"><pterms pt1="FB4_8_1"/></macrocell><macrocell id="FB4_MC9" sigUse="7" signal="spidataout4_SPECSIG"><pterms pt1="FB4_9_1" pt2="FB4_9_2" pt3="FB4_9_3" pt4="FB4_9_4"/></macrocell><macrocell id="FB4_MC10" sigUse="5" signal="spidatain1_SPECSIG"><pterms pt1="FB4_10_1" pt2="FB4_10_2" pt3="FB4_10_3" pt4="FB4_10_4"/></macrocell><macrocell id="FB4_MC11" pin="FB4_MC11_PIN28" sigUse="7" signal="spi_Nsel"><pterms pt1="FB4_11_1" pt2="FB4_11_2" pt3="FB4_11_3" pt4="FB4_11_4" pt5="FB4_11_5"/></macrocell><macrocell id="FB4_MC12" sigUse="6" signal="spidatain0_SPECSIG"><pterms pt1="FB4_12_1" pt2="FB4_12_2" pt3="FB4_12_3" pt4="FB4_12_4"/></macrocell><macrocell id="FB4_MC13" sigUse="7" signal="shiftcnt3_SPECSIG"><pterms pt1="FB4_13_1" pt2="FB4_13_2" pt3="FB4_13_3" pt4="FB4_13_4"/></macrocell><macrocell id="FB4_MC14" pin="FB4_MC14_PIN29" sigUse="3" signal="led"><pterms pt1="FB4_14_1"/></macrocell><macrocell id="FB4_MC15" pin="FB4_MC15_PIN33" sigUse="6" signal="shiftcnt2_SPECSIG"><pterms pt1="FB4_15_1" pt2="FB4_15_2" pt3="FB4_15_3" pt4="FB4_15_4"/></macrocell><macrocell id="FB4_MC16" sigUse="5" signal="shiftcnt1_SPECSIG"><pterms pt1="FB4_16_1" pt2="FB4_16_2" pt3="FB4_16_3" pt4="FB4_16_4" pt5="FB4_16_5"/></macrocell><macrocell id="FB4_MC17" pin="FB4_MC17_PIN34" sigUse="7" signal="spi_sclk"><pterms pt1="FB4_17_1" pt2="FB4_17_2" pt3="FB4_17_3" pt4="FB4_17_4" pt5="FB4_17_5"/></macrocell><macrocell id="FB4_MC18" sigUse="7" signal="ier"><pterms pt1="FB4_18_1" pt2="FB4_18_2" pt3="FB4_18_3" pt4="FB4_18_4" pt5="FB4_18_5"/></macrocell><fbinput id="FB4_I1" signal="OpTxINV24__INT_SPECSIG"/><fbinput id="FB4_I2" fbk="PIN" signal="cpu_d0PIN_SPECSIG"/><fbinput id="FB4_I3" fbk="PIN" signal="cpu_d4PIN_SPECSIG"/><fbinput id="FB4_I4" fbk="PIN" signal="cpu_d5PIN_SPECSIG"/><fbinput id="FB4_I5" fbk="PIN" signal="cpu_d6PIN_SPECSIG"/><fbinput id="FB4_I6" fbk="PIN" signal="cpu_d7PIN_SPECSIG"/><fbinput id="FB4_I7" signal="Ncs2"/><fbinput id="FB4_I8" signal="a10"/><fbinput id="FB4_I9" signal="a8"/><fbinput id="FB4_I10" signal="a9"/><fbinput id="FB4_I11" signal="cpha"/><fbinput id="FB4_I12" signal="cpol"/><fbinput id="FB4_I13" signal="cpu_Nres"/><fbinput id="FB4_I14" signal="cpu_a0_SPECSIG"/><fbinput id="FB4_I15" signal="cpu_a1_SPECSIG"/><fbinput id="FB4_I16" signal="cpu_rnw"/><fbinput id="FB4_I17" signal="frx"/><fbinput id="FB4_I18" signal="ier"/><fbinput id="FB4_I19" signal="nio_sel"/><fbinput id="FB4_I20" signal="shiftcnt0_SPECSIG"/><fbinput id="FB4_I21" signal="shiftcnt1_SPECSIG"/><fbinput id="FB4_I22" signal="shiftcnt2_SPECSIG"/><fbinput id="FB4_I23" signal="shiftcnt3_SPECSIG"/><fbinput id="FB4_I24" signal="shiftdone"/><fbinput id="FB4_I25" signal="shifting2"/><fbinput id="FB4_I26" signal="spi_Nsel"/><fbinput id="FB4_I27" signal="spi_miso"/><fbinput id="FB4_I28" signal="spidatain0_SPECSIG"/><fbinput id="FB4_I29" signal="spidataout4_SPECSIG"/><fbinput id="FB4_I30" signal="spidataout5_SPECSIG"/><fbinput id="FB4_I31" signal="spidataout6_SPECSIG"/><fbinput id="FB4_I32" signal="spidataout7_SPECSIG"/><fbinput id="FB4_I33" signal="start_shifting"/><fbinput id="FB4_I34" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"/><pterm id="FB4_1_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/></pterm><pterm id="FB4_1_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_1_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_2_1"><signal id="a8"/><signal id="nio_sel"/></pterm><pterm id="FB4_3_1"><signal id="cpu_rnw" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_2"><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_3"><signal id="start_shiftingstart_shifting_RSTF__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_4"><signal id="Ncs2"/></pterm><pterm id="FB4_4_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout7_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d7PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_4_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout7_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d7PIN_SPECSIG"/></pterm><pterm id="FB4_4_3"><signal id="Ncs2"/></pterm><pterm id="FB4_4_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_5_1"><signal id="a9"/><signal id="nio_sel"/></pterm><pterm id="FB4_6_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout6_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d6PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_6_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout6_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d6PIN_SPECSIG"/></pterm><pterm id="FB4_6_3"><signal id="Ncs2"/></pterm><pterm id="FB4_6_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_7_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout5_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d5PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_7_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout5_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d5PIN_SPECSIG"/></pterm><pterm id="FB4_7_3"><signal id="Ncs2"/></pterm><pterm id="FB4_7_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_8_1"><signal id="a10"/><signal id="nio_sel"/></pterm><pterm id="FB4_9_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout4_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_9_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout4_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB4_9_3"><signal id="Ncs2"/></pterm><pterm id="FB4_9_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_10_1"><signal id="spidatain0_SPECSIG"/></pterm><pterm id="FB4_10_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_10_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_10_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB4_11_1"><signal id="spi_Nsel"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_11_2"><signal id="spi_Nsel" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB4_11_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_11_4"><signal id="Ncs2"/></pterm><pterm id="FB4_11_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_12_1"><signal id="spi_Nsel" negated="ON"/><signal id="spi_miso"/></pterm><pterm id="FB4_12_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_12_3"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_12_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB4_13_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB4_13_2"><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB4_13_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_13_4"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_14_1"><signal id="spi_Nsel"/><signal id="start_shifting" negated="ON"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB4_15_1"><signal id="shiftcnt2_SPECSIG"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB4_15_2"><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB4_15_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_15_4"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_16_1"><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB4_16_2"><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB4_16_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_16_4"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_16_5"><signal id="cpu_Nres"/><signal id="cpha"/><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB4_17_1"><signal id="cpol"/></pterm><pterm id="FB4_17_2"><signal id="cpu_Nres"/><signal id="cpha" negated="ON"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB4_17_3"><signal id="cpu_Nres" negated="ON"/><signal id="cpol" negated="ON"/></pterm><pterm id="FB4_17_4"><signal id="cpu_Nres" negated="ON"/><signal id="cpol"/></pterm><pterm id="FB4_17_5"><signal id="OpTxINV24__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_18_1"><signal id="ier"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d6PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_18_2"><signal id="ier" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d6PIN_SPECSIG"/></pterm><pterm id="FB4_18_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_18_4"><signal id="Ncs2"/></pterm><pterm id="FB4_18_5"><signal id="cpu_rnw" negated="ON"/></pterm><equation id="shiftdone" regUse="D"><d2><eq_pterm ptindx="FB4_1_1"/></d2><clk><eq_pterm ptindx="FB4_1_3"/></clk><reset><eq_pterm ptindx="FB4_1_2"/></reset><prld ptindx="GND"/></equation><equation id="b8"><d2><eq_pterm ptindx="FB4_2_1"/></d2></equation><equation id="start_shifting" regUse="T"><d2><eq_pterm ptindx="FB4_3_1"/><eq_pterm ptindx="FB4_3_2"/></d2><clk><eq_pterm ptindx="FB4_3_4"/></clk><reset><eq_pterm ptindx="FB4_3_3"/></reset><prld ptindx="GND"/></equation><equation id="spidataout7_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_4_1"/><eq_pterm ptindx="FB4_4_2"/></d2><clk><eq_pterm ptindx="FB4_4_3"/></clk><ce><eq_pterm ptindx="FB4_4_4"/></ce><prld ptindx="GND"/></equation><equation id="b9"><d2><eq_pterm ptindx="FB4_5_1"/></d2></equation><equation id="spidataout6_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_6_1"/><eq_pterm ptindx="FB4_6_2"/></d2><clk><eq_pterm ptindx="FB4_6_3"/></clk><ce><eq_pterm ptindx="FB4_6_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout5_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_7_1"/><eq_pterm ptindx="FB4_7_2"/></d2><clk><eq_pterm ptindx="FB4_7_3"/></clk><ce><eq_pterm ptindx="FB4_7_4"/></ce><prld ptindx="GND"/></equation><equation id="b10"><d2><eq_pterm ptindx="FB4_8_1"/></d2></equation><equation id="spidataout4_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_9_1"/><eq_pterm ptindx="FB4_9_2"/></d2><clk><eq_pterm ptindx="FB4_9_3"/></clk><ce><eq_pterm ptindx="FB4_9_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB4_10_1"/></d2><clk><eq_pterm ptindx="FB4_10_3"/></clk><reset><eq_pterm ptindx="FB4_10_2"/></reset><ce><eq_pterm ptindx="FB4_10_4"/></ce><prld ptindx="GND"/></equation><equation id="spi_Nsel" regUse="T"><d2><eq_pterm ptindx="FB4_11_1"/><eq_pterm ptindx="FB4_11_2"/></d2><clk><eq_pterm ptindx="FB4_11_4"/></clk><set><eq_pterm ptindx="FB4_11_3"/></set><ce><eq_pterm ptindx="FB4_11_5"/></ce><prld ptindx="GND"/></equation><equation id="spidatain0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB4_12_1"/></d2><clk><eq_pterm ptindx="FB4_12_3"/></clk><reset><eq_pterm ptindx="FB4_12_2"/></reset><ce><eq_pterm ptindx="FB4_12_4"/></ce><prld ptindx="GND"/></equation><equation id="shiftcnt3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_13_1"/><eq_pterm ptindx="FB4_13_2"/></d2><clk><eq_pterm ptindx="FB4_13_4"/></clk><reset><eq_pterm ptindx="FB4_13_3"/></reset><prld ptindx="GND"/></equation><equation id="led"><d2><eq_pterm ptindx="FB4_14_1"/></d2></equation><equation id="shiftcnt2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_15_1"/><eq_pterm ptindx="FB4_15_2"/></d2><clk><eq_pterm ptindx="FB4_15_4"/></clk><reset><eq_pterm ptindx="FB4_15_3"/></reset><prld ptindx="GND"/></equation><equation id="shiftcnt1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB4_16_1"/><eq_pterm ptindx="FB4_16_2"/></d2><clk><eq_pterm ptindx="FB4_16_4"/></clk><reset><eq_pterm ptindx="FB4_16_3"/></reset><prld ptindx="GND"/></equation><equation id="spi_sclk" regUse="D"><d1><eq_pterm ptindx="FB4_17_1"/></d1><d2><eq_pterm ptindx="FB4_17_2"/><eq_pterm import="1" ptindx="FB4_16_5"/></d2><clk><eq_pterm ptindx="FB4_17_5"/></clk><set><eq_pterm ptindx="FB4_17_4"/></set><reset><eq_pterm ptindx="FB4_17_3"/></reset><prld ptindx="GND"/></equation><equation id="ier" regUse="T"><d2><eq_pterm ptindx="FB4_18_1"/><eq_pterm ptindx="FB4_18_2"/></d2><clk><eq_pterm ptindx="FB4_18_4"/></clk><reset><eq_pterm ptindx="FB4_18_3"/></reset><ce><eq_pterm ptindx="FB4_18_5"/></ce><prld ptindx="GND"/></equation></fblock><vcc/><gnd/><compOpts loc="ON" part="xc9572xl-10-PC44" prld="LOW" slew="FAST" mlopt="ON" power="STD" gsropt="ON" gtsopt="ON" inputs="54" keepio="OFF" pterms="25" unused="FLOAT" exhaust="OFF" gclkopt="ON" wysiwyg="OFF" ignorets="OFF" optimize="SPEED" terminate="KEEPER"/><specSig value="cpu_d&lt;0&gt;.PIN" signal="cpu_d0PIN_SPECSIG"/><specSig value="cpu_a&lt;0&gt;" signal="cpu_a0_SPECSIG"/><specSig value="cpu_a&lt;1&gt;" signal="cpu_a1_SPECSIG"/><specSig value="cpu_d&lt;1&gt;.PIN" signal="cpu_d1PIN_SPECSIG"/><specSig value="cpu_d&lt;2&gt;.PIN" signal="cpu_d2PIN_SPECSIG"/><specSig value="cpu_d&lt;4&gt;.PIN" signal="cpu_d4PIN_SPECSIG"/><specSig value="cpu_d&lt;6&gt;.PIN" signal="cpu_d6PIN_SPECSIG"/><specSig value="cpu_d&lt;3&gt;.PIN" signal="cpu_d3PIN_SPECSIG"/><specSig value="cpu_d&lt;5&gt;.PIN" signal="cpu_d5PIN_SPECSIG"/><specSig value="cpu_d&lt;7&gt;.PIN" signal="cpu_d7PIN_SPECSIG"/><specSig value="(b)" signal="b_SPECSIG"/><specSig value="spidataout&lt;2&gt;" signal="spidataout2_SPECSIG"/><specSig value="I/O" signal="IO_SPECSIG"/><specSig value="cpu_d&lt;0&gt;" signal="cpu_d0_SPECSIG"/><specSig value="cpu_d&lt;1&gt;" signal="cpu_d1_SPECSIG"/><specSig value="cpu_d&lt;2&gt;" signal="cpu_d2_SPECSIG"/><specSig value="GCK/I" signal="GCKI_SPECSIG"/><specSig value="cpu_d&lt;3&gt;" signal="cpu_d3_SPECSIG"/><specSig value="cpu_d&lt;4&gt;" signal="cpu_d4_SPECSIG"/><specSig value="cpu_d&lt;5&gt;" signal="cpu_d5_SPECSIG"/><specSig value="cpu_d&lt;6&gt;" signal="cpu_d6_SPECSIG"/><specSig value="cpu_d&lt;7&gt;" signal="cpu_d7_SPECSIG"/><specSig value="shiftcnt&lt;2&gt;" signal="shiftcnt2_SPECSIG"/><specSig value="spidataout&lt;3&gt;" signal="spidataout3_SPECSIG"/><specSig value="spidataout&lt;1&gt;" signal="spidataout1_SPECSIG"/><specSig value="spidataout&lt;0&gt;" signal="spidataout0_SPECSIG"/><specSig value="divisor&lt;2&gt;" signal="divisor2_SPECSIG"/><specSig value="divisor&lt;1&gt;" signal="divisor1_SPECSIG"/><specSig value="divisor&lt;0&gt;" signal="divisor0_SPECSIG"/><specSig value="spidatain&lt;0&gt;" signal="spidatain0_SPECSIG"/><specSig value="spidatain&lt;1&gt;" signal="spidatain1_SPECSIG"/><specSig value="spidatain&lt;2&gt;" signal="spidatain2_SPECSIG"/><specSig value="spidatain&lt;3&gt;" signal="spidatain3_SPECSIG"/><specSig value="spidatain&lt;4&gt;" signal="spidatain4_SPECSIG"/><specSig value="shiftcnt&lt;0&gt;" signal="shiftcnt0_SPECSIG"/><specSig value="$OpTx$INV$24__$INT" signal="OpTxINV24__INT_SPECSIG"/><specSig value="spidatain&lt;7&gt;" signal="spidatain7_SPECSIG"/><specSig value="spidatain&lt;6&gt;" signal="spidatain6_SPECSIG"/><specSig value="spidatain&lt;5&gt;" signal="spidatain5_SPECSIG"/><specSig value="start_shifting/start_shifting_RSTF__$INT" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"/><specSig value="cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/><specSig value="shiftcnt&lt;1&gt;" signal="shiftcnt1_SPECSIG"/><specSig value="shiftcnt&lt;3&gt;" signal="shiftcnt3_SPECSIG"/><specSig value="spidataout&lt;4&gt;" signal="spidataout4_SPECSIG"/><specSig value="spidataout&lt;5&gt;" signal="spidataout5_SPECSIG"/><specSig value="spidataout&lt;6&gt;" signal="spidataout6_SPECSIG"/><specSig value="spidataout&lt;7&gt;" signal="spidataout7_SPECSIG"/><specSig value="add_dec/XLXN_11" signal="add_decXLXN_11_SPECSIG"/></document>
diff --git a/spi6502b_pad.csv b/spi6502b_pad.csv
index 84e7d04..a1a112e 100644
--- a/spi6502b_pad.csv
+++ b/spi6502b_pad.csv
@@ -1,7 +1,7 @@
 Release 6.1i - Fit G.38
 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
 
- 5- 6-2017  5:47PM
+ 5-11-2017  2:09AM
 
 NOTE: This file is designed to be imported into a spreadsheet program
 such as Microsoft Excel for viewing, printing and sorting. The comma ','
@@ -23,7 +23,7 @@ P2,cpu_d<0>,I/O,I/O,BIDIR,,,,,,,,,
 P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,,
 P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,,
 P5,cpu_Nphi2,I,I/O/GCK1,INPUT,,,,,,,,,
-P6,extclk,I,I/O/GCK2,INPUT,,,,,,,,,
+P6,extclk,GCK/I,I/O/GCK2,,,,,,,,,,
 P7,cpu_rnw,I,I/O/GCK3,INPUT,,,,,,,,,
 P8,cpu_d<3>,I/O,I/O,BIDIR,,,,,,,,,
 P9,cpu_d<4>,I/O,I/O,BIDIR,,,,,,,,,
@@ -31,20 +31,20 @@ P10,GND,,GND,,,,,,,,,,
 P11,cpu_d<5>,I/O,I/O,BIDIR,,,,,,,,,
 P12,cpu_d<6>,I/O,I/O,BIDIR,,,,,,,,,
 P13,cpu_d<7>,I/O,I/O,BIDIR,,,,,,,,,
-P14,cpu_Nirq,O,I/O,OUTPUT,,,,,,,,,
+P14,noe,O,I/O,OUTPUT,,,,,,,,,
 P15,TDI,,TDI,,,,,,,,,,
 P16,TMS,,TMS,,,,,,,,,,
 P17,TCK,,TCK,,,,,,,,,,
 P18,Ncs2,I,I/O,INPUT,,,,,,,,,
 P19,cpu_Nres,I,I/O,INPUT,,,,,,,,,
-P20,cs1,I,I/O,INPUT,,,,,,,,,
+P20,ng,O,I/O,OUTPUT,,,,,,,,,
 P21,VCC,,VCCINT,,,,,,,,,,
 P22,cpu_a<0>,I,I/O,INPUT,,,,,,,,,
 P23,GND,,GND,,,,,,,,,,
 P24,cpu_a<1>,I,I/O,INPUT,,,,,,,,,
-P25,TIE,,I/O,,,,,,,,,,
-P26,TIE,,I/O,,,,,,,,,,
-P27,TIE,,I/O,,,,,,,,,,
+P25,b8,O,I/O,OUTPUT,,,,,,,,,
+P26,b9,O,I/O,OUTPUT,,,,,,,,,
+P27,b10,O,I/O,OUTPUT,,,,,,,,,
 P28,spi_Nsel,O,I/O,OUTPUT,,,,,,,,,
 P29,led,O,I/O,OUTPUT,,,,,,,,,
 P30,TDO,,TDO,,,,,,,,,,
@@ -53,14 +53,14 @@ P32,VCC,,VCCIO,,,,,,,,,,
 P33,TIE,,I/O,,,,,,,,,,
 P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,,
 P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,,
-P36,TIE,,I/O,,,,,,,,,,
-P37,TIE,,I/O,,,,,,,,,,
-P38,TIE,,I/O,,,,,,,,,,
-P39,TIE,,I/O/GSR,,,,,,,,,,
-P40,TIE,,I/O/GTS2,,,,,,,,,,
+P36,a8,I,I/O,INPUT,,,,,,,,,
+P37,a9,I,I/O,INPUT,,,,,,,,,
+P38,a10,I,I/O,INPUT,,,,,,,,,
+P39,cpu_Nirq,O,I/O/GSR,OUTPUT,,,,,,,,,
+P40,nio_sel,I,I/O/GTS2,INPUT,,,,,,,,,
 P41,VCC,,VCCINT,,,,,,,,,,
 P42,spi_int,I,I/O/GTS1,INPUT,,,,,,,,,
-P43,TIE,,I/O,,,,,,,,,,
+P43,nio_stb,I,I/O,INPUT,,,,,,,,,
 P44,spi_miso,I,I/O,INPUT,,,,,,,,,
 
 To preserve the pinout above for future design iterations in