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add bmm and testbench

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This commit is contained in:
Stefan 2016-01-06 21:59:21 +01:00
parent ab6aefb99a
commit e8b646bcbd
4 changed files with 232 additions and 51 deletions
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52
Apple2.xise
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@ -35,12 +35,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="src/timing_testbench.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="src/vga_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
@ -65,69 +59,75 @@
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="src/cpu_hexy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="src/disk_disp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="src/grp_debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="build/apple_II_auto_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="src/keyboard_apple.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="src/PS2/Debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="src/PS2/Keyboard.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="src/PS2/KeyboardMapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="src/PS2/PS2Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="src/apple2_top_papilio_duo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="src/dcm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="build/bios_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="src/cpu/t65/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="src/cpu/t65/T65_MCode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="src/cpu/t65/T65_Pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="src/cpu/t65/T65.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="src/timing_tb2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="94"/>
</file>
</files>
<properties>
@ -371,8 +371,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/timing_testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.timing_testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/timing_tb2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.timing_tb2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -390,7 +390,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.timing_testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.timing_tb2" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -440,7 +440,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|timing_testbench|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|timing_tb2|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="Apple2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

47
src/apple2.bmm Normal file
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@ -0,0 +1,47 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_apple RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/roms/Mram_ROM1 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM2 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM3 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM4 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM5 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM6 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM7 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM8 [7:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
ADDRESS_SPACE rom_disk RAMB16 [0x00000000:0x000007ff]
BUS_BLOCK
disk/rom/Mram_ROM [7:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

159
src/timing_tb2.vhd Normal file
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@ -0,0 +1,159 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:41:31 01/06/2016
-- Design Name:
-- Module Name: /home/mandl/Entwicklung/Apple2/timing_tb2.vhd
-- Project Name: Apple2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: timing_generator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY timing_tb2 IS
END timing_tb2;
ARCHITECTURE behavior OF timing_tb2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT timing_generator
PORT(
CLK_14M : IN std_logic;
CLK_7M_out : OUT std_logic;
Q3_out : OUT std_logic;
RAS_N_out : OUT std_logic;
CAS_N_out : OUT std_logic;
AX_out : OUT std_logic;
PHI0_out : OUT std_logic;
PRE_PHI0_out : OUT std_logic;
COLOR_REF_out : OUT std_logic;
TEXT_MODE : IN std_logic;
PAGE2 : IN std_logic;
HIRES : IN std_logic;
VIDEO_ADDRESS : OUT unsigned(15 downto 0);
H0 : OUT std_logic;
VA : OUT std_logic;
VB : OUT std_logic;
VC : OUT std_logic;
V2 : OUT std_logic;
V4 : OUT std_logic;
HBL_out : OUT std_logic;
VBL_out : OUT std_logic;
BLANK : OUT std_logic;
LDPS_N : OUT std_logic;
LD194 : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK_14M : std_logic := '0';
signal TEXT_MODE : std_logic := '0';
signal PAGE2 : std_logic := '0';
signal HIRES : std_logic := '0';
--Outputs
signal CLK_7M_out : std_logic;
signal Q3_out : std_logic;
signal RAS_N_out : std_logic;
signal CAS_N_out : std_logic;
signal AX_out : std_logic;
signal PHI0_out : std_logic;
signal PRE_PHI0_out : std_logic;
signal COLOR_REF_out : std_logic;
signal VIDEO_ADDRESS : std_logic_vector(15 downto 0);
signal H0 : std_logic;
signal VA : std_logic;
signal VB : std_logic;
signal VC : std_logic;
signal V2 : std_logic;
signal V4 : std_logic;
signal HBL_out : std_logic;
signal VBL_out : std_logic;
signal BLANK : std_logic;
signal LDPS_N : std_logic;
signal LD194 : std_logic;
-- Clock period definitions
constant CLK_14M_period : time := 71.42 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: timing_generator PORT MAP (
CLK_14M => CLK_14M,
CLK_7M_out => CLK_7M_out,
Q3_out => Q3_out,
RAS_N_out => RAS_N_out,
CAS_N_out => CAS_N_out,
AX_out => AX_out,
PHI0_out => PHI0_out,
PRE_PHI0_out => PRE_PHI0_out,
COLOR_REF_out => COLOR_REF_out,
TEXT_MODE => TEXT_MODE,
PAGE2 => PAGE2,
HIRES => HIRES,
std_logic_vector(VIDEO_ADDRESS) => VIDEO_ADDRESS,
H0 => H0,
VA => VA,
VB => VB,
VC => VC,
V2 => V2,
V4 => V4,
HBL_out => HBL_out,
VBL_out => VBL_out,
BLANK => BLANK,
LDPS_N => LDPS_N,
LD194 => LD194
);
-- Clock process definitions
CLK_14M_process :process
begin
CLK_14M <= '0';
wait for CLK_14M_period/2;
CLK_14M <= '1';
wait for CLK_14M_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_14M_period*10;
-- insert stimulus here
wait;
end process;
END;

25
src/timing_testbench.vhd
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@ -1,25 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timing_testbench is
end timing_testbench;
architecture behavioral of timing_testbench is
signal CLK_14M : std_logic := '0';
begin
uut : entity work.timing_generator
port map (
CLK_14M => CLK_14M,
TEXT_MODE => '1',
PAGE2 => '0',
HIRES => '1'
);
CLK_14M <= not CLK_14M after 34.920639355 ns;
end behavioral;