GR8RAM/cpld/output_files/GR8RAM.jdi

<sld_project_info>
  <project>
    <hash md5_digest_80b="c391878a634f7d9b75fb"/>
  </project>
  <file_info>
    <file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>
  </file_info>
</sld_project_info>
CPLD firmware compiles 2019-09-01 02:55:04 +00:00			`<sld_project_info>`
			`<project>`
Made AddrH high bit variable with mode input 2019-09-08 01:16:23 +00:00			`<hash md5_digest_80b="c391878a634f7d9b75fb"/>`
CPLD firmware compiles 2019-09-01 02:55:04 +00:00			`</project>`
			`<file_info>`
			`<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>`
			`</file_info>`
			`</sld_project_info>`