GR8RAM/cpld/output_files/GR8RAM.map.summary

Analysis & Synthesis Status : Successful - Sat Sep 07 21:15:31 2019
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX7000S
Total macrocells : 103
Total pins : 61
Made AddrH high bit variable with mode input 2019-09-08 01:16:23 +00:00			`Analysis & Synthesis Status : Successful - Sat Sep 07 21:15:31 2019`
Clarified assignments 2019-09-06 21:26:42 +00:00			`Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition`
CPLD firmware compiles 2019-09-01 02:55:04 +00:00			`Revision Name : GR8RAM`
			`Top-level Entity Name : GR8RAM`
			`Family : MAX7000S`
Pipelined addition 2019-09-05 01:45:56 +00:00			`Total macrocells : 103`
			`Total pins : 61`