2019-09-01 02:55:04 +00:00
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Fitter report for GR8RAM
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2019-09-02 01:18:44 +00:00
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Sun Sep 01 20:44:15 2019
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Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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2019-09-01 02:55:04 +00:00
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Fitter Summary
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3. Fitter Settings
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2019-09-02 01:18:44 +00:00
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4. Parallel Compilation
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5. Pin-Out File
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6. Fitter Resource Usage Summary
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7. Input Pins
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8. Output Pins
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9. Bidir Pins
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10. All Package Pins
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11. I/O Standard
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12. Dedicated Inputs I/O
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13. Output Pin Default Load For Reported TCO
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14. Fitter Resource Utilization by Entity
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15. Control Signals
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16. Global & Other Fast Signals
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17. Non-Global High Fan-Out Signals
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18. Other Routing Usage Summary
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19. LAB External Interconnect
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20. LAB Macrocells
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21. Shareable Expander
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22. Logic Cell Interconnection
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23. Fitter Device Options
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24. Fitter Messages
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2019-09-01 02:55:04 +00:00
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+-----------------------------------------------------------------------------+
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; Fitter Summary ;
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+---------------------------+-------------------------------------------------+
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2019-09-02 01:18:44 +00:00
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; Fitter Status ; Successful - Sun Sep 01 20:44:15 2019 ;
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; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
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2019-09-01 02:55:04 +00:00
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; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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; Family ; MAX7000S ;
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; Device ; EPM7128SLC84-15 ;
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; Timing Models ; Final ;
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2019-09-02 01:18:44 +00:00
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; Total macrocells ; 102 / 128 ( 80 % ) ;
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2019-09-01 02:55:04 +00:00
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; Total pins ; 67 / 68 ( 99 % ) ;
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+---------------------------+-------------------------------------------------+
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+--------------------------------------------------------------------------------------------------------------------+
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; Fitter Settings ;
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+----------------------------------------------------------------------------+-----------------------+---------------+
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; Option ; Setting ; Default Value ;
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+----------------------------------------------------------------------------+-----------------------+---------------+
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; Device ; EPM7128SLC84-15 ; ;
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; Optimize Timing for ECOs ; On ; Off ;
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; Regenerate full fit report during ECO compiles ; On ; Off ;
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; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;
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; Slow Slew Rate ; On ; Off ;
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; Fitter Effort ; Standard Fit ; Auto Fit ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Optimize Multi-Corner Timing ; Off ; Off ;
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; Fitter Initial Placement Seed ; 1 ; 1 ;
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; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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+----------------------------------------------------------------------------+-----------------------+---------------+
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2019-09-02 01:18:44 +00:00
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Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
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+-------------------------------------+
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; Parallel Compilation ;
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+----------------------------+--------+
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; Processors ; Number ;
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+----------------------------+--------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 1 ;
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+----------------------------+--------+
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2019-09-01 02:55:04 +00:00
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+--------------+
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; Pin-Out File ;
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+--------------+
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2019-09-02 01:18:44 +00:00
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The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin.
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+---------------------------------------------------+
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; Fitter Resource Usage Summary ;
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+------------------------------+--------------------+
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; Resource ; Usage ;
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+------------------------------+--------------------+
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; Logic cells ; 102 / 128 ( 80 % ) ;
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; Registers ; 50 / 128 ( 39 % ) ;
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; Number of pterms used ; 250 ;
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; I/O pins ; 67 / 68 ( 99 % ) ;
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; -- Clock pins ; 2 / 2 ( 100 % ) ;
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; -- Dedicated input pins ; 2 / 2 ( 100 % ) ;
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; ; ;
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; Global signals ; 2 ;
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; Shareable expanders ; 5 / 128 ( 4 % ) ;
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; Parallel expanders ; 0 / 120 ( 0 % ) ;
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; Cells using turbo bit ; 41 / 128 ( 32 % ) ;
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; Maximum fan-out ; 50 ;
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; Highest non-global fan-out ; 48 ;
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; Total fan-out ; 993 ;
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; Average fan-out ; 5.71 ;
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+------------------------------+--------------------+
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2019-09-01 02:55:04 +00:00
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+-----------------------------------------------------------------------------------------------------------------------------------------------+
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; Input Pins ;
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+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
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; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ;
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+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
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2019-09-02 01:18:44 +00:00
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; A[0] ; 75 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ;
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2019-09-01 02:55:04 +00:00
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; A[10] ; 11 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
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2019-09-02 01:18:44 +00:00
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; A[11] ; 12 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
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; A[12] ; 15 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ;
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; A[13] ; 16 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ;
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; A[14] ; 17 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ;
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; A[15] ; 18 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ;
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; A[1] ; 76 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ;
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; A[2] ; 77 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ;
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; A[3] ; 79 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ;
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2019-09-01 02:55:04 +00:00
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; A[4] ; 80 ; -- ; 8 ; 1 ; 0 ; no ; no ; TTL ; User ;
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; A[5] ; 81 ; -- ; 8 ; 1 ; 0 ; no ; no ; TTL ; User ;
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; A[6] ; 4 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
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; A[7] ; 5 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
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; A[8] ; 9 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
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; A[9] ; 10 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
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2019-09-02 01:18:44 +00:00
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; C7M ; 83 ; -- ; -- ; 48 ; 0 ; yes ; no ; TTL ; User ;
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2019-09-01 02:55:04 +00:00
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; C7M_2 ; 84 ; -- ; -- ; 3 ; 0 ; no ; no ; TTL ; User ;
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2019-09-02 01:18:44 +00:00
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; MODE ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
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2019-09-01 02:55:04 +00:00
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; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
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; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
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; Q3 ; 6 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
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2019-09-02 01:18:44 +00:00
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; nDEVSEL ; 21 ; -- ; 2 ; 18 ; 0 ; no ; no ; TTL ; User ;
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; nIOSEL ; 74 ; -- ; 8 ; 13 ; 0 ; no ; no ; TTL ; User ;
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; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ;
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2019-09-01 02:55:04 +00:00
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; nRES ; 1 ; -- ; -- ; 50 ; 0 ; yes ; no ; TTL ; User ;
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2019-09-02 01:18:44 +00:00
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; nWE ; 20 ; -- ; 2 ; 11 ; 0 ; no ; no ; TTL ; User ;
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2019-09-01 02:55:04 +00:00
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+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Output Pins ;
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+---------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
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; Name ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
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+---------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
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; C7Mout ; 31 ; -- ; 3 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; PHI1out ; 30 ; -- ; 3 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[0] ; 52 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[10] ; 48 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[1] ; 54 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[2] ; 50 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[3] ; 49 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[4] ; 55 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[5] ; 51 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[6] ; 57 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[7] ; 56 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[8] ; 58 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; RA[9] ; 46 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; nCAS0 ; 39 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; nCAS1 ; 40 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; nINH ; 22 ; -- ; 2 ; no ; yes ; yes ; no ; TTL ; User ; 10 pF ; - ; - ;
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; nRAS ; 60 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; nRCS ; 41 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; nROE ; 45 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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; nRWE ; 67 ; -- ; 7 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
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+---------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Bidir Pins ;
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+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+
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; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Slow Slew Rate ; Open Drain ; I/O Standard ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
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+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+
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; D[0] ; 36 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
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; D[1] ; 35 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
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; D[2] ; 34 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
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; D[3] ; 33 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
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; D[4] ; 29 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
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; D[5] ; 28 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
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; D[6] ; 27 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
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; D[7] ; 25 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
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; RD[0] ; 73 ; -- ; 8 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
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; RD[1] ; 70 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
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; RD[2] ; 69 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
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; RD[3] ; 68 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
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; RD[4] ; 65 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
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; RD[5] ; 63 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
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; RD[6] ; 64 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
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; RD[7] ; 61 ; -- ; 6 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
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2019-09-01 02:55:04 +00:00
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+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+
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+-------------------------------------------------------------------------------------------------------+
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; All Package Pins ;
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+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
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; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; User Assignment ;
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+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
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; 1 ; 0 ; -- ; nRES ; input ; TTL ; ; Y ;
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; 2 ; 1 ; -- ; PHI1in ; input ; TTL ; ; Y ;
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; 3 ; 2 ; -- ; VCCINT ; power ; ; 5.0V ; ;
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; 4 ; 3 ; -- ; A[6] ; input ; TTL ; ; Y ;
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; 5 ; 4 ; -- ; A[7] ; input ; TTL ; ; Y ;
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; 6 ; 5 ; -- ; Q3 ; input ; TTL ; ; Y ;
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; 7 ; 6 ; -- ; GND ; gnd ; ; ; ;
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; 8 ; 7 ; -- ; PHI0in ; input ; TTL ; ; Y ;
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; 9 ; 8 ; -- ; A[8] ; input ; TTL ; ; Y ;
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; 10 ; 9 ; -- ; A[9] ; input ; TTL ; ; Y ;
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; 11 ; 10 ; -- ; A[10] ; input ; TTL ; ; Y ;
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; 12 ; 11 ; -- ; A[11] ; input ; TTL ; ; Y ;
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; 13 ; 12 ; -- ; VCCIO ; power ; ; 5.0V ; ;
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; 14 ; 13 ; -- ; TDI ; input ; TTL ; ; N ;
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; 15 ; 14 ; -- ; A[12] ; input ; TTL ; ; Y ;
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; 16 ; 15 ; -- ; A[13] ; input ; TTL ; ; Y ;
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; 17 ; 16 ; -- ; A[14] ; input ; TTL ; ; Y ;
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|
; 18 ; 17 ; -- ; A[15] ; input ; TTL ; ; Y ;
|
|
|
|
|
; 19 ; 18 ; -- ; GND ; gnd ; ; ; ;
|
|
|
|
|
; 20 ; 19 ; -- ; nWE ; input ; TTL ; ; Y ;
|
|
|
|
|
; 21 ; 20 ; -- ; nDEVSEL ; input ; TTL ; ; Y ;
|
|
|
|
|
; 22 ; 21 ; -- ; nINH ; output ; TTL ; ; Y ;
|
|
|
|
|
; 23 ; 22 ; -- ; TMS ; input ; TTL ; ; N ;
|
|
|
|
|
; 24 ; 23 ; -- ; nIOSTRB ; input ; TTL ; ; Y ;
|
|
|
|
|
; 25 ; 24 ; -- ; D[7] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 26 ; 25 ; -- ; VCCIO ; power ; ; 5.0V ; ;
|
|
|
|
|
; 27 ; 26 ; -- ; D[6] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 28 ; 27 ; -- ; D[5] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 29 ; 28 ; -- ; D[4] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 30 ; 29 ; -- ; PHI1out ; output ; TTL ; ; Y ;
|
|
|
|
|
; 31 ; 30 ; -- ; C7Mout ; output ; TTL ; ; Y ;
|
|
|
|
|
; 32 ; 31 ; -- ; GND ; gnd ; ; ; ;
|
|
|
|
|
; 33 ; 32 ; -- ; D[3] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 34 ; 33 ; -- ; D[2] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 35 ; 34 ; -- ; D[1] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 36 ; 35 ; -- ; D[0] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 37 ; 36 ; -- ; RESERVED ; ; ; ; ;
|
|
|
|
|
; 38 ; 37 ; -- ; VCCIO ; power ; ; 5.0V ; ;
|
|
|
|
|
; 39 ; 38 ; -- ; nCAS0 ; output ; TTL ; ; Y ;
|
|
|
|
|
; 40 ; 39 ; -- ; nCAS1 ; output ; TTL ; ; Y ;
|
|
|
|
|
; 41 ; 40 ; -- ; nRCS ; output ; TTL ; ; Y ;
|
|
|
|
|
; 42 ; 41 ; -- ; GND ; gnd ; ; ; ;
|
|
|
|
|
; 43 ; 42 ; -- ; VCCINT ; power ; ; 5.0V ; ;
|
|
|
|
|
; 44 ; 43 ; -- ; MODE ; input ; TTL ; ; Y ;
|
|
|
|
|
; 45 ; 44 ; -- ; nROE ; output ; TTL ; ; Y ;
|
|
|
|
|
; 46 ; 45 ; -- ; RA[9] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 47 ; 46 ; -- ; GND ; gnd ; ; ; ;
|
|
|
|
|
; 48 ; 47 ; -- ; RA[10] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 49 ; 48 ; -- ; RA[3] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 50 ; 49 ; -- ; RA[2] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 51 ; 50 ; -- ; RA[5] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 52 ; 51 ; -- ; RA[0] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 53 ; 52 ; -- ; VCCIO ; power ; ; 5.0V ; ;
|
|
|
|
|
; 54 ; 53 ; -- ; RA[1] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 55 ; 54 ; -- ; RA[4] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 56 ; 55 ; -- ; RA[7] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 57 ; 56 ; -- ; RA[6] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 58 ; 57 ; -- ; RA[8] ; output ; TTL ; ; Y ;
|
|
|
|
|
; 59 ; 58 ; -- ; GND ; gnd ; ; ; ;
|
|
|
|
|
; 60 ; 59 ; -- ; nRAS ; output ; TTL ; ; Y ;
|
|
|
|
|
; 61 ; 60 ; -- ; RD[7] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 62 ; 61 ; -- ; TCK ; input ; TTL ; ; N ;
|
|
|
|
|
; 63 ; 62 ; -- ; RD[5] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 64 ; 63 ; -- ; RD[6] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 65 ; 64 ; -- ; RD[4] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 66 ; 65 ; -- ; VCCIO ; power ; ; 5.0V ; ;
|
|
|
|
|
; 67 ; 66 ; -- ; nRWE ; output ; TTL ; ; Y ;
|
|
|
|
|
; 68 ; 67 ; -- ; RD[3] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 69 ; 68 ; -- ; RD[2] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 70 ; 69 ; -- ; RD[1] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 71 ; 70 ; -- ; TDO ; output ; TTL ; ; N ;
|
|
|
|
|
; 72 ; 71 ; -- ; GND ; gnd ; ; ; ;
|
|
|
|
|
; 73 ; 72 ; -- ; RD[0] ; bidir ; TTL ; ; Y ;
|
|
|
|
|
; 74 ; 73 ; -- ; nIOSEL ; input ; TTL ; ; Y ;
|
|
|
|
|
; 75 ; 74 ; -- ; A[0] ; input ; TTL ; ; Y ;
|
|
|
|
|
; 76 ; 75 ; -- ; A[1] ; input ; TTL ; ; Y ;
|
|
|
|
|
; 77 ; 76 ; -- ; A[2] ; input ; TTL ; ; Y ;
|
|
|
|
|
; 78 ; 77 ; -- ; VCCIO ; power ; ; 5.0V ; ;
|
|
|
|
|
; 79 ; 78 ; -- ; A[3] ; input ; TTL ; ; Y ;
|
|
|
|
|
; 80 ; 79 ; -- ; A[4] ; input ; TTL ; ; Y ;
|
|
|
|
|
; 81 ; 80 ; -- ; A[5] ; input ; TTL ; ; Y ;
|
|
|
|
|
; 82 ; 81 ; -- ; GND ; gnd ; ; ; ;
|
|
|
|
|
; 83 ; 82 ; -- ; C7M ; input ; TTL ; ; Y ;
|
|
|
|
|
; 84 ; 83 ; -- ; C7M_2 ; input ; TTL ; ; Y ;
|
|
|
|
|
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
|
|
|
|
|
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------+
|
|
|
|
|
; I/O Standard ;
|
|
|
|
|
+--------------+------------+----------------------+-------------------+-------------------+-------+
|
|
|
|
|
; I/O Standard ; Input Vref ; Dedicated Input Pins ; Pins in I/O Bank1 ; Pins in I/O Bank2 ; Total ;
|
|
|
|
|
+--------------+------------+----------------------+-------------------+-------------------+-------+
|
|
|
|
|
; TTL ; - ; 4 ; 0 ; 0 ; 4 ;
|
|
|
|
|
+--------------+------------+----------------------+-------------------+-------------------+-------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------+
|
|
|
|
|
; Dedicated Inputs I/O ;
|
|
|
|
|
+--------+-------+-------+-------+--------------+------------+---------+
|
|
|
|
|
; Name ; Pin # ; Type ; VCCIO ; I/O Standard ; Input Vref ; Current ;
|
|
|
|
|
+--------+-------+-------+-------+--------------+------------+---------+
|
|
|
|
|
; C7M ; 83 ; Input ; -- ; TTL ; - ; 0 mA ;
|
|
|
|
|
; C7M_2 ; 84 ; Input ; -- ; TTL ; - ; 0 mA ;
|
|
|
|
|
; PHI1in ; 2 ; Input ; -- ; TTL ; - ; 0 mA ;
|
|
|
|
|
; nRES ; 1 ; Input ; -- ; TTL ; - ; 0 mA ;
|
|
|
|
|
+--------+-------+-------+-------+--------------+------------+---------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----------------------------------------------+
|
|
|
|
|
; Output Pin Default Load For Reported TCO ;
|
|
|
|
|
+--------------+-------+------------------------+
|
|
|
|
|
; I/O Standard ; Load ; Termination Resistance ;
|
|
|
|
|
+--------------+-------+------------------------+
|
|
|
|
|
; 3.3-V LVTTL ; 10 pF ; Not Available ;
|
|
|
|
|
; 3.3-V LVCMOS ; 10 pF ; Not Available ;
|
|
|
|
|
; TTL ; 10 pF ; Not Available ;
|
|
|
|
|
+--------------+-------+------------------------+
|
|
|
|
|
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------+
|
|
|
|
|
; Fitter Resource Utilization by Entity ;
|
|
|
|
|
+----------------------------+------------+------+-------------------------------+--------------+
|
|
|
|
|
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
|
|
|
|
|
+----------------------------+------------+------+-------------------------------+--------------+
|
2019-09-02 01:18:44 +00:00
|
|
|
; |GR8RAM ; 102 ; 67 ; |GR8RAM ; work ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
|
|
|
|
|
+----------------------------+------------+------+-------------------------------+--------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------+
|
|
|
|
|
; Control Signals ;
|
|
|
|
|
+-----------+----------+---------+--------------+--------+----------------------+------------------+
|
|
|
|
|
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
|
|
|
|
+-----------+----------+---------+--------------+--------+----------------------+------------------+
|
2019-09-02 01:18:44 +00:00
|
|
|
; A[0] ; PIN_75 ; 15 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; BankWR_MC ; LC111 ; 8 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; C7M ; PIN_83 ; 48 ; Clock ; yes ; On ; -- ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; C7M_2 ; PIN_84 ; 3 ; Clock ; no ; -- ; -- ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; PHI1b9_MC ; LC37 ; 6 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; RAMSELreg ; LC34 ; 24 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; REGEN ; LC41 ; 7 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; S[0] ; LC113 ; 46 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; S[1] ; LC117 ; 47 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; S[2] ; LC122 ; 48 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; nDEVSEL ; PIN_21 ; 18 ; Clock enable ; no ; -- ; -- ;
|
|
|
|
|
; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; nRES ; PIN_1 ; 50 ; Async. clear ; yes ; On ; -- ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; nWE ; PIN_20 ; 11 ; Clock enable ; no ; -- ; -- ;
|
2019-09-01 02:55:04 +00:00
|
|
|
+-----------+----------+---------+--------------+--------+----------------------+------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+---------------------------------------------------------------------+
|
|
|
|
|
; Global & Other Fast Signals ;
|
|
|
|
|
+------+----------+---------+----------------------+------------------+
|
|
|
|
|
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
|
|
|
|
+------+----------+---------+----------------------+------------------+
|
2019-09-02 01:18:44 +00:00
|
|
|
; C7M ; PIN_83 ; 48 ; On ; -- ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; nRES ; PIN_1 ; 50 ; On ; -- ;
|
|
|
|
|
+------+----------+---------+----------------------+------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----------------------------------------+
|
|
|
|
|
; Non-Global High Fan-Out Signals ;
|
|
|
|
|
+-------------------------------+---------+
|
|
|
|
|
; Name ; Fan-Out ;
|
|
|
|
|
+-------------------------------+---------+
|
2019-09-02 01:18:44 +00:00
|
|
|
; S[2] ; 48 ;
|
|
|
|
|
; S[1] ; 47 ;
|
|
|
|
|
; S[0] ; 46 ;
|
|
|
|
|
; Addr[0] ; 25 ;
|
|
|
|
|
; Addr[1] ; 24 ;
|
|
|
|
|
; RAMSELreg ; 24 ;
|
|
|
|
|
; Addr[2] ; 23 ;
|
|
|
|
|
; Addr[3] ; 22 ;
|
|
|
|
|
; Addr[4] ; 21 ;
|
|
|
|
|
; Addr[5] ; 20 ;
|
|
|
|
|
; Addr[6] ; 19 ;
|
|
|
|
|
; nDEVSEL ; 18 ;
|
|
|
|
|
; Addr[7] ; 18 ;
|
|
|
|
|
; Addr[8] ; 17 ;
|
|
|
|
|
; Addr[9] ; 16 ;
|
|
|
|
|
; A[3] ; 15 ;
|
|
|
|
|
; A[2] ; 15 ;
|
|
|
|
|
; A[1] ; 15 ;
|
|
|
|
|
; A[0] ; 15 ;
|
|
|
|
|
; Addr[10] ; 15 ;
|
|
|
|
|
; Addr[11] ; 14 ;
|
|
|
|
|
; nIOSEL ; 13 ;
|
|
|
|
|
; Addr[12] ; 13 ;
|
|
|
|
|
; Bank[0] ; 13 ;
|
|
|
|
|
; nIOSTRB ; 12 ;
|
|
|
|
|
; Addr[13] ; 12 ;
|
|
|
|
|
; Bank[1] ; 12 ;
|
|
|
|
|
; nWE ; 11 ;
|
|
|
|
|
; Addr[14] ; 11 ;
|
|
|
|
|
; Bank[2] ; 11 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; ASel ; 11 ;
|
|
|
|
|
; Addr[15] ; 10 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; Bank[3] ; 9 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; Addr[16] ; 9 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; IOBank0 ; 8 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; Addr[17] ; 8 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; BankWR_MC ; 8 ;
|
|
|
|
|
; AddrLWR_MC ; 8 ;
|
|
|
|
|
; AddrMWR_MC ; 8 ;
|
|
|
|
|
; RDOE~1 ; 8 ;
|
|
|
|
|
; DOE~5 ; 8 ;
|
|
|
|
|
; Bank[4] ; 7 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; Addr[18] ; 7 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; REGEN ; 7 ;
|
|
|
|
|
; D[3]~3 ; 6 ;
|
|
|
|
|
; D[2]~2 ; 6 ;
|
|
|
|
|
; D[1]~1 ; 6 ;
|
|
|
|
|
; D[0]~0 ; 6 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; Addr[19] ; 6 ;
|
|
|
|
|
; lpm_counter:Ref_rtl_0|dffs[3] ; 6 ;
|
|
|
|
|
; lpm_counter:Ref_rtl_0|dffs[2] ; 6 ;
|
|
|
|
|
; lpm_counter:Ref_rtl_0|dffs[0] ; 6 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; PHI1b9_MC ; 6 ;
|
|
|
|
|
; D[7]~7 ; 5 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; D[6]~6 ; 5 ;
|
|
|
|
|
; D[5]~5 ; 5 ;
|
|
|
|
|
; D[4]~4 ; 5 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; Bank[5] ; 5 ;
|
|
|
|
|
; RAMSEL_MC ; 5 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; lpm_counter:Ref_rtl_0|dffs[1] ; 5 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; Addr[20] ; 4 ;
|
|
|
|
|
; AddrHWR_MC ; 4 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; C7M_2 ; 3 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; Bank[6] ; 3 ;
|
|
|
|
|
; Addr[22] ; 3 ;
|
|
|
|
|
; Addr[21] ; 3 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; IOROMEN ; 3 ;
|
|
|
|
|
; CSDBEN ; 3 ;
|
|
|
|
|
; PHI0seen ; 3 ;
|
|
|
|
|
; PHI1reg ; 3 ;
|
|
|
|
|
; PHI1in ; 2 ;
|
|
|
|
|
; CASr ; 2 ;
|
|
|
|
|
; CASf ; 2 ;
|
|
|
|
|
; RD[7]~7 ; 1 ;
|
|
|
|
|
; RD[6]~6 ; 1 ;
|
|
|
|
|
; RD[5]~5 ; 1 ;
|
|
|
|
|
; RD[4]~4 ; 1 ;
|
|
|
|
|
; RD[3]~3 ; 1 ;
|
|
|
|
|
; RD[2]~2 ; 1 ;
|
|
|
|
|
; RD[1]~1 ; 1 ;
|
|
|
|
|
; RD[0]~0 ; 1 ;
|
|
|
|
|
; A[10] ; 1 ;
|
|
|
|
|
; A[9] ; 1 ;
|
|
|
|
|
; A[8] ; 1 ;
|
|
|
|
|
; A[7] ; 1 ;
|
|
|
|
|
; A[6] ; 1 ;
|
|
|
|
|
; A[5] ; 1 ;
|
|
|
|
|
; A[4] ; 1 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; ~VCC~0 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; RA~111 ; 1 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; RA~106 ; 1 ;
|
|
|
|
|
; RA~105 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; RA~100 ; 1 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; RA~99 ; 1 ;
|
|
|
|
|
; RA~94 ; 1 ;
|
|
|
|
|
; RA~93 ; 1 ;
|
|
|
|
|
; RA~88 ; 1 ;
|
|
|
|
|
; RA~87 ; 1 ;
|
|
|
|
|
; RA~82 ; 1 ;
|
|
|
|
|
; RA~81 ; 1 ;
|
|
|
|
|
; RA~75 ; 1 ;
|
|
|
|
|
; RA~70 ; 1 ;
|
|
|
|
|
; Bank[7] ; 1 ;
|
|
|
|
|
; comb~55 ; 1 ;
|
|
|
|
|
; comb~51 ; 1 ;
|
|
|
|
|
; RA~66 ; 1 ;
|
|
|
|
|
; RA~63 ; 1 ;
|
|
|
|
|
; RA~60 ; 1 ;
|
|
|
|
|
; comb~48 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; RASf ; 1 ;
|
|
|
|
|
; RASr ; 1 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; comb~46 ; 1 ;
|
|
|
|
|
; PHI1b8_MC ; 1 ;
|
|
|
|
|
; PHI1b7_MC ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; PHI1b6_MC ; 1 ;
|
|
|
|
|
; PHI1b5_MC ; 1 ;
|
|
|
|
|
; PHI1b4_MC ; 1 ;
|
|
|
|
|
; PHI1b3_MC ; 1 ;
|
|
|
|
|
; PHI1b2_MC ; 1 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; comb~42 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; PHI1b1_MC ; 1 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; C7M_2~1 ; 1 ;
|
|
|
|
|
; nWE~1 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; PHI1b0_MC ; 1 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; D[7]~38 ; 1 ;
|
|
|
|
|
; D[6]~36 ; 1 ;
|
|
|
|
|
; D[5]~34 ; 1 ;
|
|
|
|
|
; D[4]~32 ; 1 ;
|
|
|
|
|
; D[3]~30 ; 1 ;
|
|
|
|
|
; D[2]~28 ; 1 ;
|
|
|
|
|
; D[1]~26 ; 1 ;
|
|
|
|
|
; D[0]~24 ; 1 ;
|
|
|
|
|
; Dout[7]~95 ; 1 ;
|
|
|
|
|
; Dout[6]~89 ; 1 ;
|
|
|
|
|
; Dout[5]~83 ; 1 ;
|
|
|
|
|
; Dout[4]~77 ; 1 ;
|
|
|
|
|
; Dout[3]~71 ; 1 ;
|
|
|
|
|
; Dout[2]~65 ; 1 ;
|
|
|
|
|
; Dout[1]~59 ; 1 ;
|
|
|
|
|
; Dout[0]~53 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
+-------------------------------+---------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+--------------------------------------------------+
|
|
|
|
|
; Other Routing Usage Summary ;
|
|
|
|
|
+-----------------------------+--------------------+
|
|
|
|
|
; Other Routing Resource Type ; Usage ;
|
|
|
|
|
+-----------------------------+--------------------+
|
|
|
|
|
; Output enables ; 2 / 6 ( 33 % ) ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; PIA buffers ; 198 / 288 ( 69 % ) ;
|
|
|
|
|
; PIAs ; 228 / 288 ( 79 % ) ;
|
2019-09-01 02:55:04 +00:00
|
|
|
+-----------------------------+--------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------------+
|
|
|
|
|
; LAB External Interconnect ;
|
|
|
|
|
+-----------------------------------------------+-----------------------------+
|
2019-09-02 01:18:44 +00:00
|
|
|
; LAB External Interconnects (Average = 28.50) ; Number of LABs (Total = 8) ;
|
2019-09-01 02:55:04 +00:00
|
|
|
+-----------------------------------------------+-----------------------------+
|
2019-09-02 01:18:44 +00:00
|
|
|
; 0 - 2 ; 0 ;
|
|
|
|
|
; 3 - 5 ; 0 ;
|
|
|
|
|
; 6 - 8 ; 0 ;
|
|
|
|
|
; 9 - 11 ; 0 ;
|
|
|
|
|
; 12 - 14 ; 0 ;
|
|
|
|
|
; 15 - 17 ; 0 ;
|
|
|
|
|
; 18 - 20 ; 1 ;
|
|
|
|
|
; 21 - 23 ; 0 ;
|
|
|
|
|
; 24 - 26 ; 0 ;
|
|
|
|
|
; 27 - 29 ; 3 ;
|
|
|
|
|
; 30 - 32 ; 3 ;
|
|
|
|
|
; 33 - 35 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
+-----------------------------------------------+-----------------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------+
|
|
|
|
|
; LAB Macrocells ;
|
|
|
|
|
+-----------------------------------------+-----------------------------+
|
2019-09-02 01:18:44 +00:00
|
|
|
; Number of Macrocells (Average = 12.75) ; Number of LABs (Total = 8) ;
|
2019-09-01 02:55:04 +00:00
|
|
|
+-----------------------------------------+-----------------------------+
|
|
|
|
|
; 0 ; 0 ;
|
|
|
|
|
; 1 ; 0 ;
|
|
|
|
|
; 2 ; 0 ;
|
|
|
|
|
; 3 ; 0 ;
|
|
|
|
|
; 4 ; 0 ;
|
|
|
|
|
; 5 ; 0 ;
|
|
|
|
|
; 6 ; 0 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; 7 ; 0 ;
|
|
|
|
|
; 8 ; 2 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; 9 ; 0 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; 10 ; 0 ;
|
|
|
|
|
; 11 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; 12 ; 0 ;
|
|
|
|
|
; 13 ; 1 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; 14 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
; 15 ; 0 ;
|
|
|
|
|
; 16 ; 3 ;
|
|
|
|
|
+-----------------------------------------+-----------------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-------------------------------------------------------------------------------+
|
|
|
|
|
; Shareable Expander ;
|
|
|
|
|
+-------------------------------------------------+-----------------------------+
|
2019-09-02 01:18:44 +00:00
|
|
|
; Number of shareable expanders (Average = 0.63) ; Number of LABs (Total = 2) ;
|
2019-09-01 02:55:04 +00:00
|
|
|
+-------------------------------------------------+-----------------------------+
|
|
|
|
|
; 0 ; 6 ;
|
2019-09-02 01:18:44 +00:00
|
|
|
; 1 ; 0 ;
|
|
|
|
|
; 2 ; 1 ;
|
|
|
|
|
; 3 ; 1 ;
|
2019-09-01 02:55:04 +00:00
|
|
|
+-------------------------------------------------+-----------------------------+
|
|
|
|
|
|
|
|
|
|
|
2019-09-02 01:18:44 +00:00
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
; Logic Cell Interconnection ;
|
|
|
|
|
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
; LAB ; Logic Cell ; Input ; Output ;
|
|
|
|
|
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], RAMSELreg ; Dout[7]~95, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~111 ;
|
|
|
|
|
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], RAMSELreg ; Dout[3]~71, Addr[11], Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~70 ;
|
|
|
|
|
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[1], S[2], S[0], Addr[0], RAMSELreg ; Dout[0]~53, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~70 ;
|
|
|
|
|
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], RAMSELreg ; Dout[2]~65, Addr[11], Addr[16], Addr[17], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], RA~66, Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
|
|
|
|
|
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], RAMSELreg ; Dout[1]~59, Addr[11], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], RA~63, Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
|
|
|
|
|
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], RAMSELreg ; Dout[0]~53, Addr[11], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], RA~60, Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
|
|
|
|
|
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RAMSELreg ; Dout[7]~95, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[15], RA~93 ;
|
|
|
|
|
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], RAMSELreg ; Dout[6]~89, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[6], Addr[14], Addr[15], RA~105 ;
|
|
|
|
|
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[0], Addr[1], RAMSELreg ; Dout[2]~65, Addr[11], Addr[7], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~81 ;
|
|
|
|
|
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], RAMSELreg ; Dout[5]~83, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~99 ;
|
|
|
|
|
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~75 ;
|
|
|
|
|
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], RAMSELreg ; Dout[5]~83, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[13], Addr[14], Addr[15], RA~81 ;
|
|
|
|
|
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], RAMSELreg ; Dout[4]~77, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~75 ;
|
|
|
|
|
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[0], Addr[1], Addr[2], Addr[3], RAMSELreg ; Dout[4]~77, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~93 ;
|
|
|
|
|
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], RAMSELreg ; Dout[6]~89, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[14], Addr[15], RA~87 ;
|
|
|
|
|
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[0], Addr[1], Addr[2], RAMSELreg ; Dout[3]~71, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~87 ;
|
|
|
|
|
; B ; LC29 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], Addr[17], Addr[18], RAMSELreg ; Dout[3]~71, Addr[19], RA~60, Addr[20], Addr[21], Addr[22] ;
|
|
|
|
|
; B ; LC31 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], Addr[17], RAMSELreg ; Dout[2]~65, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~111 ;
|
|
|
|
|
; B ; LC19 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ;
|
|
|
|
|
; B ; LC30 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~46 ;
|
|
|
|
|
; B ; LC21 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], RAMSELreg ; Dout[0]~53, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~99 ;
|
|
|
|
|
; B ; LC32 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
|
|
|
|
|
; B ; LC27 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~75, RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ;
|
|
|
|
|
; B ; LC17 ; ; nINH ;
|
|
|
|
|
; B ; LC22 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], RAMSELreg ; Dout[1]~59, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~105 ;
|
|
|
|
|
; B ; LC20 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~70, RA~75, RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ;
|
|
|
|
|
; B ; LC26 ; C7M, nRES, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[22], S[1], RAMSELreg, S[2], S[0] ; Addr[22], comb~51, comb~55 ;
|
|
|
|
|
; B ; LC25 ; C7M, nRES, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[21], S[1], RAMSELreg, S[2], S[0] ; Addr[21], RA~66, Addr[22] ;
|
|
|
|
|
; B ; LC28 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ;
|
|
|
|
|
; B ; LC23 ; C7M, nRES, Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[20], S[1], RAMSELreg, S[2], S[0] ; Addr[20], RA~63, Addr[21], Addr[22] ;
|
|
|
|
|
; C ; LC34 ; C7M, nRES, RAMSEL_MC, S[2], S[0], S[1], RAMSELreg ; RAMSELreg, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15] ;
|
|
|
|
|
; C ; LC46 ; PHI1in ; PHI1b1_MC ;
|
|
|
|
|
; C ; LC35 ; C7M_2 ; C7Mout ;
|
|
|
|
|
; C ; LC37 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, PHI1out, S[0], S[1], S[2] ;
|
|
|
|
|
; C ; LC33 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
|
|
|
|
; C ; LC38 ; RD[4], nDEVSEL, A[1], A[2], A[3], A[0], Addr[12], Addr[4] ; D[4] ;
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; C ; LC40 ; RD[5], nDEVSEL, A[1], A[2], A[3], A[0], Addr[13], Addr[5] ; D[5] ;
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; C ; LC43 ; RD[6], nDEVSEL, A[1], A[2], A[3], A[0], Addr[14], Addr[6] ; D[6] ;
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; C ; LC45 ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7] ; D[7] ;
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; C ; LC36 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
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; C ; LC39 ; C7M, nRES, RAMSEL_MC, S[2], S[1] ; RA~60, RA~63, RA~66, RA~70, RA~75, RA~81, RA~87, RA~93, RA~99, RA~105, RA~111 ;
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; C ; LC42 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1] ; comb~48 ;
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; C ; LC41 ; C7M, nRES, nIOSEL, S[0], S[2], S[1] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, IOBank0 ;
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; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ;
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; D ; LC56 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
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; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ;
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; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ;
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; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ;
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; D ; LC53 ; Addr[22], CASf, nDEVSEL, CASr ; nCAS0 ;
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; D ; LC51 ; Addr[22], CASf, nDEVSEL, CASr ; nCAS1 ;
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; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
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; E ; LC80 ; IOBank0, Bank[0], nIOSEL, nIOSTRB, Addr[0], ASel, Addr[11] ; RA[0] ;
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; E ; LC72 ; Addr[10], ASel, Addr[21] ; RA[10] ;
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; E ; LC68 ; PHI1b7_MC ; PHI1b9_MC ;
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; E ; LC67 ; nWE ; nROE ;
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; E ; LC70 ; PHI1b4_MC ; PHI1b6_MC ;
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; E ; LC65 ; PHI1b5_MC ; PHI1b7_MC ;
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; E ; LC69 ; Addr[9], ASel, Addr[20] ; RA[9] ;
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; E ; LC66 ; PHI1b6_MC ; PHI1b8_MC ;
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; E ; LC77 ; IOBank0, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[5], ASel, Addr[16], RA~94 ; RA[5] ;
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; E ; LC73 ; IOBank0, Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[3], ASel, Addr[14], RA~82 ; RA[3] ;
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; E ; LC75 ; IOBank0, Bank[2], Bank[1], nIOSEL, nIOSTRB, Bank[0], Addr[2], ASel, Addr[13] ; RA[2] ;
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; F ; LC93 ; RASr, RASf ; nRAS ;
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; F ; LC91 ; Addr[8], ASel, Addr[19] ; RA[8] ;
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; F ; LC94 ; D[7] ; RD[7] ;
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; F ; LC82 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~99, RA~100, RA~105, RA~106, RA~111 ;
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; F ; LC85 ; IOBank0, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[4], ASel, Addr[15], RA~88 ; RA[4] ;
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; F ; LC88 ; IOBank0, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[6], ASel, Addr[17], RA~100 ; RA[6] ;
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; F ; LC86 ; IOBank0, Bank[7], Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[7], ASel, Addr[18], RA~106 ; RA[7] ;
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; F ; LC83 ; IOBank0, Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[1], ASel, Addr[12] ; RA[1] ;
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; G ; LC109 ; D[1] ; RD[1] ;
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; G ; LC101 ; D[4] ; RD[4] ;
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; G ; LC97 ; D[5] ; RD[5] ;
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; G ; LC111 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
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; G ; LC102 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~46 ;
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; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ;
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; G ; LC108 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~105, RA~106, RA~111 ;
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; G ; LC107 ; D[2] ; RD[2] ;
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; G ; LC99 ; D[6] ; RD[6] ;
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; G ; LC112 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~111 ;
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; G ; LC103 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[0], S[2], S[1], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~70, RA~75, RA~81, RA~87, RA~93, RA~99, RA~105, RA~111 ;
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; G ; LC98 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; ASel, RASr, RAMSELreg, CASr, RASf ;
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; G ; LC105 ; D[3] ; RD[3] ;
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; G ; LC110 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19] ;
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; G ; LC106 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[11], Addr[8], Addr[9], Addr[10], Addr[12], Addr[13], Addr[14], Addr[15] ;
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; G ; LC100 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[7], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6] ;
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; H ; LC115 ; D[0] ; RD[0] ;
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; H ; LC126 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
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; H ; LC128 ; C7M, nRES, S[1], S[0], S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], RAMSEL_MC ; comb~51, comb~55 ;
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; H ; LC119 ; nRES, S[0], S[2], S[1], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], nWE, RAMSEL_MC, C7M_2 ; comb~48 ;
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; H ; LC123 ; PHI1b2_MC ; PHI1b4_MC ;
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; H ; LC124 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
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; H ; LC121 ; PHI1b1_MC ; PHI1b3_MC ;
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; H ; LC114 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ;
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; H ; LC118 ; PHI1b0_MC ; PHI1b2_MC ;
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; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
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; H ; LC120 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
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; H ; LC125 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
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; H ; LC117 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
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; H ; LC122 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
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; H ; LC127 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~51, comb~55 ;
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; H ; LC116 ; PHI1b3_MC ; PHI1b5_MC ;
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+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
2019-09-01 02:55:04 +00:00
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+---------------------------------------------------------------+
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; Fitter Device Options ;
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|
+----------------------------------------------+----------------+
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|
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; Option ; Setting ;
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|
+----------------------------------------------+----------------+
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|
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; Enable user-supplied start-up clock (CLKUSR) ; Off ;
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; Enable device-wide reset (DEV_CLRn) ; Off ;
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; Enable device-wide output enable (DEV_OE) ; Off ;
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; Enable INIT_DONE output ; Off ;
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; Configuration scheme ; Passive Serial ;
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; Security bit ; Off ;
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; Base pin-out file on sameframe device ; Off ;
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|
+----------------------------------------------+----------------+
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|
|
+-----------------+
|
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|
|
; Fitter Messages ;
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|
+-----------------+
|
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|
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Warning (20028): Parallel compilation is not licensed and has been disabled
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|
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
|
2019-09-02 01:18:44 +00:00
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|
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 4708 megabytes
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Info: Processing ended: Sun Sep 01 20:44:15 2019
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
|
2019-09-01 02:55:04 +00:00
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