GR8RAM/cpld/db/GR8RAM.tmw_info

start_full_compilation:s:00:00:26
start_analysis_synthesis:s:00:00:10-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:05-start_full_compilation
start_assembler:s:00:00:05-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502. 2019-10-18 19:07:38 +00:00			`start_full_compilation:s:00:00:26`
			`start_analysis_synthesis:s:00:00:10-start_full_compilation`
Made AddrH high bit variable with mode input 2019-09-08 01:16:23 +00:00			`start_analysis_elaboration:s-start_full_compilation`
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502. 2019-10-18 19:07:38 +00:00			`start_fitter:s:00:00:05-start_full_compilation`
			`start_assembler:s:00:00:05-start_full_compilation`
			`start_timing_analyzer:s:00:00:06-start_full_compilation`