GR8RAM/cpld/output_files/GR8RAM.jdi

<sld_project_info>
  <project>
    <hash md5_digest_80b="053b98ea9c3c88706d49"/>
  </project>
  <file_info>
    <file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>
  </file_info>
</sld_project_info>
CPLD firmware compiles 2019-09-01 02:55:04 +00:00			`<sld_project_info>`
			`<project>`
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502. 2019-10-18 19:07:38 +00:00			`<hash md5_digest_80b="053b98ea9c3c88706d49"/>`
CPLD firmware compiles 2019-09-01 02:55:04 +00:00			`</project>`
			`<file_info>`
			`<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>`
			`</file_info>`
			`</sld_project_info>`