forked from Apple-2-HW/GR8RAM
Register reset/initial values set syntax changed
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@ -73,24 +73,24 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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output nCAS1 = ~(CASr | (CASf & RAMSEL & Addr[22])); // DRAM CAS bank 1
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output nCAS1 = ~(CASr | (CASf & RAMSEL & Addr[22])); // DRAM CAS bank 1
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/* 6502-accessible Registers */
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/* 6502-accessible Registers */
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reg [7:0] Bank = 8'h00; // Bank register for ROM access
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reg [7:0] Bank = 0; // Bank register for ROM access
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reg [22:0] Addr = 23'h00000; // RAM address register
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reg [22:0] Addr = 0; // RAM address register
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/* Increment Control */
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/* Increment Control */
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reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
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reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
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/* CAS rising/falling edge components */
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/* CAS rising/falling edge components */
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// These are combined to create the CAS outputs.
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// These are combined to create the CAS outputs.
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reg CASr = 1'b0;
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reg CASr = 0;
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reg CASf = 1'b0;
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reg CASf = 0;
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reg RASr = 1'b0;
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reg RASr = 0;
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reg RASf = 1'b0;
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reg RASf = 0;
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/* State Counters */
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/* State Counters */
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reg PHI1reg = 1'b0; // Saved PHI1 at last rising clock edge
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reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
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reg PHI0seen = 1'b0; // Have we seen PHI0 since reset?
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reg PHI0seen = 0; // Have we seen PHI0 since reset?
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reg [2:0] S = 3'h0; // State counter
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reg [2:0] S = 0; // State counter
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reg [3:0] Ref = 4'h0; // Refresh skip counter
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reg [3:0] Ref = 0; // Refresh skip counter
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/* Misc. */
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/* Misc. */
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reg REGEN = 0; // Register enable
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reg REGEN = 0; // Register enable
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@ -112,13 +112,13 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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always @(posedge C7M, negedge nRES) begin
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin // Reset
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if (~nRES) begin // Reset
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PHI1reg <= 1'b0;
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PHI1reg <= 0;
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PHI0seen <= 1'b0;
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PHI0seen <= 0;
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S <= 3'h0;
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S <= 0;
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Ref <= 3'b000;
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Ref <= 0;
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REGEN <= 1'b0;
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REGEN <= 0;
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IOROMEN <= 1'b0;
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IOROMEN <= 0;
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CSDBEN <= 1'b0;
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CSDBEN <= 0;
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end else begin
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end else begin
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// Synchronize state counter to S1 when just entering PHI1
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// Synchronize state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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PHI1reg <= PHI1; // Save old PHI1
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@ -151,12 +151,12 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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always @(negedge C7M, negedge nRES) begin
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always @(negedge C7M, negedge nRES) begin
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if (~nRES) begin
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if (~nRES) begin
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Addr <= 23'h000000;
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Addr <= 0;
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Bank <= 8'h00;
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Bank <= 0;
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FullIOEN <= 1'b0;
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FullIOEN <= 0;
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IncAddrL <= 1'b0;
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IncAddrL <= 0;
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IncAddrM <= 1'b0;
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IncAddrM <= 0;
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IncAddrH <= 1'b0;
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IncAddrH <= 0;
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end else begin
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end else begin
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// Increment address register
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// Increment address register
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if (S==1 & IncAddrL) begin
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if (S==1 & IncAddrL) begin
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