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This commit is contained in:
Zane Kaminski 2021-03-19 06:59:22 -04:00
parent 9ac2ba97ae
commit 52b3716342
34 changed files with 610 additions and 494 deletions
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118
cpld/GR8RAM.v
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@ -118,27 +118,22 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout,
wire AddrLSpecSEL = RAcur[3:0]==4'h0; wire AddrLSpecSEL = RAcur[3:0]==4'h0;
always @(posedge C25M) begin always @(posedge C25M) begin
if (~nRESr) begin if (~nRESr) begin
Addr[23:20] <= SetFW[1] ? 4'h0 : 4'hF; Addr[23:0] <= 24'h000000;
Addr[19:0] <= 20'h00000;
end else if (PS==7 && REGEN && DEVSELr) begin end else if (PS==7 && REGEN && DEVSELr) begin
if (RAMSpecSEL) begin if (RAMSpecSEL) begin
if (SetFW[1]) Addr[23:0] <= Addr[23:0]+1; Addr[23:0] <= Addr[23:0]+1;
else Addr[23:0] <= { 4'hF, Addr[19:0]+1 };
end else if (AddrLSpecSEL && ~nWEcur) begin end else if (AddrLSpecSEL && ~nWEcur) begin
Addr[7:0] <= RD[7:0]; Addr[7:0] <= RD[7:0];
if (~RD[7] && Addr[7]) begin if (~RD[7] && Addr[7]) begin
if (SetFW[1]) Addr[23:8] <= Addr[23:8]+1; Addr[23:8] <= Addr[23:8]+1;
else Addr[23:8] <= { 4'hF, Addr[19:8]+1 };
end end
end else if (AddrMSpecSEL && ~nWEcur) begin end else if (AddrMSpecSEL && ~nWEcur) begin
Addr[15:8] <= RD[7:0]; Addr[15:8] <= RD[7:0];
if (~RD[7] && Addr[15]) begin if (~RD[7] && Addr[15]) begin
if (SetFW[1]) Addr[23:16] <= Addr[23:16]+1; Addr[23:16] <= Addr[23:16]+1;
else Addr[23:16] <= { 4'hF, Addr[19:16]+1 };
end end
end else if (AddrHSpecSEL && ~nWEcur) begin end else if (AddrHSpecSEL && ~nWEcur) begin
if (SetFW[1]) Addr[23:16] <= RD[7:0]; Addr[23:16] <= RD[7:0];
else Addr[23:16] <= { 4'hF, RD[3:0] };
end end
end end
end end
@ -260,7 +255,7 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout,
always @(negedge C25M) begin UFMBr0 <= UFMB; RTPBr0 <= RTPB; end always @(negedge C25M) begin UFMBr0 <= UFMB; RTPBr0 <= RTPB; end
always @(posedge C25M) begin UFMBr <= UFMBr0; RTPBr <= RTPBr0; end always @(posedge C25M) begin UFMBr <= UFMBr0; RTPBr <= RTPBr0; end
reg SetLoaded = 0; reg SetLoaded = 0;
reg [1:0] SetFW; reg SetFW;
reg SetLim8M; reg SetLim8M;
always @(posedge C25M) begin always @(posedge C25M) begin
if (~SetLoaded) begin if (~SetLoaded) begin
@ -274,7 +269,7 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout,
ARShift <= 1; ARShift <= 1;
DRCLK <= 0; DRCLK <= 0;
DRShift <= 0; DRShift <= 0;
SetFW[1:0] <= 2'b11; SetFW <= 1'b1;
SetLim8M <= 1'b1; SetLim8M <= 1'b1;
end else if (LS[15:0]<=16'h1FFF) begin end else if (LS[15:0]<=16'h1FFF) begin
case (LS[3:1]) case (LS[3:1])
@ -378,7 +373,7 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout,
Amux[2:0]==2'h0 ? 2'b00 : // mode register / "all" Amux[2:0]==2'h0 ? 2'b00 : // mode register / "all"
Amux[2:0]==2'h1 ? 2'b00 : // FIXME: init row / col Amux[2:0]==2'h1 ? 2'b00 : // FIXME: init row / col
Amux[2:0]==2'h2 ? 2'b10 : // ROM row / col Amux[2:0]==2'h2 ? 2'b10 : // ROM row / col
/* 2'h3 */ { 1'b0, Addr[23] }; // RAM col /* 2'h3 */ { 1'b0, Addr[23] & SetFW & ~SetLim8M }; // RAM col
output [12:0] SA; assign SA[12:0] = output [12:0] SA; assign SA[12:0] =
Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register
Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all" Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all"
@ -386,7 +381,10 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout,
Amux[2:0]==3'h3 ? 13'b0011000100000 : // FIXME: init col Amux[2:0]==3'h3 ? 13'b0011000100000 : // FIXME: init col
Amux[2:0]==3'h4 ? { 9'b000000000, Bank[1:0], RAcur[11:10] } : // ROM row Amux[2:0]==3'h4 ? { 9'b000000000, Bank[1:0], RAcur[11:10] } : // ROM row
Amux[2:0]==3'h5 ? { 4'b0000, RAcur[9:1]} : // ROM col Amux[2:0]==3'h5 ? { 4'b0000, RAcur[9:1]} : // ROM col
Amux[2:0]==3'h6 ? { Addr[22:10] } : // RAM row Amux[2:0]==3'h6 ? { Addr[22] & SetFW,
Addr[21] & SetFW,
Addr[20] & SetFW,
Addr[19:10] } : // RAM row
/* 3'h7 */ { 4'b0000, Addr[9:1] }; // RAM col /* 3'h7 */ { 4'b0000, Addr[9:1] }; // RAM col
output DQML; assign DQML = output DQML; assign DQML =
Amux[2:0]==3'h0 ? 1'b1 : // mode register Amux[2:0]==3'h0 ? 1'b1 : // mode register
@ -415,97 +413,7 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout,
always @(posedge C25M) begin always @(posedge C25M) begin
case (PS[2:0]) case (PS[2:0])
0: begin 0: begin
if (InitActv) begin if (PSStart) begin
case (IS[1:0])
0: begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b000;
end 1: begin
if (LS[3:0]==4'h3) begin
// PC all
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b0;
Amux <= 3'b001;
end else if (LS[3:0]==4'hB) begin
// Load mode
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b0;
Amux <= 3'b000;
end else begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b000;
end
end 2: begin
if (LS[2:0]==3'h3) begin
// AREF
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
Amux <= 3'b000;
end else begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b000;
end
end 3: begin
if (LS[2:0]==3'h3) begin
// AREF
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
Amux <= 3'b010;
end else if (LS[2:0]==3'h5) begin
// ACT
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b010;
end else if (LS[2:0]==3'h7) begin
// WR AP
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b0;
Amux <= 3'b011;
end else begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b010;
end
end
endcase
end else if (PSStart) begin
// NOP CKE // NOP CKE
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b1; nRCS <= 1'b1;

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cpld/db/GR8RAM.fit.qmsg
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42
cpld/db/GR8RAM.hier_info
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@ -8,14 +8,20 @@ C25M => nRAS~reg0.CLK
C25M => nRCS~reg0.CLK C25M => nRCS~reg0.CLK
C25M => RCKE~reg0.CLK C25M => RCKE~reg0.CLK
C25M => RefReqd.CLK C25M => RefReqd.CLK
C25M => IS[0].CLK
C25M => IS[1].CLK
C25M => PS[0].CLK C25M => PS[0].CLK
C25M => PS[1].CLK C25M => PS[1].CLK
C25M => PS[2].CLK C25M => PS[2].CLK
C25M => SDOE.CLK C25M => SDOE.CLK
C25M => WRD[6].CLK C25M => WRD[6].CLK
C25M => WRD[7].CLK C25M => WRD[7].CLK
C25M => DRDIn.CLK
C25M => SetLoaded.CLK
C25M => SetLim8M.CLK
C25M => SetFW.CLK
C25M => DRShift.CLK
C25M => DRCLK.CLK
C25M => ARShift.CLK
C25M => ARCLK.CLK
C25M => MOSIOE.CLK C25M => MOSIOE.CLK
C25M => MOSIout.CLK C25M => MOSIout.CLK
C25M => FCKEN.CLK C25M => FCKEN.CLK
@ -175,3 +181,35 @@ MISO => WRD[7].DATAIN
MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE
|GR8RAM|UFM:UFM_inst
arclk => arclk.IN1
ardin => ardin.IN1
arshft => arshft.IN1
drclk => drclk.IN1
drdin => drdin.IN1
drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.busy
drdout <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.drdout
osc <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.osc
rtpbusy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.rtpbusy
|GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
busy <= maxii_ufm_block1.BUSY
drclk => maxii_ufm_block1.DRCLK
drdin => maxii_ufm_block1.DRDIN
drdout <= maxii_ufm_block1.DRDOUT
drshft => maxii_ufm_block1.DRSHFT
erase => maxii_ufm_block1.ERASE
osc <= maxii_ufm_block1.OSC
oscena => maxii_ufm_block1.OSCENA
program => maxii_ufm_block1.PROGRAM
rtpbusy <= maxii_ufm_block1.BGPBUSY

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cpld/db/GR8RAM.ipinfo
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cpld/db/GR8RAM.lpc.html
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@ -15,4 +15,36 @@
<TH>Input only Bidir</TH> <TH>Input only Bidir</TH>
<TH>Output only Bidir</TH> <TH>Output only Bidir</TH>
</TR> </TR>
<TR >
<TD >UFM_inst|UFM_altufm_none_0ep_component</TD>
<TD >9</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >UFM_inst</TD>
<TD >9</TD>
<TD >2</TD>
<TD >0</TD>
<TD >2</TD>
<TD >4</TD>
<TD >2</TD>
<TD >2</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE> </TABLE>

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cpld/db/GR8RAM.lpc.txt
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@ -1,5 +1,8 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ; ; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; UFM_inst|UFM_altufm_none_0ep_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst ; 9 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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cpld/db/GR8RAM.map.qmsg
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@ -1,31 +1,32 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616150630415 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616151477988 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:43:50 2021 " "Processing started: Fri Mar 19 06:43:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616151478004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:57:57 2021 " "Processing started: Fri Mar 19 06:57:57 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616151478004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616151478004 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616151478004 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616150631900 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616151479754 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150632103 ""} { "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616151480004 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150632103 ""} { "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616151480004 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151480020 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151480020 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616151480020 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(109) " "Verilog HDL warning at gr8ram.v(109): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150632353 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(109) " "Verilog HDL warning at gr8ram.v(109): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616151480270 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(233) " "Verilog HDL warning at gr8ram.v(233): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150632353 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(335) " "Verilog HDL warning at gr8ram.v(335): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616151480270 ""}
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632353 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616150632353 ""} { "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151480285 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616151480285 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616150632384 ""} { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(247) " "Verilog HDL Implicit Net warning at gr8ram.v(247): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 247 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616151480285 ""}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(250) " "Verilog HDL Implicit Net warning at gr8ram.v(250): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 250 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616151480285 ""}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "SetFW gr8ram.v(230) " "Verilog HDL warning at gr8ram.v(230): object SetFW used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616151480316 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(263) " "Verilog HDL or VHDL warning at gr8ram.v(263): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 263 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(34) " "Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(252) " "Verilog HDL or VHDL warning at gr8ram.v(252): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 252 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(125) " "Verilog HDL assignment warning at gr8ram.v(125): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(254) " "Verilog HDL or VHDL warning at gr8ram.v(254): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 254 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 24 gr8ram.v(126) " "Verilog HDL assignment warning at gr8ram.v(126): truncated value with size 36 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "IS gr8ram.v(354) " "Verilog HDL or VHDL warning at gr8ram.v(354): object \"IS\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 354 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(130) " "Verilog HDL assignment warning at gr8ram.v(130): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(365) " "Verilog HDL or VHDL warning at gr8ram.v(365): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 365 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 16 gr8ram.v(131) " "Verilog HDL assignment warning at gr8ram.v(131): truncated value with size 36 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(34) " "Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(136) " "Verilog HDL assignment warning at gr8ram.v(136): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 136 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(124) " "Verilog HDL assignment warning at gr8ram.v(124): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 8 gr8ram.v(137) " "Verilog HDL assignment warning at gr8ram.v(137): truncated value with size 36 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(128) " "Verilog HDL assignment warning at gr8ram.v(128): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 128 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 gr8ram.v(195) " "Verilog HDL assignment warning at gr8ram.v(195): truncated value with size 2 to match size of target (1)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 195 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632400 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(133) " "Verilog HDL assignment warning at gr8ram.v(133): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 133 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480332 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(249) " "Verilog HDL assignment warning at gr8ram.v(249): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 249 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632400 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(351) " "Verilog HDL assignment warning at gr8ram.v(351): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 351 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480348 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(110) " "Net \"RDout\" at gr8ram.v(110) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"} { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(110) " "Net \"RDout\" at gr8ram.v(110) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616151480348 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "SetFW 0 gr8ram.v(230) " "Net \"SetFW\" at gr8ram.v(230) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"} { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(336) " "Net \"WRD\[5..0\]\" at gr8ram.v(336) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 336 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616151480348 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(234) " "Net \"WRD\[5..0\]\" at gr8ram.v(234) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 234 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 250 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616151480457 ""}
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 161 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616150633900 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616150633900 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616151480488 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616150634400 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616150634400 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 156 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616151482051 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616151482051 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "350 " "Implemented 350 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_LCELLS" "281 " "Implemented 281 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616150634962 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616151482410 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 372 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616151482410 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616151482410 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616150635150 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "351 " "Implemented 351 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616151482957 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616151482957 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616151482957 ""} { "Info" "ICUT_CUT_TM_LCELLS" "281 " "Implemented 281 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616151482957 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616151482957 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616151482957 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 06:43:55 2021 " "Processing ended: Fri Mar 19 06:43:55 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616151483223 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616151483426 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 06:58:03 2021 " "Processing ended: Fri Mar 19 06:58:03 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616151483426 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616151483426 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616151483426 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616151483426 ""}

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cpld/db/GR8RAM.map.rdb
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cpld/db/GR8RAM.pre_map.hdb
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cpld/db/GR8RAM.root_partition.map.reg_db.cdb
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cpld/db/GR8RAM.rtlv_sg_swap.cdb
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cpld/db/GR8RAM.vpr.ammdb
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cpld/db/prev_cmp_GR8RAM.qmsg
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cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
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cpld/output_files/GR8RAM.fit.rpt
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@ -1,5 +1,5 @@
Fitter report for GR8RAM Fitter report for GR8RAM
Fri Mar 19 06:44:01 2021 Fri Mar 19 06:58:10 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -50,17 +50,17 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; Fitter Summary ; ; Fitter Summary ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
; Fitter Status ; Failed - Fri Mar 19 06:44:01 2021 ; ; Fitter Status ; Failed - Fri Mar 19 06:58:10 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 250 / 240 ( 104 % ) ; ; Total logic elements ; 247 / 240 ( 103 % ) ;
; Total pins ; 69 / 80 ( 86 % ) ; ; Total pins ; 69 / 80 ( 86 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 1 / 1 ( 100 % ) ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
@ -138,19 +138,19 @@ applicable agreement for further details.
; Total logic elements ; Not available ; ; Total logic elements ; Not available ;
; ; ; ; ; ;
; Total LABs ; Not available ; ; Total LABs ; Not available ;
; Logic elements in carry chains ; 51 ; ; Logic elements in carry chains ; 62 ;
; Virtual pins ; 0 ; ; Virtual pins ; 0 ;
; I/O pins ; 69 / 80 ( 86 % ) ; ; I/O pins ; 69 / 80 ( 86 % ) ;
; -- Clock pins ; 0 / 4 ( 0 % ) ; ; -- Clock pins ; 0 / 4 ( 0 % ) ;
; ; ; ; ; ;
; Global signals ; 1 ; ; Global signals ; 1 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 1 / 1 ( 100 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ; ; Global clocks ; 1 / 4 ( 25 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ;
; Maximum fan-out ; 99 ; ; Maximum fan-out ; 103 ;
; Highest non-global fan-out ; 36 ; ; Highest non-global fan-out ; 36 ;
; Total fan-out ; 1002 ; ; Total fan-out ; 980 ;
; Average fan-out ; 3.14 ; ; Average fan-out ; 3.09 ;
+--------------------------------+------------------+ +--------------------------------+------------------+
@ -159,7 +159,7 @@ applicable agreement for further details.
+---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; ; Name ; Pin # ; I/O Bank ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
+---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; C25M ; Unassigned ; -- ; 99 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; C25M ; Unassigned ; -- ; 103 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;
; MISO ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; MISO ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;
; PHI0 ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; PHI0 ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;
; RA[0] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; RA[0] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;
@ -232,9 +232,9 @@ applicable agreement for further details.
; RD[1] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; ; RD[1] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ;
; RD[2] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; ; RD[2] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ;
; RD[3] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; ; RD[3] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ;
; RD[4] ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; ; RD[4] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ;
; RD[5] ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; ; RD[5] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ;
; RD[6] ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; ; RD[6] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ;
; RD[7] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; ; RD[7] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ;
; SD[0] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; ; SD[0] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ;
; SD[1] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; ; SD[1] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ;
@ -383,13 +383,15 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ; ; Fitter Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; |GR8RAM ; 250 (250) ; 99 ; 0 ; 69 ; 0 ; 151 (151) ; 0 (0) ; 99 (99) ; 51 (51) ; 27 (27) ; |GR8RAM ; work ; ; |GR8RAM ; 247 (247) ; 103 ; 1 ; 69 ; 0 ; 144 (144) ; 0 (0) ; 103 (103) ; 62 (62) ; 27 (27) ; |GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ;
; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -470,27 +472,26 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------+----------+---------------+ +---------+----------+---------------+
+-----------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------+
; Control Signals ; ; Control Signals ;
+-------------+------------+---------+-------------------------+--------+----------------------+------------------+ +-------------+------------+---------+---------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------+------------+---------+-------------------------+--------+----------------------+------------------+ +-------------+------------+---------+---------------+--------+----------------------+------------------+
; Addr[14]~8 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; ; ARCLK~6 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ;
; Addr[17]~19 ; Unassigned ; 4 ; Clock enable ; no ; -- ; -- ; ; Addr[0]~4 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ;
; Addr[4]~10 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; ; Addr[20]~16 ; Unassigned ; 7 ; Clock enable ; no ; -- ; -- ;
; Bank[0]~1 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; ; Addr[9]~2 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ;
; C25M ; Unassigned ; 99 ; Clock ; yes ; Global Clock ; Not Available ; ; Bank[0]~1 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ;
; Equal0~3 ; Unassigned ; 3 ; Clock enable ; no ; -- ; -- ; ; C25M ; Unassigned ; 103 ; Clock ; yes ; Global Clock ; Not Available ;
; IS[0]~4 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; ; DRShift~0 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ;
; InitActv ; Unassigned ; 23 ; Sync. clear ; no ; -- ; -- ; ; Equal0~3 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ;
; MOSIOE ; Unassigned ; 3 ; Output enable ; no ; -- ; -- ; ; MOSIOE ; Unassigned ; 3 ; Output enable ; no ; -- ; -- ;
; MOSIout~2 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; ; MOSIout~4 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ;
; PSStart~2 ; Unassigned ; 18 ; Clock enable ; no ; -- ; -- ; ; PSStart~1 ; Unassigned ; 18 ; Clock enable ; no ; -- ; -- ;
; PS[2] ; Unassigned ; 17 ; Sync. load ; no ; -- ; -- ; ; SDOE ; Unassigned ; 8 ; Output enable ; no ; -- ; -- ;
; SDOE ; Unassigned ; 8 ; Output enable ; no ; -- ; -- ; ; always18~0 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ;
; always15~0 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; ; nRESr ; Unassigned ; 36 ; Sync. clear ; no ; -- ; -- ;
; nRESr ; Unassigned ; 36 ; Sync. clear, Sync. load ; no ; -- ; -- ; +-------------+------------+---------+---------------+--------+----------------------+------------------+
+-------------+------------+---------+-------------------------+--------+----------------------+------------------+
+-----------------------------------------------------------------------+ +-----------------------------------------------------------------------+
@ -498,7 +499,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------+------------+---------+----------------------+------------------+ +------+------------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+------------+---------+----------------------+------------------+ +------+------------+---------+----------------------+------------------+
; C25M ; Unassigned ; 99 ; Global Clock ; Not Available ; ; C25M ; Unassigned ; 103 ; Global Clock ; Not Available ;
+------+------------+---------+----------------------+------------------+ +------+------------+---------+----------------------+------------------+
@ -508,84 +509,84 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Fan-Out ; ; Name ; Fan-Out ;
+--------------+------------------+ +--------------+------------------+
; nRESr ; 36 ; ; nRESr ; 36 ;
; InitActv ; 23 ;
; RAMSpecSEL~4 ; 19 ;
; PS[1] ; 19 ;
; Amux[1] ; 19 ; ; Amux[1] ; 19 ;
; PSStart~2 ; 18 ; ; RAMSpecSEL~4 ; 18 ;
; PSStart~1 ; 18 ;
; Amux[0] ; 18 ; ; Amux[0] ; 18 ;
; PS[2] ; 17 ;
; Amux[2] ; 17 ; ; Amux[2] ; 17 ;
; PS[0] ; 16 ; ; PS[0] ; 16 ;
; RAcur[0] ; 15 ; ; RAcur[0] ; 14 ;
; always11~0 ; 13 ; ; PS[2] ; 13 ;
; LS[2] ; 12 ; ; PS[1] ; 13 ;
; LS[1] ; 12 ; ; Addr[20]~10 ; 11 ;
; LS[0] ; 11 ; ; Addr[0]~3 ; 11 ;
; LS[3] ; 11 ; ; always11~0 ; 11 ;
; LS[4] ; 9 ; ; InitActv ; 11 ;
; LS[6] ; 11 ;
; LS[1] ; 10 ;
; comb~2 ; 9 ; ; comb~2 ; 9 ;
; Addr[4]~10 ; 8 ; ; Addr[0]~4 ; 8 ;
; Addr[14]~8 ; 8 ; ; Addr[9]~2 ; 8 ;
; RAMSpecSEL~2 ; 8 ;
; LS[5] ; 8 ;
; SDOE ; 8 ; ; SDOE ; 8 ;
; Addr[17] ; 7 ; ; LS[5] ; 8 ;
; Addr[16] ; 7 ; ; LS[4] ; 8 ;
; Addr[4]~9 ; 7 ; ; LS[3] ; 8 ;
; IS[1] ; 7 ; ; Addr[20]~16 ; 7 ;
; RAMSpecSEL~3 ; 7 ; ; RAMSpecSEL~1 ; 7 ;
; nWEcur ; 6 ; ; nWEcur ; 6 ;
; Addr[18] ; 6 ; ; RAMSpecSEL~3 ; 6 ;
; Addr[17]~16 ; 6 ; ; Equal7~0 ; 6 ;
; Equal15~0 ; 5 ; ; LS[2] ; 6 ;
; Addr[19] ; 5 ; ; LS[7] ; 6 ;
; IS[0] ; 5 ; ; SetLoaded ; 5 ;
; always11~1 ; 5 ; ; Mux1~0 ; 5 ;
; LS[6] ; 5 ; ; LS[0] ; 5 ;
; Equal36~1 ; 5 ; ; LS[15] ; 5 ;
; LS[14] ; 5 ;
; LS[13] ; 5 ;
; LS[12] ; 5 ;
; Equal45~1 ; 5 ;
; RD[7]~7 ; 4 ; ; RD[7]~7 ; 4 ;
; RD[1]~1 ; 4 ; ; RD[1]~1 ; 4 ;
; RD[0]~0 ; 4 ; ; RD[0]~0 ; 4 ;
; Equal16~1 ; 4 ; ; Addr[22] ; 4 ;
; always19~1 ; 4 ; ; Addr[21] ; 4 ;
; Mux6~3 ; 4 ; ; Addr[20] ; 4 ;
; Addr[17]~19 ; 4 ; ; Addr[19] ; 4 ;
; Addr[18] ; 4 ;
; Addr[17] ; 4 ;
; Addr[16] ; 4 ;
; RACr ; 4 ; ; RACr ; 4 ;
; RAcur[1] ; 4 ; ; RAcur[1] ; 4 ;
; Equal7~0 ; 4 ;
; Equal16~0 ; 4 ;
; nBODf ; 4 ; ; nBODf ; 4 ;
; LS[17] ; 4 ; ; LS[17] ; 4 ;
; LS[16] ; 4 ;
; LS[7] ; 4 ;
; Equal2~0 ; 4 ;
; Addr[7] ; 4 ; ; Addr[7] ; 4 ;
; Addr[15] ; 4 ; ; Addr[15] ; 4 ;
; Addr[23] ; 4 ; ; RD[6]~6 ; 3 ;
; RD[5]~5 ; 3 ;
; RD[4]~4 ; 3 ;
; RD[3]~3 ; 3 ; ; RD[3]~3 ; 3 ;
; RD[2]~2 ; 3 ; ; RD[2]~2 ; 3 ;
; Equal33~0 ; 3 ; ; ARCLK~4 ; 3 ;
; Equal30~0 ; 3 ; ; Equal39~0 ; 3 ;
; MOSIOE ; 3 ; ; MOSIOE ; 3 ;
; Equal12~0 ; 3 ; ; Equal12~0 ; 3 ;
; nRCS~0 ; 3 ; ; always22~1 ; 3 ;
; RefReqd ; 3 ; ; RefReqd ; 3 ;
; Addr~4 ; 3 ; ; always11~1 ; 3 ;
; RAcur[2] ; 3 ; ; RAcur[2] ; 3 ;
; RAcur[3] ; 3 ; ; RAcur[3] ; 3 ;
; always6~0 ; 3 ; ; always6~2 ; 3 ;
; Equal0~3 ; 3 ; ; always6~1 ; 3 ;
; Equal2~4 ; 3 ; ; Equal0~2 ; 3 ;
; LS[15] ; 3 ; ; LS[8] ; 3 ;
; LS[14] ; 3 ;
; LS[13] ; 3 ;
; LS[12] ; 3 ;
; LS[11] ; 3 ; ; LS[11] ; 3 ;
; LS[10] ; 3 ; ; LS[10] ; 3 ;
; LS[9] ; 3 ; ; LS[9] ; 3 ;
; LS[8] ; 3 ; ; LS[16] ; 3 ;
; Addr[20] ; 3 ; ; Equal44~0 ; 3 ;
; Equal0~0 ; 3 ;
; DRCLK~0 ; 3 ;
; Addr[9] ; 3 ; ; Addr[9] ; 3 ;
; Addr[8] ; 3 ; ; Addr[8] ; 3 ;
; Addr[14] ; 3 ; ; Addr[14] ; 3 ;
@ -594,49 +595,49 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Addr[11] ; 3 ; ; Addr[11] ; 3 ;
; Addr[10] ; 3 ; ; Addr[10] ; 3 ;
; REGEN ; 3 ; ; REGEN ; 3 ;
; RD[6]~6 ; 2 ;
; RD[5]~5 ; 2 ;
; RD[4]~4 ; 2 ;
; nIOSEL ; 2 ; ; nIOSEL ; 2 ;
; nIOSTRB ; 2 ; ; nIOSTRB ; 2 ;
; nDEVSEL ; 2 ; ; nDEVSEL ; 2 ;
; nWE ; 2 ; ; nWE ; 2 ;
; PHI0 ; 2 ; ; PHI0 ; 2 ;
; IS[0]~4 ; 2 ; ; always18~0 ; 2 ;
; always15~0 ; 2 ; ; MOSIout~4 ; 2 ;
; MOSIout~2 ; 2 ;
; Equal15~2 ; 2 ;
; SDRAMActv ; 2 ; ; SDRAMActv ; 2 ;
; Equal15~1 ; 2 ; ; Equal0~3 ; 2 ;
; Equal44~1 ; 2 ;
; ARCLK~6 ; 2 ;
; DRShift~0 ; 2 ;
; DRCLK~2 ; 2 ;
; ARCLK~1 ; 2 ;
; MOSIout ; 2 ; ; MOSIout ; 2 ;
; FCKEN ; 2 ; ; FCKEN ; 2 ;
; Equal0~4 ; 2 ; ; FCS~1 ; 2 ;
; FCS~3 ; 2 ; ; FCKEN~2 ; 2 ;
; FCS~2 ; 2 ; ; Equal12~1 ; 2 ;
; Mux7~1 ; 2 ; ; Mux4~0 ; 2 ;
; Mux7~0 ; 2 ; ; Mux1~3 ; 2 ;
; always19~0 ; 2 ; ; always22~0 ; 2 ;
; Mux1~1 ; 2 ;
; Bank[0]~1 ; 2 ; ; Bank[0]~1 ; 2 ;
; Mux11~0 ; 2 ;
; DEVSELr ; 2 ; ; DEVSELr ; 2 ;
; RAcur[7] ; 2 ; ; RAcur[7] ; 2 ;
; RAMSpecSEL~2 ; 2 ;
; RAcur[10] ; 2 ; ; RAcur[10] ; 2 ;
; RAMSpecSEL~1 ; 2 ;
; always10~3 ; 2 ; ; always10~3 ; 2 ;
; always10~0 ; 2 ; ; always10~0 ; 2 ;
; RAMSpecSEL~0 ; 2 ; ; RAMSpecSEL~0 ; 2 ;
; IOSELr ; 2 ; ; IOSELr ; 2 ;
; Equal0~2 ; 2 ; ; always6~0 ; 2 ;
; Equal35~0 ; 2 ; ; ARCLK~0 ; 2 ;
; SDRAMActv~0 ; 2 ; ; SDRAMActv~0 ; 2 ;
; InitIntr ; 2 ; ; InitIntr ; 2 ;
; Equal2~6 ; 2 ; ; Equal2~3 ; 2 ;
; Equal2~2 ; 2 ;
; FCS ; 2 ; ; FCS ; 2 ;
; RCKE~reg0 ; 2 ; ; RCKE~reg0 ; 2 ;
; DQML~1 ; 2 ; ; DQML~1 ; 2 ;
; DQML~0 ; 2 ; ; DQML~0 ; 2 ;
; Addr[0] ; 2 ; ; Addr[0] ; 2 ;
; SA~24 ; 2 ;
; RAcur[9] ; 2 ; ; RAcur[9] ; 2 ;
; RAcur[8] ; 2 ; ; RAcur[8] ; 2 ;
; Addr[6] ; 2 ; ; Addr[6] ; 2 ;
@ -666,87 +667,100 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RA[2] ; 1 ; ; RA[2] ; 1 ;
; RA[10] ; 1 ; ; RA[10] ; 1 ;
; RA[1] ; 1 ; ; RA[1] ; 1 ;
; MOSIout~3 ; 1 ; ; ~GND ; 1 ;
; Equal17~2 ; 1 ; ; FCKEN~4 ; 1 ;
; Addr~31 ; 1 ;
; WRD[6] ; 1 ; ; WRD[6] ; 1 ;
; Equal31~0 ; 1 ; ; Equal39~1 ; 1 ;
; Equal16~2 ; 1 ; ; MOSIout~2 ; 1 ;
; FCKEN~1 ; 1 ; ; MOSIout~1 ; 1 ;
; Equal30~1 ; 1 ; ; MOSIout~0 ; 1 ;
; Equal44~2 ; 1 ;
; DEVSELr0 ; 1 ; ; DEVSELr0 ; 1 ;
; IOSTRBr0 ; 1 ; ; IOSTRBr0 ; 1 ;
; IOSELr0 ; 1 ; ; IOSELr0 ; 1 ;
; FCKEN~0 ; 1 ; ; ARCLK~3 ; 1 ;
; FCS~4 ; 1 ; ; ARCLK~2 ; 1 ;
; Mux5~2 ; 1 ; ; DRShift~1 ; 1 ;
; Mux5~1 ; 1 ; ; FCS~0 ; 1 ;
; Mux5~0 ; 1 ; ; Mux0~2 ; 1 ;
; Mux0~1 ; 1 ;
; Mux0~0 ; 1 ;
; Add1~112 ; 1 ;
; Add1~110 ; 1 ;
; Mux3~0 ; 1 ;
; Mux1~5 ; 1 ;
; Mux1~2 ; 1 ;
; Add1~105 ; 1 ;
; Addr~29 ; 1 ;
; Add2~70 ; 1 ;
; Add3~30 ; 1 ;
; Add1~102 ; 1 ; ; Add1~102 ; 1 ;
; Add1~100 ; 1 ; ; Add1~100 ; 1 ;
; Mux9~1 ; 1 ; ; Addr~27 ; 1 ;
; Mux9~0 ; 1 ; ; Add3~27 ; 1 ;
; Mux8~1 ; 1 ; ; Add3~25 ; 1 ;
; Mux8~0 ; 1 ; ; Add2~67 ; 1 ;
; Mux6~6 ; 1 ; ; Add2~65 ; 1 ;
; Mux7~5 ; 1 ; ; Add1~97 ; 1 ;
; Mux7~4 ; 1 ;
; Mux7~3 ; 1 ;
; Mux7~2 ; 1 ;
; Mux6~4 ; 1 ;
; Mux6~2 ; 1 ;
; Mux6~1 ; 1 ;
; Mux6~0 ; 1 ;
; Addr~30 ; 1 ;
; Addr~29 ; 1 ;
; Add2~60 ; 1 ;
; Addr~28 ; 1 ;
; Add1~95 ; 1 ; ; Add1~95 ; 1 ;
; Addr~25 ; 1 ;
; Add2~62 ; 1 ;
; Add2~60 ; 1 ;
; Add3~22 ; 1 ;
; Add3~20 ; 1 ;
; Add1~92 ; 1 ; ; Add1~92 ; 1 ;
; Add1~90 ; 1 ; ; Add1~90 ; 1 ;
; Addr~26 ; 1 ; ; Addr~23 ; 1 ;
; Add3~2 ; 1 ; ; Add3~17 ; 1 ;
; Add3~15 ; 1 ;
; Add2~57 ; 1 ; ; Add2~57 ; 1 ;
; Add2~55 ; 1 ; ; Add2~55 ; 1 ;
; Add1~87 ; 1 ; ; Add1~87 ; 1 ;
; Add1~85 ; 1 ; ; Add1~85 ; 1 ;
; Addr~24 ; 1 ; ; Addr~21 ; 1 ;
; Add2~52 ; 1 ; ; Add2~52 ; 1 ;
; Add2~50 ; 1 ; ; Add2~50 ; 1 ;
; Add3~1 ; 1 ; ; Add3~12 ; 1 ;
; Add3~10 ; 1 ;
; Add1~82 ; 1 ; ; Add1~82 ; 1 ;
; Add1~80 ; 1 ; ; Add1~80 ; 1 ;
; Addr~23 ; 1 ; ; Addr~20 ; 1 ;
; Add2~47 ; 1 ; ; Add2~47 ; 1 ;
; Add2~45 ; 1 ; ; Add2~45 ; 1 ;
; Add1~77 ; 1 ; ; Add1~77 ; 1 ;
; Add1~75 ; 1 ; ; Add1~75 ; 1 ;
; Addr~21 ; 1 ; ; Addr~18 ; 1 ;
; Add3~0 ; 1 ; ; Add3~7 ; 1 ;
; Add3~5 ; 1 ;
; Add2~42 ; 1 ; ; Add2~42 ; 1 ;
; Add2~40 ; 1 ; ; Add2~40 ; 1 ;
; Add1~72 ; 1 ; ; Add1~72 ; 1 ;
; Add1~70 ; 1 ; ; Add1~70 ; 1 ;
; Addr~20 ; 1 ; ; Addr~17 ; 1 ;
; Add2~37 ; 1 ; ; Add2~37 ; 1 ;
; Add2~35 ; 1 ; ; Add2~35 ; 1 ;
; Addr[20]~15 ; 1 ;
; Addr[20]~14 ; 1 ;
; Addr[20]~13 ; 1 ;
; Add1~67 ; 1 ; ; Add1~67 ; 1 ;
; Add1~65 ; 1 ; ; Add1~65 ; 1 ;
; Addr~17 ; 1 ; ; Addr~11 ; 1 ;
; Add2~32 ; 1 ; ; Add2~32 ; 1 ;
; Add2~30 ; 1 ; ; Add2~30 ; 1 ;
; Add3~2 ; 1 ;
; Add3~0 ; 1 ;
; Add1~62 ; 1 ; ; Add1~62 ; 1 ;
; Add1~60 ; 1 ; ; Add1~60 ; 1 ;
; Add1~57 ; 1 ; ; Add1~57 ; 1 ;
; Add1~55 ; 1 ; ; Add1~55 ; 1 ;
; Addr~15 ; 1 ; ; Addr~9 ; 1 ;
; Add2~27 ; 1 ; ; Add2~27 ; 1 ;
; Add2~25 ; 1 ; ; Add2~25 ; 1 ;
; Add1~52 ; 1 ; ; Add1~52 ; 1 ;
; Add1~50 ; 1 ; ; Add1~50 ; 1 ;
; Add1~47 ; 1 ; ; Add1~47 ; 1 ;
; Add1~45 ; 1 ; ; Add1~45 ; 1 ;
; Addr~14 ; 1 ; ; Addr~8 ; 1 ;
; Add2~22 ; 1 ; ; Add2~22 ; 1 ;
; Add2~20 ; 1 ; ; Add2~20 ; 1 ;
; Add1~42 ; 1 ; ; Add1~42 ; 1 ;
@ -755,67 +769,59 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Add1~35 ; 1 ; ; Add1~35 ; 1 ;
; Add1~32 ; 1 ; ; Add1~32 ; 1 ;
; Add1~30 ; 1 ; ; Add1~30 ; 1 ;
; Addr~13 ; 1 ; ; Addr~7 ; 1 ;
; Add2~17 ; 1 ; ; Add2~17 ; 1 ;
; Add2~15 ; 1 ; ; Add2~15 ; 1 ;
; Add1~27 ; 1 ; ; Add1~27 ; 1 ;
; Add1~25 ; 1 ; ; Add1~25 ; 1 ;
; Add1~22 ; 1 ; ; Add1~22 ; 1 ;
; Add1~20 ; 1 ; ; Add1~20 ; 1 ;
; Addr~12 ; 1 ; ; Addr~6 ; 1 ;
; Add2~12 ; 1 ; ; Add2~12 ; 1 ;
; Add2~10 ; 1 ; ; Add2~10 ; 1 ;
; Add1~17 ; 1 ; ; Add1~17 ; 1 ;
; Add1~15 ; 1 ; ; Add1~15 ; 1 ;
; Add1~12 ; 1 ; ; Add1~12 ; 1 ;
; Add1~10 ; 1 ; ; Add1~10 ; 1 ;
; Addr~11 ; 1 ; ; Addr~5 ; 1 ;
; Add2~7 ; 1 ; ; Add2~7 ; 1 ;
; Add2~5 ; 1 ; ; Add2~5 ; 1 ;
; Add1~7 ; 1 ; ; Add1~7 ; 1 ;
; Add1~5 ; 1 ; ; Add1~5 ; 1 ;
; Addr[14]~7 ; 1 ; ; Addr[9]~1 ; 1 ;
; Add1~2 ; 1 ; ; Add1~2 ; 1 ;
; Add1~0 ; 1 ; ; Add1~0 ; 1 ;
; Addr~6 ; 1 ; ; Addr~0 ; 1 ;
; Add2~2 ; 1 ; ; Add2~2 ; 1 ;
; Add2~0 ; 1 ; ; Add2~0 ; 1 ;
; PHI0r1 ; 1 ; ; PHI0r1 ; 1 ;
; PSStart~1 ; 1 ;
; WideOr0~2 ; 1 ;
; WideOr0~1 ; 1 ;
; ROMSpecRD ; 1 ;
; Mux10~0 ; 1 ;
; PSStart~0 ; 1 ; ; PSStart~0 ; 1 ;
; Mux11~1 ; 1 ; ; ROMSpecRD ; 1 ;
; Addr~5 ; 1 ;
; Addr~3 ; 1 ;
; Addr~2 ; 1 ;
; RAcur[4] ; 1 ; ; RAcur[4] ; 1 ;
; always10~2 ; 1 ; ; always10~2 ; 1 ;
; always10~1 ; 1 ; ; always10~1 ; 1 ;
; nBODf0 ; 1 ;
; Equal0~1 ; 1 ; ; Equal0~1 ; 1 ;
; Equal0~0 ; 1 ; ; LS[6]~33 ; 1 ;
; LS[4]~33 ; 1 ;
; Equal2~5 ; 1 ;
; LS[2]~31 ; 1 ;
; LS[1]~29 ; 1 ;
; Equal2~3 ; 1 ;
; LS[15]~27 ; 1 ;
; LS[14]~25 ; 1 ;
; LS[16]~21 ; 1 ;
; Equal2~2 ; 1 ;
; LS[13]~19 ; 1 ;
; LS[12]~17 ; 1 ;
; LS[11]~15 ; 1 ;
; LS[10]~13 ; 1 ;
; Equal2~1 ; 1 ; ; Equal2~1 ; 1 ;
; LS[9]~11 ; 1 ; ; LS[8]~31 ; 1 ;
; LS[8]~9 ; 1 ; ; Equal2~0 ; 1 ;
; LS[7]~7 ; 1 ; ; LS[11]~29 ; 1 ;
; LS[5]~5 ; 1 ; ; LS[10]~27 ; 1 ;
; LS[6]~3 ; 1 ; ; LS[9]~25 ; 1 ;
; LS[16]~23 ; 1 ;
; LS[2]~21 ; 1 ;
; LS[5]~19 ; 1 ;
; LS[4]~17 ; 1 ;
; LS[7]~15 ; 1 ;
; LS[15]~13 ; 1 ;
; LS[14]~11 ; 1 ;
; LS[13]~9 ; 1 ;
; LS[12]~7 ; 1 ;
; LS[1]~3 ; 1 ;
; ARShift ; 1 ;
; ARCLK ; 1 ;
; DRShift ; 1 ;
; DRCLK ; 1 ;
; FCK~reg0 ; 1 ; ; FCK~reg0 ; 1 ;
; DQMH~0 ; 1 ; ; DQMH~0 ; 1 ;
; DQML~2 ; 1 ; ; DQML~2 ; 1 ;
@ -824,6 +830,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; nCAS~reg0 ; 1 ; ; nCAS~reg0 ; 1 ;
; nRAS~reg0 ; 1 ; ; nRAS~reg0 ; 1 ;
; nRCS~reg0 ; 1 ; ; nRCS~reg0 ; 1 ;
; SA~25 ; 1 ;
; SA~24 ; 1 ;
; SA~23 ; 1 ; ; SA~23 ; 1 ;
; SA~22 ; 1 ; ; SA~22 ; 1 ;
; SA~21 ; 1 ; ; SA~21 ; 1 ;
@ -853,12 +861,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; SA~4 ; 1 ; ; SA~4 ; 1 ;
; RAcur[11] ; 1 ; ; RAcur[11] ; 1 ;
; SA~3 ; 1 ; ; SA~3 ; 1 ;
; PHI0r0 ; 1 ;
; SA~2 ; 1 ; ; SA~2 ; 1 ;
; SA~1 ; 1 ; ; SA~1 ; 1 ;
; SA~0 ; 1 ; ; SA~0 ; 1 ;
; PHI0r0 ; 1 ; ; nBODf0 ; 1 ;
; Equal36~0 ; 1 ; ; Equal45~0 ; 1 ;
; SBA~0 ; 1 ;
; nRESr0 ; 1 ; ; nRESr0 ; 1 ;
; comb~1 ; 1 ; ; comb~1 ; 1 ;
; PHI0r2 ; 1 ; ; PHI0r2 ; 1 ;
@ -989,7 +997,7 @@ Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (170189): Fitter placement preparation operations beginning Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds.
@ -1002,7 +1010,7 @@ Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (170189): Fitter placement preparation operations beginning Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.00 seconds. Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
Info (170216): Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements Info (170216): Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements
Info (176234): Starting register packing Info (176234): Starting register packing
Info (186391): Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option Info (186391): Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option
@ -1011,15 +1019,15 @@ Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (170189): Fitter placement preparation operations beginning Info (170189): Fitter placement preparation operations beginning
Error (170011): Design contains 250 blocks of type logic cell. However, device contains only 240. Error (170011): Design contains 247 blocks of type logic cell. However, device contains only 240.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds. Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
Error (171000): Can't fit design in device Error (171000): Can't fit design in device
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
Error: Quartus II 32-bit Fitter was unsuccessful. 2 errors, 4 warnings Error: Quartus II 32-bit Fitter was unsuccessful. 2 errors, 4 warnings
Error: Peak virtual memory: 359 megabytes Error: Peak virtual memory: 367 megabytes
Error: Processing ended: Fri Mar 19 06:44:01 2021 Error: Processing ended: Fri Mar 19 06:58:10 2021
Error: Elapsed time: 00:00:05 Error: Elapsed time: 00:00:05
Error: Total CPU time (on all processors): 00:00:05 Error: Total CPU time (on all processors): 00:00:05

6
cpld/output_files/GR8RAM.fit.summary
View File

@ -1,11 +1,11 @@
Fitter Status : Failed - Fri Mar 19 06:44:01 2021 Fitter Status : Failed - Fri Mar 19 06:58:10 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Device : EPM240T100C5 Device : EPM240T100C5
Timing Models : Final Timing Models : Final
Total logic elements : 250 / 240 ( 104 % ) Total logic elements : 247 / 240 ( 103 % )
Total pins : 69 / 80 ( 86 % ) Total pins : 69 / 80 ( 86 % )
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % ) UFM blocks : 1 / 1 ( 100 % )

18
cpld/output_files/GR8RAM.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for GR8RAM Flow report for GR8RAM
Fri Mar 19 06:44:01 2021 Fri Mar 19 06:58:10 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,17 +40,17 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
; Flow Status ; Flow Failed - Fri Mar 19 06:44:01 2021 ; ; Flow Status ; Flow Failed - Fri Mar 19 06:58:10 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 250 / 240 ( 104 % ) ; ; Total logic elements ; 247 / 240 ( 103 % ) ;
; Total pins ; 69 / 80 ( 86 % ) ; ; Total pins ; 69 / 80 ( 86 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 1 / 1 ( 100 % ) ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
@ -59,7 +59,7 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/19/2021 06:43:51 ; ; Start date & time ; 03/19/2021 06:57:59 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
+-------------------+---------------------+ +-------------------+---------------------+
@ -70,7 +70,7 @@ applicable agreement for further details.
+---------------------------------------+--------------------------------+---------------+-------------+------------+ +---------------------------------------+--------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+--------------------------------+---------------+-------------+------------+ +---------------------------------------+--------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 44085571633675.161615063101880 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 44085571633675.161615147901060 ; -- ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; ; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
@ -88,9 +88,9 @@ applicable agreement for further details.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ; ; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:05 ;
; Fitter ; 00:00:05 ; 1.0 ; 359 MB ; 00:00:04 ; ; Fitter ; 00:00:05 ; 1.0 ; 367 MB ; 00:00:05 ;
; Total ; 00:00:10 ; -- ; -- ; 00:00:09 ; ; Total ; 00:00:11 ; -- ; -- ; 00:00:10 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+

172
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM Analysis & Synthesis report for GR8RAM
Fri Mar 19 06:43:55 2021 Fri Mar 19 06:58:03 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -13,12 +13,15 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
5. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis 8. Analysis & Synthesis IP Cores Summary
9. General Register Statistics 9. Registers Removed During Synthesis
10. Inverted Register Statistics 10. Removed Registers Triggering Further Register Optimizations
11. Multiplexer Restructuring Statistics (Restructuring Performed) 11. General Register Statistics
12. Analysis & Synthesis Messages 12. Inverted Register Statistics
13. Analysis & Synthesis Suppressed Messages 13. Multiplexer Restructuring Statistics (Restructuring Performed)
14. Port Connectivity Checks: "UFM:UFM_inst"
15. Analysis & Synthesis Messages
16. Analysis & Synthesis Suppressed Messages
@ -44,7 +47,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Mar 19 06:43:55 2021 ; ; Analysis & Synthesis Status ; Successful - Fri Mar 19 06:58:03 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
@ -52,7 +55,7 @@ applicable agreement for further details.
; Total logic elements ; 281 ; ; Total logic elements ; 281 ;
; Total pins ; 69 ; ; Total pins ; 69 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
@ -151,6 +154,7 @@ applicable agreement for further details.
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+ +----------------------------------+-----------------+------------------------------+-------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+ +----------------------------------+-----------------+------------------------------+-------------------------------+---------+
; UFM.v ; yes ; User Wizard-Generated File ; Z:/Repos/GR8RAM/cpld/UFM.v ; ;
; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; Z:/Repos/GR8RAM/cpld/gr8ram.v ; ; ; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; Z:/Repos/GR8RAM/cpld/gr8ram.v ; ;
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+ +----------------------------------+-----------------+------------------------------+-------------------------------+---------+
@ -161,53 +165,77 @@ applicable agreement for further details.
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Total logic elements ; 281 ; ; Total logic elements ; 281 ;
; -- Combinational with no register ; 182 ; ; -- Combinational with no register ; 178 ;
; -- Register only ; 31 ; ; -- Register only ; 34 ;
; -- Combinational with a register ; 68 ; ; -- Combinational with a register ; 69 ;
; ; ; ; ; ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 118 ; ; -- 4 input functions ; 106 ;
; -- 3 input functions ; 54 ; ; -- 3 input functions ; 52 ;
; -- 2 input functions ; 70 ; ; -- 2 input functions ; 80 ;
; -- 1 input functions ; 8 ; ; -- 1 input functions ; 8 ;
; -- 0 input functions ; 0 ; ; -- 0 input functions ; 1 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 233 ; ; -- normal mode ; 223 ;
; -- arithmetic mode ; 48 ; ; -- arithmetic mode ; 58 ;
; -- qfbk mode ; 0 ; ; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ; ; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 28 ; ; -- synchronous clear/load mode ; 25 ;
; -- asynchronous clear/load mode ; 0 ; ; -- asynchronous clear/load mode ; 0 ;
; ; ; ; ; ;
; Total registers ; 99 ; ; Total registers ; 103 ;
; Total logic cells in carry chains ; 51 ; ; Total logic cells in carry chains ; 62 ;
; I/O pins ; 69 ; ; I/O pins ; 69 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; C25M ; ; Maximum fan-out node ; C25M ;
; Maximum fan-out ; 99 ; ; Maximum fan-out ; 103 ;
; Total fan-out ; 1030 ; ; Total fan-out ; 1009 ;
; Average fan-out ; 2.94 ; ; Average fan-out ; 2.87 ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ; ; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; |GR8RAM ; 281 (281) ; 99 ; 0 ; 69 ; 0 ; 182 (182) ; 31 (31) ; 68 (68) ; 51 (51) ; 0 (0) ; |GR8RAM ; work ; ; |GR8RAM ; 281 (281) ; 103 ; 1 ; 69 ; 0 ; 178 (178) ; 34 (34) ; 69 (69) ; 62 (62) ; 0 (0) ; |GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ;
; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ; ; Analysis & Synthesis IP Cores Summary ;
+---------------------------------------+----------------------+ +--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
; Register name ; Reason for Removal ; ; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+---------------------------------------+----------------------+ +--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
; Addr[21,22] ; Merged with Addr[23] ; ; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |GR8RAM|UFM:UFM_inst ; Z:/Repos/GR8RAM/cpld/UFM.v ;
; Total Number of Removed Registers = 2 ; ; +--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
+---------------------------------------+----------------------+
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; DRDIn ; Stuck at GND due to stuck port data_in ;
; SetFW ; Stuck at VCC due to stuck port data_in ;
; SetLim8M ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 3 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+---------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+---------------+---------------------------+----------------------------------------+
; DRDIn ; Stuck at GND ; SetFW, SetLim8M ;
; ; due to stuck port data_in ; ;
+---------------+---------------------------+----------------------------------------+
+------------------------------------------------------+ +------------------------------------------------------+
@ -215,12 +243,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Statistic ; Value ; ; Statistic ; Value ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Total registers ; 99 ; ; Total registers ; 103 ;
; Number of registers using Synchronous Clear ; 25 ; ; Number of registers using Synchronous Clear ; 25 ;
; Number of registers using Synchronous Load ; 3 ; ; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 43 ; ; Number of registers using Clock Enable ; 49 ;
; Number of registers using Preset ; 0 ; ; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
@ -244,12 +272,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ; ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|Bank[0] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|Bank[0] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[4] ; ; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[0] ;
; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |GR8RAM|IS[0] ; ; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[9] ;
; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[14] ; ; 13:1 ; 2 bits ; 16 LEs ; 12 LEs ; 4 LEs ; Yes ; |GR8RAM|DRShift ;
; 9:1 ; 4 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |GR8RAM|Addr[17] ; ; 9:1 ; 8 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |GR8RAM|Addr[20] ;
; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|SA ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|SA ;
; 8:1 ; 5 bits ; 25 LEs ; 15 LEs ; 10 LEs ; No ; |GR8RAM|SA ; ; 8:1 ; 5 bits ; 25 LEs ; 15 LEs ; 10 LEs ; No ; |GR8RAM|SA ;
; 8:1 ; 4 bits ; 20 LEs ; 12 LEs ; 8 LEs ; No ; |GR8RAM|SA ; ; 8:1 ; 4 bits ; 20 LEs ; 12 LEs ; 8 LEs ; No ; |GR8RAM|SA ;
@ -257,13 +285,26 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFM:UFM_inst" ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; ardin ; Input ; Info ; Stuck at GND ;
; oscena ; Input ; Info ; Stuck at VCC ;
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------+ +-------------------------------+
; Analysis & Synthesis Messages ; ; Analysis & Synthesis Messages ;
+-------------------------------+ +-------------------------------+
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Mar 19 06:43:50 2021 Info: Processing started: Fri Mar 19 06:57:57 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
@ -271,37 +312,40 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 2: UFM Info (12023): Found entity 2: UFM
Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: GR8RAM Info (12023): Found entity 1: GR8RAM
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(247): created implicit net for "UFMB"
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(250): created implicit net for "RTPB"
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10858): Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned Warning (10858): Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned
Warning (10858): Verilog HDL warning at gr8ram.v(230): object SetFW used but never assigned Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(252): object "UFMBr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(263): object "RefReady" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(254): object "RTPBr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(354): object "IS" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(365): object "RefReady" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18) Warning (10230): Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(125): truncated value with size 32 to match size of target (24) Warning (10230): Verilog HDL assignment warning at gr8ram.v(124): truncated value with size 32 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(126): truncated value with size 36 to match size of target (24) Warning (10230): Verilog HDL assignment warning at gr8ram.v(128): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(130): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at gr8ram.v(133): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(131): truncated value with size 36 to match size of target (16) Warning (10230): Verilog HDL assignment warning at gr8ram.v(351): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(136): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(137): truncated value with size 36 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(195): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(249): truncated value with size 32 to match size of target (3)
Warning (10030): Net "RDout" at gr8ram.v(110) has no driver or initial value, using a default initial value '0' Warning (10030): Net "RDout" at gr8ram.v(110) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "SetFW" at gr8ram.v(230) has no driver or initial value, using a default initial value '0' Warning (10030): Net "WRD[5..0]" at gr8ram.v(336) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "WRD[5..0]" at gr8ram.v(234) has no driver or initial value, using a default initial value '0' Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component"
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD[6]" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD[6]" into an OR gate
Warning (13024): Output pins are stuck at VCC or GND Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "RAdir" is stuck at VCC Warning (13410): Pin "RAdir" is stuck at VCC
Info (21057): Implemented 350 device resources after synthesis - the final resource count might be different Warning (13410): Pin "SBA[0]" is stuck at GND
Info (21057): Implemented 351 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 25 input pins Info (21058): Implemented 25 input pins
Info (21059): Implemented 28 output pins Info (21059): Implemented 28 output pins
Info (21060): Implemented 16 bidirectional pins Info (21060): Implemented 16 bidirectional pins
Info (21061): Implemented 281 logic cells Info (21061): Implemented 281 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings
Info: Peak virtual memory: 301 megabytes Info: Peak virtual memory: 301 megabytes
Info: Processing ended: Fri Mar 19 06:43:55 2021 Info: Processing ended: Fri Mar 19 06:58:03 2021
Info: Elapsed time: 00:00:05 Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05 Info: Total CPU time (on all processors): 00:00:06
+------------------------------------------+ +------------------------------------------+

2
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,4 +1,4 @@
Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
Warning (10273): Verilog HDL warning at gr8ram.v(109): extended using "x" or "z" Warning (10273): Verilog HDL warning at gr8ram.v(109): extended using "x" or "z"
Warning (10273): Verilog HDL warning at gr8ram.v(233): extended using "x" or "z" Warning (10273): Verilog HDL warning at gr8ram.v(335): extended using "x" or "z"

4
cpld/output_files/GR8RAM.map.summary
View File

@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Fri Mar 19 06:43:55 2021 Analysis & Synthesis Status : Successful - Fri Mar 19 06:58:03 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
@ -6,4 +6,4 @@ Family : MAX II
Total logic elements : 281 Total logic elements : 281
Total pins : 69 Total pins : 69
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % ) UFM blocks : 1 / 1 ( 100 % )