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Removed inhibit output

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Zane Kaminski 2020-02-26 03:14:33 -05:00
parent 76bceb089d
commit 593f5cb010
1 changed files with 3 additions and 5 deletions
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8
cpld/GR8RAM.v
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@ -1,11 +1,12 @@
module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
A, RA, nWE, D, RD, A, RA, nWE, D, RD,
nDEVSEL, nIOSEL, nIOSTRB, nINH, nDEVSEL, nIOSEL, nIOSTRB,
nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE); nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE);
/* Clock, Reset, Mode */ /* Clock, Reset, Mode */
input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs
input nRES, nMode; // Reset, mode input nRES, Mode;
input Mode;
/* PHI1 Delay */ /* PHI1 Delay */
wire [8:0] PHI1b; wire [8:0] PHI1b;
@ -57,9 +58,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
AddrLSELA ? Addr[7:0] : 8'h00; AddrLSELA ? Addr[7:0] : 8'h00;
inout [7:0] D = DOE ? Dout : 8'bZ; inout [7:0] D = DOE ? Dout : 8'bZ;
/* Inhibit output */
output nINH = 1'bZ;
/* DRAM and ROM Control Signals */ /* DRAM and ROM Control Signals */
output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSEN); // ROM chip select output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSEN); // ROM chip select
output nROE = ~nWE; // need this for flash ROM output nROE = ~nWE; // need this for flash ROM