forked from Apple-2-HW/GR8RAM
Fabbed
This commit is contained in:
Zane Kaminski
parent
9f0867fe56
commit
db594211fa
@ -1 +1,50 @@
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Recovery
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GR8RAM/LibraryCard Slinky memory map
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-----------------------------
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1 FF FFFF | |
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. .. .... | LibCrd Sect. Cache (8 MB) |
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1 80 0000 | |
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-----------------------------
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1 7F FFFF | |
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. .. .... | reserved (6 MB) |
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1 20 0000 | |
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-----------------------------
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1 1F FFFF | |
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. .. .... | LibCrd registers (1 MB) |
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1 10 0000 | |
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-----------------------------
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1 0F FFFF | |
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. .. .... | 256x IOSTRB area (512 kB) |
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1 08 0000 | |
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-----------------------------
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1 07 FFFF | |
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. .. .... | 256x IOSEL area (512 kB) |
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1 00 0000 | |
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-----------------------------
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0 FF 0000 | |
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. .. .... | RAMFactor Memory (16 MB) |
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0 00 0000 | |
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-----------------------------
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Library Card register space
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-----------------------------
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1 7F FFFF | |
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. .. .... | reserved (768 kB) |
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1 74 0000 | |
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-----------------------------
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1 73 FFFF | |
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. .. .... | Response B (64 kB) |
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1 73 0000 | |
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-----------------------------
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1 72 FFFF | |
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. .. .... | Command B (64 kB) |
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1 72 0000 | |
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-----------------------------
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1 71 FFFF | |
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. .. .... | Response A (64 kB) |
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1 71 0000 | |
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-----------------------------
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1 70 FFFF | |
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. .. .... | Command A (64 kB) |
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1 70 0000 | |
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-----------------------------
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BIN
Documentation/Placement.pdf
Normal file
BIN
Documentation/Placement.pdf
Normal file
Binary file not shown.
BIN
Documentation/Schematic.pdf
Normal file
BIN
Documentation/Schematic.pdf
Normal file
Binary file not shown.
155
GR8RAM-cache.lib
155
GR8RAM-cache.lib
@ -246,28 +246,6 @@ X A 2 100 0 70 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_D_Small_ALT
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#
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DEF Device_D_Small_ALT D 0 10 N N 1 F N
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F0 "D" -50 80 50 H V L CNN
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F1 "Device_D_Small_ALT" -150 -80 50 H V L CNN
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F2 "" 0 0 50 V I C CNN
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F3 "" 0 0 50 V I C CNN
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$FPLIST
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TO-???*
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*_Diode_*
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*SingleDiode*
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D_*
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$ENDFPLIST
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DRAW
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P 2 0 1 0 -30 -40 -30 40 N
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P 2 0 1 0 -30 0 30 0 N
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P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
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X K 1 -100 0 70 R 50 50 1 1 P
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X A 2 100 0 70 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_D_Zener_Small_ALT
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#
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DEF Device_D_Zener_Small_ALT D 0 10 N N 1 F N
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@ -384,42 +362,16 @@ X ~ 2 0 -100 30 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# GW_Logic_74125
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# GW_Logic_741G125GW
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#
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DEF GW_Logic_74125 U 0 40 Y Y 1 F N
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F0 "U" 0 450 50 H V C CNN
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F1 "GW_Logic_74125" 0 -450 50 H V C CNN
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F2 "stdpads:TSSOP-14_4.4x5mm_P0.65mm" 0 -500 50 H I C TNN
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F3 "" 0 -50 60 H I C CNN
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DRAW
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S -200 400 200 -400 0 1 10 f
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X 1~OE~ 1 -400 300 200 R 50 50 1 1 I
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X 3~OE~ 10 400 -100 200 L 50 50 1 1 I
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X 4Y 11 400 0 200 L 50 50 1 1 T
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X 4A 12 400 100 200 L 50 50 1 1 I
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X 4~OE~ 13 400 200 200 L 50 50 1 1 I
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X Vcc 14 400 300 200 L 50 50 1 1 W
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X 1A 2 -400 200 200 R 50 50 1 1 I
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X 1Y 3 -400 100 200 R 50 50 1 1 T
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X 2~OE~ 4 -400 0 200 R 50 50 1 1 I
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X 2A 5 -400 -100 200 R 50 50 1 1 I
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X 2Y 6 -400 -200 200 R 50 50 1 1 T
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X GND 7 -400 -300 200 R 50 50 1 1 W
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X 3Y 8 400 -300 200 L 50 50 1 1 T
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X 3A 9 400 -200 200 L 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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# GW_Logic_741G04GW
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#
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DEF GW_Logic_741G04GW U 0 40 Y Y 1 F N
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DEF GW_Logic_741G125GW U 0 40 Y Y 1 F N
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F0 "U" 0 250 50 H V C CNN
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F1 "GW_Logic_741G04GW" 0 -250 50 H V C CNN
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F1 "GW_Logic_741G125GW" 0 -250 50 H V C CNN
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F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
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F3 "" 0 -200 60 H I C CNN
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DRAW
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S 200 -200 -200 200 0 1 10 f
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X NC 1 -350 100 150 R 50 50 1 1 N
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X ~OE~ 1 -400 100 200 R 50 50 1 1 I
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X A 2 -400 0 200 R 50 50 1 1 I
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X GND 3 -400 -100 200 R 50 50 1 1 W
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X Y 4 400 -100 200 L 50 50 1 1 O
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@ -477,10 +429,10 @@ ENDDEF
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#
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# GW_PLD_EPM240T100
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#
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DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 L N
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DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 F N
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F0 "U" 0 50 50 H V C CNN
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F1 "GW_PLD_EPM240T100" 0 -50 50 H V C CNN
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F2 "Package_QFP:LQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
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F2 "stdpads:TQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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*QFP*P0.5mm*
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@ -605,66 +557,6 @@ X Vin 3 -450 100 200 R 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# GW_RAM_Flash-4Mx16-TSOP1-48
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#
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DEF GW_RAM_Flash-4Mx16-TSOP1-48 U 0 20 Y Y 1 F N
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F0 "U" 0 1050 50 H V C CNN
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F1 "GW_RAM_Flash-4Mx16-TSOP1-48" 0 0 50 V V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S -300 1000 300 -1700 0 1 10 f
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X GND 27 -500 -1600 200 R 50 50 0 0 W
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X VCC 37 -500 900 200 R 50 50 0 0 W
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X A15 1 -500 -800 200 R 50 50 1 1 I
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X A20 10 -500 -1300 200 R 50 50 1 1 I
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X ~WE~ 11 500 -1500 200 L 50 50 1 1 I L
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X ~RESET~ 12 500 -800 200 L 50 50 1 1 I L
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X A21 13 -500 -1400 200 R 50 50 1 1 I
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X ~WP~ 14 500 -1100 200 L 50 50 1 1 I L
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X ~BY~ 15 500 -1200 200 L 50 50 1 1 I L
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X A18 16 -500 -1100 200 R 50 50 1 1 I
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X A17 17 -500 -1000 200 R 50 50 1 1 I
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X A7 18 -500 0 200 R 50 50 1 1 I
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X A6 19 -500 100 200 R 50 50 1 1 I
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X A14 2 -500 -700 200 R 50 50 1 1 I
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X A5 20 -500 200 200 R 50 50 1 1 I
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X A4 21 -500 300 200 R 50 50 1 1 I
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X A3 22 -500 400 200 R 50 50 1 1 I
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X A2 23 -500 500 200 R 50 50 1 1 I
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X A1 24 -500 600 200 R 50 50 1 1 I
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X A0 25 -500 700 200 R 50 50 1 1 I
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X ~CS~ 26 500 -1400 200 L 50 50 1 1 I L
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X ~OE~ 28 500 -1600 200 L 50 50 1 1 I L
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X D0 29 500 900 200 L 50 50 1 1 B
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X A13 3 -500 -600 200 R 50 50 1 1 I
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X D8 30 500 100 200 L 50 50 1 1 B
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X D1 31 500 800 200 L 50 50 1 1 B
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X D9 32 500 0 200 L 50 50 1 1 B
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X D2 33 500 700 200 L 50 50 1 1 B
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X D10 34 500 -100 200 L 50 50 1 1 B
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X D3 35 500 600 200 L 50 50 1 1 B
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X D11 36 500 -200 200 L 50 50 1 1 B
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X D4 38 500 500 200 L 50 50 1 1 B
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X D12 39 500 -300 200 L 50 50 1 1 B
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X A12 4 -500 -500 200 R 50 50 1 1 I
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X D5 40 500 400 200 L 50 50 1 1 B
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X D13 41 500 -400 200 L 50 50 1 1 B
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X D6 42 500 300 200 L 50 50 1 1 B
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X D14 43 500 -500 200 L 50 50 1 1 B
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X D7 44 500 200 200 L 50 50 1 1 B
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X D15/A22 45 500 -600 200 L 50 50 1 1 B
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X GND 46 -500 -1600 200 R 50 50 1 1 W
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X ~BYTE~ 47 500 -900 200 L 50 50 1 1 I L
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X A16 48 -500 -900 200 R 50 50 1 1 I
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X A11 5 -500 -400 200 R 50 50 1 1 I
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X A10 6 -500 -300 200 R 50 50 1 1 I
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X A9 7 -500 -200 200 R 50 50 1 1 I
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X A8 8 -500 -100 200 R 50 50 1 1 I
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X A19 9 -500 -1200 200 R 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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# GW_RAM_SDRAM-16Mx16-TSOP2-54
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#
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DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
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@ -730,6 +622,26 @@ X VDDQ 9 -500 900 200 R 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# GW_RAM_SPIFlash-SO-8
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#
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DEF GW_RAM_SPIFlash-SO-8 U 0 40 Y Y 1 F N
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F0 "U" 0 350 50 H V C CNN
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F1 "GW_RAM_SPIFlash-SO-8" 0 -250 50 H V C CNN
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F2 "stdpads:Hybrid_SPIFlash_SOIC-8_SOIC-16" 0 -300 50 H I C TNN
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F3 "" 0 0 50 H I C TNN
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DRAW
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S -350 300 350 -200 0 1 10 f
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X ~CS~ 1 -550 200 200 R 50 50 1 1 I
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X DO/IO1 2 -550 100 200 R 50 50 1 1 B
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X ~WP~/IO2 3 -550 0 200 R 50 50 1 1 B
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X GND 4 -550 -100 200 R 50 50 1 1 W
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X DI/IO0 5 550 -100 200 L 50 50 1 1 B
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X CLK 6 550 0 200 L 50 50 1 1 I
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X ~HLD~/IO3 7 550 100 200 L 50 50 1 1 B
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X Vcc 8 550 200 200 L 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# Mechanical_Fiducial
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#
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DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
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@ -745,6 +657,21 @@ C 0 0 50 0 1 20 f
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ENDDRAW
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ENDDEF
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#
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# Mechanical_MountingHole
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#
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DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
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F0 "H" 0 200 50 H V C CNN
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F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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MountingHole*
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$ENDFPLIST
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DRAW
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C 0 0 50 0 1 50 N
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ENDDRAW
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ENDDEF
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#
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# Mechanical_MountingHole_Pad
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#
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DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
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Binary file not shown.
BIN
GR8RAM.4205A-gerberlite.zip
Normal file
BIN
GR8RAM.4205A-gerberlite.zip
Normal file
Binary file not shown.
31801
GR8RAM.kicad_pcb
31801
GR8RAM.kicad_pcb
File diff suppressed because it is too large
Load Diff
22
GR8RAM.pro
22
GR8RAM.pro
@ -1,4 +1,4 @@
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update=Tuesday, September 29, 2020 at 09:10:17 PM
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update=Wednesday, January 06, 2021 at 01:09:33 AM
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version=1
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last_client=kicad
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[general]
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@ -12,16 +12,6 @@ NetIExt=net
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version=1
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LibDir=
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[eeschema/libraries]
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=Pcbnew
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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@ -267,3 +257,13 @@ uViaDrill=0.1
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=Pcbnew
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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||||
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5485
GR8RAM.sch
5485
GR8RAM.sch
File diff suppressed because it is too large
Load Diff
885
cpld/GR8RAM.v
885
cpld/GR8RAM.v
@ -1,599 +1,374 @@
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module GR8RAM(C25M, PHI1, nIOSEL, nDEVSEL, nIOSTRB,
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RA, RB6, nRWE, nROE, nAOE, Adir, nRCS,
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RD, nDOE, Ddir,
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SBA, SA, nSCS, nRAS, nCAS, nSWE, DQML, DQMH, SCKE, SD,
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nRST, nPreBOD,
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module GR8RAM(C25M, PHI0, nPBOD, nBOD, nRES,
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nIOSEL, nDEVSEL, nIOSTRB,
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RA, nWEin, nWEout, Adir,
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RD, Ddir,
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DMAin, DMAout, INTin, INTout,
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nIRQout, nINHout, nDMAout, nNMIout);
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nDMA, nRDY, nNMI, nIRQ, nINH, nRESout
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SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
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nFCS, FCK, MISO, MOSI);
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/* Clock inputs */
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input C25M, PHI1;
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wire PHI0 = ~PHI1;
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/* Reset inputs */
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input nRST, nPreBOD;
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reg nRSTr0;
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/* Clock signals */
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input C25M, PHI0;
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reg PHI0r1, PHI0r2, PHI0r3;
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always @(negedge C25M) begin PHI0r1 <= PHI0; end
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always @(posedge C25M) begin
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nRSTr0 <= nRST;
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PHI0r2 <= PHI0r1; PHI0r3 <= PHI0r2;
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end
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/* Select inputs */
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/* Reset/brown-out detect inputs */
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input nRES, nPBOD, nBOD;
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reg PBODr1, PBODr2, BODr1, BODr2, RESr1, RESr2;
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always @(negedge C25M) begin
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PBODr1 <= ~nPBOD; BODr1 <= ~nBOD; RESr1 <= ~nRES;
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end
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always @(posedge C25M) begin
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PBODr2 <= PBODr1; BODr2 <= BODr1; RESr2 <= RESr1;
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end
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/* Apple IO area select signals */
|
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input nIOSEL, nDEVSEL, nIOSTRB;
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/* Synchronized select inputs */
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reg nDEVSELr0, nDEVSELr1;
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reg nIOSELr0;
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reg nIOSTRBr0;
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always @(posedge C25M) begin
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nDEVSELr0 <= nDEVSEL;
|
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nDEVSELr1 <= nDEVSELr0;
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nIOSELr0 <= nIOSEL;
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nIOSTRBr0 <= nIOSTRB;
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||||
end
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/* DEVSEL-based state counter */
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wire [9:0] DEVSELe = {DEVSELer[9:1], nDEVSELr1 && ~nDEVSELr0 && nRSTr0}
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reg [9:1] DEVSELer;
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always @(posedge C25M) begin
|
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DEVSELer[9:1] <= DEVSELe[8:0];
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||||
end
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||||
reg DEVSELr1, DEVSELr2;
|
||||
always @(negedge C25M) begin DEVSELr1 <= ~nDEVSEL; end
|
||||
always @(posedge C25M) begin DEVSELr2 <= DEVSELr1; end
|
||||
|
||||
/* Flash Control */
|
||||
output nRCS = ~((~nIOSEL || (~nIOSTRB && IOROMEN)) && CSDBEN && nRST);
|
||||
output nROE = ~nRWE;
|
||||
|
||||
/* 6502/Flash Data Bus */
|
||||
inout RD = RDOE ? Rdout : 8'bZ;
|
||||
wire RDOE = ~nDEVSEL && nRST;
|
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wire RDout =
|
||||
AddrLSelA ? Addr[7:0] :
|
||||
AddrMSelA ? Addr[15:8] :
|
||||
AddrHSelA ? Addr[23:16] :
|
||||
DataSelA ? Addr==0 ? Data0[7:0] : Data[7:0] :
|
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8'h57;
|
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output nDOE = ~((~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)) && CSDBEN && nRST);
|
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output Ddir = ~nRWE;
|
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|
||||
/* Data bus / ROM chip select delay */
|
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reg CSDBEN = 0;
|
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always @(posedge C25M, negedge nRST) begin
|
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if (~nRST) CSDBEN <= 1'b0;
|
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else CSDBEN <= ~nDEVSELr0 || ~nIOSELr0 || ~nIOSTRBr0;
|
||||
end
|
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|
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/* IOROMEN control */
|
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wire IOROMEN = IOROMEN0 ^ IOROMEN1;
|
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reg IOROMEN0 = 0;
|
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reg IOROMEN1 = 0;
|
||||
always @(negedge nIOSEL, negedge nRST) begin
|
||||
if (~nRST) IOROMEN0 <= 1'b0; // On reset, set both to 0; 0 ^ 0 == 0
|
||||
else IOROMEN0 <= ~IOROMEN1; // Enable; X ^ ~X == 1
|
||||
end
|
||||
always @(negedge nIOSTRB, negedge nRST) begin
|
||||
if (~nRST) IOROMEN1 <= 1'b0; // On reset, set both to 0; 0 ^ 0 == 0
|
||||
else if (RA[10:0] == 11'h7FF) IOROMEN1 <= IOROMEN0; // Disable; X^X==0
|
||||
end
|
||||
|
||||
/* 6502/Flash Address Bus */
|
||||
input [15:0] RA;
|
||||
input nRWE;
|
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output nAOE = 0;
|
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output Adir = 1;
|
||||
reg [3:0] RAr;
|
||||
reg nRWEr;
|
||||
always @(posedge nDEVSEL) begin
|
||||
// Latch RA and nRWE at end of DEVSEL access
|
||||
RAr[3:0] <= RA[3:0];
|
||||
nRWEr <= nRWE;
|
||||
end
|
||||
|
||||
/* Register Select Signals */
|
||||
wire AddrLSelA = RA[3:0] == 4'h0;
|
||||
wire AddrMSelA = RA[3:0] == 4'h1;
|
||||
wire AddrHSelA = RA[3:0] == 4'h2;
|
||||
wire DataSelA = RA[3:0] == 4'h3;
|
||||
wire DMAAddrLSelA = RA[3:0] == 4'h4;
|
||||
wire DMAAddrHSelA = RA[3:0] == 4'h5;
|
||||
wire DMALenLSelA = RA[3:0] == 4'h6;
|
||||
wire DMALenHSelA = RA[3:0] == 4'h7;
|
||||
|
||||
wire MagicSelA = RA[3:0] == 4'h8;
|
||||
wire CfgSelA = RA[3:0] == 4'h9;
|
||||
wire RAMMaskSelA = RA[3:0] == 4'hB;
|
||||
wire BankHSelA = RA[3:0] == 4'hE;
|
||||
wire BankLSelA = RA[3:0] == 4'hF;
|
||||
|
||||
/* SDRAM Address / Flash Bank Bus */
|
||||
output [1:0] SBA = SAmux ? SBAreg[1:0] :
|
||||
~nIOSTRB ? {
|
||||
BankC8[4], // SBA0, Bank4
|
||||
BankC8[2] // SBA1, Bank2
|
||||
} : { // IOSEL
|
||||
1'b1, // SBA0, Bank4
|
||||
1'b1 // SBA1, Bank2
|
||||
};
|
||||
output [12:0] SA = SAmux ? SAreg[12:0] :
|
||||
~nIOSTRB ? {
|
||||
SAreg[0], // SA0
|
||||
BankC8[11], // SA1, Bank11
|
||||
BankC8[8], // SA2, Bank8
|
||||
SAreg[3], // SA3
|
||||
SAreg[4], // SA4
|
||||
BankC8[7], // SA5, Bank7
|
||||
SAreg[6], // SA6
|
||||
BankC8[10], // SA7, Bank10
|
||||
BankC8[9], // SA8, Bank9
|
||||
BankC8[1], // SA9, Bank1
|
||||
BankC8[0], // SA10, Bank0
|
||||
BankC8[3], // SA11, Bank3
|
||||
BankC8[5] ^ BankCX[5] // SA12, Bank5
|
||||
} : { // IOSEL
|
||||
SAreg[0], // SA0
|
||||
1'b0, // SA1, Bank11
|
||||
1'b0, // SA2, Bank8
|
||||
SAreg[3], // SA3
|
||||
SAreg[4], // SA4
|
||||
1'b1, // SA5, Bank7
|
||||
SAreg[6], // SA6
|
||||
1'b0, // SA7, Bank10
|
||||
1'b0, // SA8, Bank9
|
||||
1'b1, // SA9, Bank1
|
||||
1'b1, // SA10, Bank0
|
||||
1'b1, // SA11, Bank3
|
||||
BankCX[5] // SA12, Bank5
|
||||
};
|
||||
output RB6 = ~nIOSTRB ? BankC8[6] ^ BankCX[6] : BankCX[6];
|
||||
reg SAmux = 1'b0;
|
||||
reg [1:0] SBAreg;
|
||||
reg [12:0] SAreg;
|
||||
|
||||
/* SDRAM Data Bus */
|
||||
inout [7:0] SD = SDOE ? WRD : 8'bZ;
|
||||
reg SDOE = 0;
|
||||
reg [7:0] WRD = 0;
|
||||
always @(posedge nDEVSEL) begin
|
||||
WRD[7:0] <= RD[7:0];
|
||||
if (nRSTr0 && DataSelA && ~nRWE && Addr==0) Data0[7:0] <= RD[7:0];
|
||||
end
|
||||
|
||||
/* SDRAM Control Bus */
|
||||
output reg nSCS = 1;
|
||||
output reg nRAS = 1;
|
||||
output reg nCAS = 1;
|
||||
output reg nSWE = 1;
|
||||
output reg DQML = 1;
|
||||
output reg DQMH = 1;
|
||||
output reg SCKE = 1;
|
||||
|
||||
/* INT/DMA in/out */
|
||||
input DMAin;
|
||||
input INTin;
|
||||
/* DMA/IRQ daisy chain */
|
||||
input DMAin, INTin;
|
||||
output DMAout = DMAin;
|
||||
output INTout = INTin;
|
||||
|
||||
/* IRQ, NMI, DMA, INH outputs (open-drain is external) */
|
||||
output nIRQ = 1;
|
||||
output nNMI = 1;
|
||||
/* Apple open-drain outputs */
|
||||
output nDMA = 1;
|
||||
output nRDY = 1;
|
||||
output nNMI = 1;
|
||||
output nIRQ = 1;
|
||||
output nINH = 1;
|
||||
output nRESout = 0;
|
||||
|
||||
/* Refresh/Init Counter */
|
||||
reg [19:0] Tick;
|
||||
/* Apple address bus */
|
||||
input [15:0] RA;
|
||||
input nWEin;
|
||||
output RAdir = 1;
|
||||
output nWEout = 1;
|
||||
reg [15:0] RAr1; reg nWEr1;
|
||||
reg [15:0] RAr2; reg nWEr2;
|
||||
reg [15:0] RAcur; reg nWEcur;
|
||||
always @(negedge C25M) begin RAr1 <= RA; nWEr1 <= nWE; end
|
||||
always @(posedge C25M) begin RAr2 <= RAr1; nWEr2 <= nWEr1; end
|
||||
always @(posedge C25M) begin
|
||||
Tick <= Tick+1;
|
||||
if (S==0 && ~PHI0r2) begin
|
||||
RAcur <= RAr2;
|
||||
nWEcur <= nWER2;
|
||||
end
|
||||
end
|
||||
reg InitDone = 0;
|
||||
|
||||
/* Apple select signals */
|
||||
wire ROMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]!=4'h0;
|
||||
wire ROMSpecRD = ROMSpecSEL && nWE;
|
||||
wire RAMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[7:4]!=4'h8 && RAcur[3:0]==4'h3;
|
||||
wire RAMSpecRD = RAMSpecSEL && nWE;
|
||||
wire RAMSpecWR = RAMSpecSEL && ~nWE;
|
||||
wire SpecRD = ROMSpecRD || RAMSpecRD;
|
||||
reg RAMRD = 0, RAMWR = 0;
|
||||
always @(posedge C25M) begin
|
||||
if (Tick[19:0]==20'hFFFFF) InitDone <= 1'b1;
|
||||
if (S==5) begin
|
||||
RAMRD <= RAMSpecRD && DEVSELr2;
|
||||
RAMWR <= RAMSpecWR && DEVSELr2;
|
||||
end else if (S==0) begin
|
||||
RAMRD <= 0;
|
||||
RAMWR <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
/* Apple data bus */
|
||||
inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0];
|
||||
reg RDdir = 1;
|
||||
reg [7:0] RDout;
|
||||
|
||||
/* SDRAM data bus */
|
||||
inout [7:0] SD = SDOE ? RD[7:0] : 8'bZ;
|
||||
reg SDOE = 0;
|
||||
|
||||
/* SDRAM address/command */
|
||||
output reg [1:0] SBA;
|
||||
output reg [12:0] SA;
|
||||
output reg RCKE = 1;
|
||||
output reg nRCS = 1;
|
||||
output reg nRAS = 1;
|
||||
output reg nCAS = 1;
|
||||
output reg nSWE = 1;
|
||||
output reg DQMH = 1;
|
||||
output reg DQML = 1;
|
||||
|
||||
/* SPI flash */
|
||||
output reg nFCS = 1;
|
||||
output reg FCK = 0;
|
||||
output reg MOSI = MOSIOE ? MOSIout : 1'bZ;
|
||||
reg MOSIOE = 0;
|
||||
reg MOSIout;
|
||||
input MISO;
|
||||
|
||||
/* State counters */
|
||||
reg [24:0] FS = 0;
|
||||
always @(posedge C25M) begin FS <= FS+1; end
|
||||
reg [2:0] S = 0;
|
||||
always @(posedge C25M) begin
|
||||
if (S==0 && PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2) S <= 1;
|
||||
else if (S==0) S <= 0;
|
||||
else S <= S+1;
|
||||
end
|
||||
reg RefWake = 0;
|
||||
|
||||
/* Refresh state */
|
||||
reg RefReady = 0;
|
||||
reg RefDone = 0;
|
||||
always @(posedge C25M) begin RefReady <= S==0; end
|
||||
always @(posedge C25M) begin
|
||||
if (FS[6:0]==7'h00) RefDone <= 0;
|
||||
else (S==0 && RefReady && RCKE && ~(PHI0r2 && ~PHI0r3)) RefDone <= 1;
|
||||
end
|
||||
|
||||
/* User-Accessible Registers */
|
||||
reg [23:0] Addr = 0;
|
||||
reg [7:0] Data = 0;
|
||||
reg [7:0] Data0 = 0;
|
||||
reg [11:0] BankC8 = 0; // Bits 9:8 are XORed with BankCX
|
||||
reg [6:5] BankCX = 0; // Bank CX is init value
|
||||
reg ExtBankEN = 0;
|
||||
/* Slinky registers */
|
||||
reg [24:0] Addr;
|
||||
wire AddrHSpecSEL = RAcur[3:0]==4'h2;
|
||||
wire AddrMSpecSEL = RAcur[3:0]==4'h1;
|
||||
wire AddrLSpecSEL = RAcur[3:0]==4'h0;
|
||||
always @(posedge C25M) begin
|
||||
if (S==7 && DEVSELr2) begin
|
||||
if (AddrHSpecSEL || AddrMSpecSEL || AddrLSpecSEL) begin
|
||||
Addr[24] <= 1'b0;
|
||||
end
|
||||
|
||||
/* Set/Increment Address Register */
|
||||
always @(posedge C25M, negedge nRST) begin
|
||||
if (~nRST) begin
|
||||
Addr <= 0;
|
||||
end else begin
|
||||
if (DEVSELe[0] && ~nRWEr) begin // Write address register
|
||||
if (RAr[3:0]==4'h0) begin // AddrL
|
||||
Addr[7:0] <= WRD[7:0];
|
||||
if (Addr[7] & ~WRD[7]) Addr[23:8] <= Addr[23:8]+1;
|
||||
end else if (RAr[3:0]==4'h1) begin // AddrM
|
||||
Addr[15:8] <= WRD[7:0];
|
||||
if (Addr[15] & ~WRD[7]) Addr[23:16] <= Addr[23:16]+1;
|
||||
end else if (RAr[3:0]==4'h2) begin // AddrH
|
||||
Addr[23:16] <= WRD[7:0];
|
||||
end
|
||||
end else if (DEVSELe[2] && RAr[3:0]==4'h3) begin // R/W data
|
||||
Addr[23:0] <= Addr[23:0]+1;
|
||||
if (AddrHSpecSEL) begin
|
||||
Addr[23:16] <= RD[7:0];
|
||||
end else if (RAMRD || RAMWR ||
|
||||
(AddrMSpecSEL && Addr[15] && ~RD[7]) ||
|
||||
(AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF)) begin
|
||||
Addr[23:16] <= Addr[23:16]+1;
|
||||
end
|
||||
|
||||
if (AddrMSpecSEL) begin
|
||||
Addr[15:8] <= RD[7:0];
|
||||
end else if (RAMRD || RAMWR ||
|
||||
(AddrLSpecSEL && Addr[7] && ~RD[7])) begin
|
||||
Addr[15:8] <= Addr[15:8]+1;
|
||||
end
|
||||
|
||||
if (AddrLSpecSEL) begin
|
||||
Addr[7:0] <= RD[7:0];
|
||||
end else if (RAMRD || RAMWR) begin
|
||||
Addr[7:0] <= Addr[7:0]+1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* Set bank */
|
||||
always @(posedge nDEVSEL, negedge nRST) begin
|
||||
if (~nRST) begin
|
||||
BankC8 <= 0;
|
||||
end else begin
|
||||
if (~nRWE) begin
|
||||
if (RAr[3:0]==4'hE && ExtBankEN) begin
|
||||
BankC8[11:10] <= WRD[3:2];
|
||||
BankC8[9:8] <= WRD[1:0] ^ BankCX[9:8];
|
||||
end else if (RAr[3:0]==4'hF) begin
|
||||
BankC8[7] <= WRD[7] & ExtBankEN;
|
||||
BankC8[6:0] <= WRD[6:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* Latch read data */
|
||||
always @(posedge C25M) begin
|
||||
if (DEVSELe[9]) Data[7:0] <= SDD[7:0];
|
||||
end
|
||||
|
||||
/* SDRAM Control */
|
||||
always @(posedge C25M) begin
|
||||
if (~InitDone) begin
|
||||
if (Tick[19:8]==12'hFFF) begin
|
||||
if (Tick[3:0]==4'h8) begin
|
||||
if (Tick[7:4]==4'h0) begin
|
||||
// PC all
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b0;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
SAreg[10] <= 1'b1; // "all"
|
||||
end else if (Tick[7:4]==4'h7) begin
|
||||
// Load mode register
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b0;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
SAreg[11] <= 1'b0; // Reserved in mode register
|
||||
end else begin
|
||||
// AREF
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
// NOP
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
SCKE <= 1'b0;
|
||||
nSCS <= 1'b1;
|
||||
if (S==0) begin
|
||||
if ((PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2 && SpecRD) ||
|
||||
(~RefReady && ~RefDone)) begin
|
||||
// NOP cken
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
end
|
||||
|
||||
// Mode register contents
|
||||
SBAreg[1:0] <= 2'b00; // Reserved
|
||||
SAreg[11] <= 1'b0; // Reserved
|
||||
SAreg[9] <= 1'b1; // "1" for single write mode
|
||||
SAreg[8] <= 1'b0; // Reserved
|
||||
SAreg[7] <= 1'b0; // "0" for not test mode
|
||||
SAreg[6:4] <= 3'b010; // "2" for CAS latency 2
|
||||
SAreg[3] <= 1'b0; // "0" for sequential burst (not used)
|
||||
SAreg[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
||||
|
||||
SAmux <= 1'b1;
|
||||
RefDone <= 1'b0;
|
||||
RefWake <= 1'b0;
|
||||
end else if (DEVSELe[0] && RAr[3:0]==4'h3) begin
|
||||
// NOP
|
||||
SCKE <= ~nRWEr;
|
||||
nSCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
SAmux <= 1'b1;
|
||||
RefWake <= 1'b0;
|
||||
end else if (DEVSELe[1] && RAr[3:0]==4'h3) begin
|
||||
// ACT
|
||||
SCKE <= ~nRWEr;
|
||||
nSCS <= nRWEr;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Row address
|
||||
SBAreg[1:0] <= Addr[23:22];
|
||||
SAreg[12] <= 1'b0;
|
||||
SAreg[11:0] <= Addr[21:10];
|
||||
|
||||
SAmux <= 1'b1;
|
||||
RefWake <= 1'b0;
|
||||
end else if (DEVSELe[2] && RAr[3:0]==4'h3) begin
|
||||
// WR/NOP
|
||||
SCKE <= ~nRWEr;
|
||||
nSCS <= nRWEr;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b0;
|
||||
DQML <= Addr[0];
|
||||
DQMH <= ~Addr[0];
|
||||
|
||||
// Column address
|
||||
SBAreg[1:0] <= Addr[23:22];
|
||||
SAreg[12:11] <= 2'b00;
|
||||
SAreg[9] <= 1'b0;
|
||||
SAreg[8:0] <= Addr[9:1];
|
||||
|
||||
// Auto-precharge only if row will increment
|
||||
SAreg[10] <= Addr[9:0]==10'h3FF;
|
||||
|
||||
SAmux <= 1'b1;
|
||||
RefWake <= 1'b0;
|
||||
end else if (DEVSELe[3] && RAr[3:0]==4'h3) begin
|
||||
// NOP
|
||||
SCKE <= ~nRWEr;
|
||||
nSCS <= nRWEr;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
SAmux <= 1'b0;
|
||||
RefWake <= 1'b0;
|
||||
end else if (DEVSELe[4] && RAr[3:0]==4'h3) begin
|
||||
// NOP (auto-precharge from previous write)
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
SAmux <= 1'b0;
|
||||
RefWake <= 1'b0;
|
||||
end else if (DEVSELe[5] && RAr[3:0]==4'h3) begin
|
||||
// ACT only if WR AP just occurred / NOP
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= ~nRWEr && ~SAreg[10];
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Row address
|
||||
SBAreg[1:0] <= Addr[23:22];
|
||||
SAreg[12] <= 1'b0;
|
||||
SAreg[11:0] <= Addr[21:10];
|
||||
|
||||
SAmux <= 1'b1;
|
||||
RefWake <= 1'b0;
|
||||
end else if (DEVSELe[6] && RAr[3:0]==4'h3) begin
|
||||
// RD
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= Addr[0];
|
||||
DQMH <= ~Addr[0];
|
||||
|
||||
// Column address
|
||||
SBAreg[1:0] <= Addr[23:22];
|
||||
SAreg[12:11] <= 2'b00;
|
||||
SAreg[10] <= 1'b1; // auto-precharge
|
||||
SAreg[9] <= 1'b0;
|
||||
SAreg[8:0] <= Addr[9:1];
|
||||
|
||||
SAmux <= 1'b1;
|
||||
RefWake <= 1'b0;
|
||||
end else if (DEVSELe[7] && RAr[3:0]==4'h3) begin
|
||||
// NOP
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
SAmux <= 1'b0;
|
||||
RefWake <= 1'b0;
|
||||
end else begin
|
||||
if (Tick[5] && ~RefDone) begin
|
||||
if (~RefWake) begin
|
||||
// NOP
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
RefWake <= 1'b1;
|
||||
end else begin
|
||||
// AREF
|
||||
SCKE <= 1'b1;
|
||||
nSCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
RefWake <= 1'b0;
|
||||
RefDone <= 1'b1;
|
||||
end
|
||||
DQML <= 1'b1;
|
||||
end else if (RefReady && ~RefDone && RCKE &&
|
||||
~(PHI0r2 && ~PHI0r3)) begin
|
||||
// AREF
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
SCKE <= 1'b0;
|
||||
nSCS <= 1'b1;
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h1) begin
|
||||
if (SpecRD) begin
|
||||
// ACT
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
|
||||
RefWake <= 1'b0;
|
||||
if (Tick[5]) RefDone <= 1'b0;
|
||||
if (RAMSpecRD) begin
|
||||
RBA[1] <= Addr[24];
|
||||
RBA[0] <= Addr[23];
|
||||
RA[12:0] <= Addr[22:10];
|
||||
end else begin
|
||||
RBA[1] <= 1'b1;
|
||||
RBA[0] <= 1'b0;
|
||||
RA[12:10] <= 3'b000;
|
||||
RA[9:2] <= Bank[7:0];
|
||||
RA[1:0] <= RAcur[11:10];
|
||||
end
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h2) begin
|
||||
if (SpecRD) begin
|
||||
// RD auto-PC
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b1;
|
||||
|
||||
SAmux <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
/* UFM Interface */
|
||||
reg ARCLK = 0; // UFM address register clock
|
||||
// UFM address register data input tied to 0
|
||||
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
|
||||
reg DRCLK = 0; // UFM data register clock
|
||||
reg DRDIn = 0; // UFM data register input
|
||||
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
|
||||
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
|
||||
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
|
||||
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
|
||||
wire DRDOut; // UFM data output
|
||||
// UFM oscillator always enabled
|
||||
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
|
||||
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
|
||||
.arclk (ARCLK),
|
||||
.ardin (1'b0),
|
||||
.arshft (ARShift),
|
||||
.drclk (DRCLK),
|
||||
.drdin (DRDIn),
|
||||
.drshft (DRShift),
|
||||
.erase (UFMErase),
|
||||
.oscena (1'b1),
|
||||
.program (UFMProgram),
|
||||
.busy (UFMBusy),
|
||||
.drdout (DRDOut),
|
||||
.osc (UFMOsc),
|
||||
.rtpbusy (RTPBusy));
|
||||
reg UFMBr = 0; // UFMBusy registered to sync with C14M
|
||||
reg RTPBr = 0; // RTPBusy registered to sync with C14M
|
||||
|
||||
reg [15:0] Cfg;
|
||||
reg CfgLoaded = 0;
|
||||
// Do nothing when Tick15:14==2'h0
|
||||
// Get ready when Tick15:14==2'h1
|
||||
// Zero AR
|
||||
// Load Cfg when Tick15:14==2'h2
|
||||
// Tick13:6 (256) - first half of UFM looked at
|
||||
// Tick5:2 (16) - 16 bits loaded from UFM
|
||||
// 0: set CfgLoaded if DRDout==1, otherwise shift DRDout into Cfg
|
||||
// 1-14: continue shifting DRDout into Cfg[15:0]
|
||||
// 15: shift last DRDout bit into Cfg[15:0] and increment AR
|
||||
// Tick1:0 (4) - 1 bit shifted
|
||||
// Do nothing when Tick15:14==2'h3
|
||||
// Set CfgLoaded too
|
||||
always @(posedge C25M) begin
|
||||
if (~CfgLoaded) begin
|
||||
if (Tick[15:14]==2'h0) begin
|
||||
// Do nothing
|
||||
ARShift <= 1;
|
||||
ARCLK <= 0;
|
||||
DRCLK <= 0;
|
||||
end else if (Tick[15:14]==2'h1) begin
|
||||
// Shift zeros into AR during first half
|
||||
if (~Tick[13]) begin
|
||||
ARShift <= 1;
|
||||
ARCLK <= Tick[1];
|
||||
end else begin
|
||||
ARShift <= 0;
|
||||
ARCLK <= 0;
|
||||
A[12:11] <= 1'b0; // don't care
|
||||
A[10] <= 1'b1; // auto-precharge
|
||||
A[9] <= 1'b0; // don't care
|
||||
if (RAMSpecRD) begin
|
||||
RBA[1] <= Addr[24];
|
||||
RBA[0] <= Addr[23];
|
||||
RA[8:0] <= Addr[9:1];
|
||||
DQMH <= ~Addr[0];
|
||||
DQML <= Addr[0];
|
||||
end else /* ROMSpecRD */ begin
|
||||
RBA[1] <= 1'b1;
|
||||
RBA[0] <= 1'b0;
|
||||
RA[8:0] <= RAcur[9:1];
|
||||
DQMH <= ~RAcur[0];
|
||||
DQML <= RAcur[0];
|
||||
end
|
||||
|
||||
// Load default config
|
||||
Cfg[15:0] <= 16'hFFFF;
|
||||
|
||||
// Load indirect into DR at end
|
||||
if (Tick[13:0]==14'h3FFC ||
|
||||
Tick[13:0]==14'h3FFD ||
|
||||
Tick[13:0]==14'h3FFE ||
|
||||
Tick[13:0]==14'h3FFF || ) begin
|
||||
DRCLK <= 1;
|
||||
end else DRCLK <= 0;
|
||||
end else if (Tick[15:14]==2'h2) begin
|
||||
// Load 16 bits into Cfg register
|
||||
if (Tick[5:2]==4'h0 && Tick[1:0]==0 && DRDout) begin
|
||||
CfgLoaded <= 1;
|
||||
end else if (Tick[1:0]==0) begin
|
||||
Cfg[15:0] <= {Cfg[14:1], DRDout};
|
||||
end
|
||||
|
||||
// Increment AR
|
||||
if (Tick[5:2]==4'hE) begin
|
||||
ARCLK <= 1;
|
||||
end else begin
|
||||
ARCLK <= 0;
|
||||
end
|
||||
|
||||
// Load indirect into DR
|
||||
if (Tick[5:2]==4'hF) begin
|
||||
DRCLK <= 1;
|
||||
end else begin
|
||||
DRCLK <= 0;
|
||||
end
|
||||
|
||||
ARShift <= 1'b0; // Only incrementing AR now
|
||||
end else if (Tick[15:14]==2'h3) begin
|
||||
// Do nothing
|
||||
ARShift <= 1;
|
||||
ARCLK <= 0;
|
||||
DRCLK <= 0;
|
||||
CfgLoaded <= 1; // in case setting at address 0xFF
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h3) begin
|
||||
if (SpecRD) begin
|
||||
// NOP cken
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h4) begin
|
||||
if (RAMSpecWR) begin
|
||||
// NOP cken
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h5) begin
|
||||
if (RAMSpecWR && DEVSELr2) begin
|
||||
// ACT
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
|
||||
DRShift <= 0; // Only reading DR during init, not writing UFM
|
||||
DRDIn <= 0;
|
||||
end else if (DEVSELe[0] && RAr[3:0]==4'h8) begin
|
||||
|
||||
end else begin
|
||||
// Do nothing
|
||||
ARShift <= 1;
|
||||
ARCLK <= 0;
|
||||
DRCLK <= 0;
|
||||
DRShift <= 0;
|
||||
DRDIn <= 0;
|
||||
BA[1] <= Addr[24];
|
||||
BA[0] <= Addr[23];
|
||||
A[12:0] <= Addr[22:10];
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (s==4'h6) begin
|
||||
if (RAMWR) begin
|
||||
// WR auto-PC
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b0;
|
||||
|
||||
BA[1] <= Addr[24];
|
||||
BA[0] <= Addr[23];
|
||||
A[12:11] <= 1'b0; // don't care
|
||||
A[10] <= 1'b1; // auto-precharge
|
||||
A[9:0] <= Addr[9:0];
|
||||
DQMH <= ~Addr[10];
|
||||
DQML <= Addr[10];
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h7) begin
|
||||
if (RAMSpecWR) begin
|
||||
// NOP cken
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge nDEVSEL, negedge nRST) begin
|
||||
if (~nRST)
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -1,37 +1,38 @@
|
||||
Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
|
||||
C38 C40 C39 C41 ,4,"10n","stdpads:C_0603","~","C57112"
|
||||
C8 C10 C11 C1 C7 C2 C3 C4 C36 C37 C5 C6 ,12,"10u","stdpads:C_0805","~","C15850"
|
||||
C9 C12 C13 C14 C15 C16 C17 C19 C20 C21 C22 C23 C18 C24 C25 C27 C28 C29 C30 C31 C26 C32 C33 C34 C35 ,25,"2u2","stdpads:C_0603","~","C23630"
|
||||
D1 ,1,"M7","stdpads:D_SMA","~","C95872"
|
||||
C38 C40 C41 ,3,"22n","stdpads:C_0603","~","C21122"
|
||||
C39 ,1,"1n","stdpads:C_0603","~","C1588"
|
||||
C8 C10 C11 C1 C7 C36 C37 C5 C6 C2 C3 C4 ,12,"10u","stdpads:C_0805","~","C15850"
|
||||
C9 C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 ,27,"2u2","stdpads:C_0603","~","C23630"
|
||||
D2 ,1,"SMBJ5.0A","stdpads:D_SMB","~","C110528"
|
||||
D3 ,1,"SS14","stdpads:D_SMA","~","C2480"
|
||||
F1 ,1,"nSMD035-16V","stdpads:BelFuse_1206","~","C70072"
|
||||
FB1 ,1,"GZ2012D601TF","stdpads:Murata_BLM21","~","C1017"
|
||||
FID1 FID2 FID3 FID4 FID5 ,5,"Fiducial","stdpads:Fiducial","~"
|
||||
D3 D1 ,2,"SS34","stdpads:D_SMA","~","C8678"
|
||||
F1 ,1,"nSMD050-16V","stdpads:BelFuse_1206","~","C70075"
|
||||
FB1 ,1,"GZ2012D101TF","stdpads:Murata_BLM21","~","C1015"
|
||||
FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
|
||||
H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
|
||||
H5 H4 H3 H2 H6 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
|
||||
H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
|
||||
J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
|
||||
J2 ,1,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
|
||||
J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
|
||||
J3 ,1,"DC in","stdpads:BOOMELE_DC-005_DC_5.5-2.0MM","~"
|
||||
J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
|
||||
Q1 ,1,"AO3401A","stdpads:SOT-23","http://www.aosmd.com/pdfs/datasheet/AO3401A.pdf","C15127"
|
||||
R1 R2 ,2,"DNP","stdpads:R_0805","~"
|
||||
R10 R16 R2 R15 R4 ,5,"2k2","stdpads:R_0603","~","C4190"
|
||||
R11 ,1,"330","stdpads:R_0603","~","C23138"
|
||||
R12 ,1,"1k","stdpads:R_0805","~","C17513"
|
||||
R13 ,1,"100","stdpads:R_0805","~","C17408"
|
||||
R18 ,1,"22k","stdpads:R_0603","~","C31850"
|
||||
R3 ,1,"3k0","stdpads:R_0603","~","C4211"
|
||||
R4 R16 ,2,"2k2","stdpads:R_0603","~","C4190"
|
||||
R7 R6 R11 R10 R17 R14 R15 ,7,"1k","stdpads:R_0603","~","C21190"
|
||||
R8 R5 ,2,"1M","stdpads:R_0603","~","C22935"
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Can't render this file because it has a wrong number of fields in line 10.
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