diff --git a/Docs.sch b/Docs.sch index 11da77b..3f0dae6 100644 --- a/Docs.sch +++ b/Docs.sch @@ -48,14 +48,10 @@ Wire Wire Line 10300 1100 10300 1000 Wire Wire Line 10000 1100 10300 1100 -Wire Wire Line - 10000 1000 10000 1100 Wire Wire Line 9700 1000 10000 1000 Wire Wire Line 9400 1100 9700 1100 -Wire Wire Line - 9400 1000 9400 1100 Wire Wire Line 9100 1000 9400 1000 Wire Wire Line @@ -92,20 +88,8 @@ Wire Wire Line 6400 1100 6700 1100 Wire Wire Line 7600 1000 7600 1100 -Wire Wire Line - 10300 1550 9450 1550 -Wire Wire Line - 8250 1450 9400 1450 -Wire Wire Line - 7350 1550 8200 1550 -Wire Wire Line - 8250 1450 8200 1550 Wire Wire Line 10300 1550 10350 1450 -Wire Wire Line - 9400 1450 9450 1550 -Wire Wire Line - 7300 1450 7350 1550 Wire Wire Line 7300 1000 7600 1000 Text Notes 6900 1100 0 40 ~ 0 @@ -114,14 +98,10 @@ Text Notes 7500 1100 0 40 ~ 0 S2 Wire Wire Line 10300 1400 10350 1300 -Wire Wire Line - 8250 1400 10300 1400 Wire Wire Line 8200 1300 8250 1400 Wire Wire Line 10300 1150 10350 1250 -Wire Wire Line - 8250 1150 10300 1150 Wire Wire Line 8200 1250 8250 1150 Text Notes 8100 1100 0 40 ~ 0 @@ -222,8 +202,6 @@ Wire Wire Line 10350 1250 10400 1250 Wire Wire Line 10350 1300 10400 1300 -Wire Wire Line - 10350 1450 10400 1450 Wire Wire Line 1350 1300 3400 1300 Wire Wire Line @@ -246,10 +224,6 @@ Wire Wire Line 3450 1150 6100 1150 Wire Wire Line 9700 1100 9700 1000 -Text Notes 900 3500 0 100 ~ 0 -State Synchronization -Text Notes 7050 3500 0 100 ~ 0 -Address Bus Routing Wire Wire Line 1600 1850 1650 1750 Wire Wire Line @@ -326,194 +300,22 @@ Wire Wire Line 6400 1900 6450 1950 Wire Wire Line 6150 1300 8200 1300 -Text Notes 3650 3900 0 100 ~ 0 -ROM / DRAM Control -Text Notes 3650 3550 0 100 ~ 0 -Refresh Skip Counter -Text Notes 3700 3650 0 50 ~ 0 -Ref[3:0] = ~S1~ ? Ref[3:0] : Ref[3:2]==3 ? 0 : Ref[3:0]+1 @ ~C7M~ -Text Notes 950 4850 0 50 ~ 0 -BankSEL = A==XXXF & DEVSEL & REGEN\nRAMSEL = A==XXX3 & DEVSEL & REGEN\nRAMSELreg = S3 ? RAMSEL : RAMSELreg;\nAddrHSEL = A==XXX2 & DEVSEL & REGEN\nAddrMSEL = A==XXX1 & DEVSEL & REGEN\nAddrLSEL = A==XXX0 & DEVSEL & REGEN\n\nREGEN = (IOSEL & S3) ? 1 : REGEN @ C7M\nIOROMEN = (A==XXFF & IOSTRB & S3) ? 0 :\n (A==XX00 & IOSEL & S3) ? 1 :\n IOROMEN @ C7M -Text Notes 900 3900 0 100 ~ 0 -Select Signals -Text Notes 950 3700 0 50 ~ 0 -PHI0reg = PHI0 @ C7M\nS[3:0] = (~PHI0~ & PHI0reg) ? 1 : S0 ? 0 : S+1 @ C7M Wire Wire Line 1650 1850 6400 1850 -Text Notes 800 3050 2 50 ~ 0 -RA -Text Notes 800 2750 2 50 ~ 0 -~CAS~ -Wire Wire Line - 2550 2750 3100 2750 -Wire Wire Line - 2500 2650 2550 2750 -Wire Wire Line - 3100 2750 3150 2650 -Wire Wire Line - 1300 2750 1350 2650 -Wire Wire Line - 7900 2750 7350 2750 -Wire Wire Line - 7900 2750 7950 2650 -Wire Wire Line - 7300 2650 7350 2750 -Wire Wire Line - 5500 2950 5550 3050 -Wire Wire Line - 5500 3050 5550 2950 -Wire Wire Line - 9100 3050 9150 2950 -Wire Wire Line - 9100 2950 9150 3050 -Wire Wire Line - 9400 2650 9450 2750 -Wire Wire Line - 4300 2950 4350 3050 -Wire Wire Line - 4300 3050 4350 2950 -Wire Wire Line - 10300 3050 10350 2950 -Wire Wire Line - 10300 2950 10350 3050 -Wire Wire Line - 9150 2950 10300 2950 -Wire Wire Line - 9150 3050 10300 3050 -Wire Wire Line - 1300 3050 1350 2950 -Wire Wire Line - 1300 2950 1350 3050 -Wire Wire Line - 1300 2950 900 2950 -Wire Wire Line - 1300 3050 900 3050 -Wire Wire Line - 4600 2650 4650 2750 -Wire Wire Line - 4900 2650 4950 2750 -Wire Wire Line - 10300 2750 10350 2650 -Wire Wire Line - 900 2750 1300 2750 -Wire Wire Line - 9700 2650 9750 2750 -Wire Wire Line - 10350 2950 10400 2950 -Wire Wire Line - 10350 3050 10400 3050 -Wire Wire Line - 5550 2950 9100 2950 -Wire Wire Line - 5550 3050 9100 3050 -Wire Wire Line - 4350 2950 5500 2950 -Wire Wire Line - 4350 3050 5500 3050 -Wire Wire Line - 4300 3050 1350 3050 -Wire Wire Line - 1350 2950 4300 2950 -Text Notes 800 2600 2 50 ~ 0 -~CAS~f -Wire Wire Line - 9400 2500 9450 2600 -Wire Wire Line - 4600 2500 4650 2600 -Wire Wire Line - 5200 2500 5250 2600 -Wire Wire Line - 6400 2600 6450 2500 -Wire Wire Line - 10000 2500 10050 2600 -Text Notes 800 2450 2 50 ~ 0 -~CAS~r -Wire Wire Line - 3100 2450 3150 2350 -Wire Wire Line - 7900 2450 7350 2450 -Wire Wire Line - 7900 2450 7950 2350 -Wire Wire Line - 7300 2350 7350 2450 -Wire Wire Line - 9700 2350 9750 2450 -Wire Wire Line - 4900 2350 4950 2450 -Wire Wire Line - 5500 2450 5550 2350 -Wire Wire Line - 10300 2450 10350 2350 -Wire Wire Line - 4950 2450 5500 2450 -Wire Wire Line - 2200 2600 2250 2500 -Wire Wire Line - 900 2600 2200 2600 -Wire Wire Line - 9750 2450 10300 2450 -Wire Wire Line - 6100 2750 6150 2650 Wire Wire Line 1600 1900 900 1900 Wire Wire Line 1600 2000 900 2000 Wire Wire Line 1350 1450 1300 1550 -Wire Wire Line - 2500 2350 2550 2450 -Wire Wire Line - 2550 2450 3100 2450 -Wire Wire Line - 10000 2900 10050 2800 -Wire Wire Line - 8850 2900 8800 2800 -Wire Wire Line - 5200 2900 5250 2800 -Wire Wire Line - 3400 2900 3450 2800 -Wire Wire Line - 2850 2900 3400 2900 -Wire Wire Line - 2800 2800 2850 2900 -Wire Wire Line - 8200 2900 8250 2800 -Wire Wire Line - 7650 2900 8200 2900 -Wire Wire Line - 7600 2800 7650 2900 -Wire Wire Line - 900 2900 1000 2900 -Wire Wire Line - 1000 2900 1050 2800 -Text Notes 800 2900 2 50 ~ 0 -~RAS~ -Text Notes 7100 3800 0 50 ~ 0 -RA[10:8] = (RAMSEL & (S4 | S5)) ? Addr[10:8] : Addr[21:19] @ C7M\nRA[7:1] = RAMSEL ? (S4 ? Addr[7:1] : Addr[18:12]) : Bank[6:0] @ C7M\nRA[0] = RAMSEL ? (S4 ? Addr[0] : Addr[11]) : A[11] @ C7M -Text Notes 3700 4850 0 50 ~ 0 -DBEN = ~S2~ & ~S3~ @ C7M\nRCS = IOSEL | (IOSTRB & IOROMEN)\nROE = R~W~\nRWE = ~R~W & (DEVSEL | IOSEL | IOSTRB)\n\nCASr = (S1 & Ref[3:0]==0) | (S5 & RAMSEL) @ C7M\nCASf = ((S5 & R~W~) | S6 | S7) & RAMSEL @ ~C7M~\n\nRASf = (S4 & RAMSEL) | (S5 & RAMSEL & ~R~W) | (S2 & Ref[3:0]==0) @ ~C7M~\nCAS0 = CASr | (CASf & DEVSEL & ~Addr[22]~)\nCAS1 = CASr | (CASf & DEVSEL & Addr[22]) -Text Notes 7100 5200 0 50 ~ 0 -RD[7:0] = (~R~W & ~RES~) ? D[7:0]: 8’bZ\nD[7:0] = (DBEN & R~W~ & ~RES~ & (DEVSEL | IOSEL | (IOSTRB & ROMEN))) ?\n AddrHSEL ? {1’b1, Addr[22:16]} : \n AddrMSEL ? Addr[15:8] : \n AddrLSEL ? Addr[7:0] : \n RD[7:0] : 8’bZ -Text Notes 7100 4500 0 50 ~ 0 -Bank[6:0] = (S6 & BankSEL & ~R~W) ? D[6:0] : Bank[6:0] @ C7M\nAddr[22:16] = (S6 & AddrHSEL & ~R~W) ? D[6:0] : Addr[22:16] @ C7M\nAddr[15:8] = (S6 & AddrMSEL & ~R~W) ? D[7:0] : Addr[15:8] @ C7M\nAddr[7:0] = (S6 & AddrLSEL & ~R~W) ? D[7:0] : Addr[7:0] @ C7M\nif (S1 & RAMSELreg) Addr[22:0]++ @ C7M -Text Notes 7050 4700 0 100 ~ 0 -Data Bus Routing -Text Notes 7050 4050 0 100 ~ 0 -6502-Accessible Registers -Wire Wire Line - 4900 2900 4950 2800 -Wire Wire Line - 9700 2900 9750 2800 Wire Wire Line 900 1550 1300 1550 Wire Wire Line 3400 1450 3450 1550 Wire Wire Line - 3900 1450 3950 1550 + 3850 1450 3900 1550 Wire Wire Line 6350 1550 6400 1450 -Wire Wire Line - 6150 1450 7300 1450 Wire Bus Line 6100 1550 6100 2250 Wire Wire Line @@ -526,10 +328,6 @@ Wire Bus Line 9100 950 9100 2200 Wire Bus Line 9700 950 9700 2200 -Wire Bus Line - 10300 850 10300 2250 -Wire Bus Line - 8200 850 8200 2250 Wire Bus Line 7300 950 7300 2200 Wire Bus Line @@ -553,11 +351,9 @@ Wire Bus Line Wire Bus Line 2500 950 2500 2200 Wire Wire Line - 3400 1450 3900 1450 + 3400 1450 3850 1450 Wire Bus Line 3400 850 3400 2250 -Text Notes 800 1700 2 50 ~ 0 -PHI0 Wire Wire Line 3400 1700 3450 1600 Wire Wire Line @@ -573,18 +369,16 @@ Wire Wire Line Wire Wire Line 8200 1700 8250 1600 Wire Wire Line - 8250 1600 10300 1600 + 10350 1700 10400 1700 Wire Wire Line - 10400 1650 10450 1650 -Wire Wire Line - 10350 1550 10400 1650 + 10300 1600 10350 1700 Wire Wire Line 5200 1000 5200 1100 Wire Wire Line 4600 1000 4600 1100 Text Notes 6300 1100 0 40 ~ 0 S7 -Text Notes 1200 6100 0 200 ~ 0 +Text Notes 2550 4900 0 200 ~ 0 Information here may be out of date,\nsuperseded by ./cpld/GR8RAM.v Wire Wire Line 1600 2000 1650 1950 @@ -596,46 +390,432 @@ Wire Wire Line 4800 2000 4750 1950 Wire Wire Line 4800 1900 4750 1950 -Wire Wire Line - 3450 1550 6350 1550 Wire Wire Line 3450 1600 6600 1600 Wire Wire Line 6200 1700 8200 1700 Wire Wire Line - 9450 2600 10400 2600 + 10000 1000 10000 1100 Wire Wire Line - 4650 2600 6400 2600 + 8850 2450 8800 2350 Wire Wire Line - 900 2500 10400 2500 + 3100 2450 3150 2350 Wire Wire Line - 4050 2900 4000 2800 + 2550 2450 3100 2450 Wire Wire Line - 1350 2650 2500 2650 + 2500 2350 2550 2450 +Text Notes 800 2450 2 50 ~ 0 +~RAS~ rd Wire Wire Line - 4000 2800 3450 2800 + 4900 2450 4950 2350 Wire Wire Line - 2800 2800 1050 2800 + 4050 2450 4000 2350 Wire Wire Line - 4650 2750 6100 2750 + 4050 2450 4900 2450 Wire Wire Line - 4050 2900 5200 2900 + 9700 2450 9750 2350 Wire Wire Line - 4950 2800 7600 2800 + 8850 2450 9700 2450 Wire Wire Line - 3150 2650 7300 2650 -Wire Wire Line - 9450 2750 10300 2750 -Wire Wire Line - 8850 2900 10000 2900 -Wire Wire Line - 7950 2650 10400 2650 -Wire Wire Line - 8250 2800 10400 2800 + 9750 2350 10400 2350 Wire Wire Line 900 2350 2500 2350 Wire Wire Line - 7950 2350 10400 2350 + 8250 1150 10300 1150 Wire Wire Line - 3150 2350 7300 2350 + 9400 1000 9400 1100 +Wire Wire Line + 900 3050 4300 3050 +Wire Wire Line + 900 2950 4300 2950 +Wire Wire Line + 900 3350 1300 3350 +Wire Wire Line + 1000 3400 900 3400 +Wire Wire Line + 1600 3500 1050 3500 +Wire Wire Line + 1000 3400 1050 3500 +Wire Wire Line + 1650 3400 2200 3400 +Wire Wire Line + 4650 3350 5500 3350 +Wire Wire Line + 5550 3950 9700 3950 +Wire Wire Line + 5550 3850 9700 3850 +Wire Wire Line + 10300 3950 9750 3950 +Wire Wire Line + 9750 3850 10300 3850 +Wire Wire Line + 9450 3350 10300 3350 +Wire Wire Line + 9750 3050 10400 3050 +Wire Wire Line + 9750 2950 10400 2950 +Wire Wire Line + 9700 3050 9150 3050 +Wire Wire Line + 9150 2950 9700 2950 +Wire Wire Line + 9700 2950 9750 3050 +Wire Wire Line + 10350 3250 10400 3250 +Wire Wire Line + 10300 3350 10350 3250 +Wire Wire Line + 10050 3500 10400 3500 +Wire Wire Line + 10000 3400 10050 3500 +Wire Wire Line + 9450 3350 9400 3250 +Wire Wire Line + 5250 3500 5800 3500 +Wire Wire Line + 7300 3250 7350 3350 +Text Notes 800 3500 2 50 ~ 0 +~CAS~ wr +Wire Wire Line + 2250 3500 2800 3500 +Wire Wire Line + 2200 3400 2250 3500 +Wire Wire Line + 2800 3500 2850 3400 +Wire Wire Line + 1600 3500 1650 3400 +Wire Wire Line + 7600 3500 7050 3500 +Wire Wire Line + 7600 3500 7650 3400 +Wire Wire Line + 7000 3400 7050 3500 +Wire Wire Line + 5200 3400 5250 3500 +Wire Wire Line + 5800 3500 5850 3400 +Wire Wire Line + 4650 3350 4600 3250 +Text Notes 800 3350 2 50 ~ 0 +~RAS~ wr +Wire Wire Line + 1300 3350 1350 3250 +Wire Wire Line + 7350 3350 7900 3350 +Wire Wire Line + 7900 3350 7950 3250 +Wire Wire Line + 2500 3250 2550 3350 +Wire Wire Line + 2550 3350 3100 3350 +Wire Wire Line + 3100 3350 3150 3250 +Wire Wire Line + 5500 3350 5550 3250 +Wire Wire Line + 10350 3950 10400 3950 +Wire Wire Line + 10350 3850 10400 3850 +Wire Wire Line + 1300 3950 900 3950 +Wire Wire Line + 1300 3850 900 3850 +Wire Wire Line + 1300 3850 1350 3950 +Wire Wire Line + 1300 3950 1350 3850 +Wire Wire Line + 10300 3850 10350 3950 +Wire Wire Line + 10300 3950 10350 3850 +Wire Wire Line + 4900 3950 4950 3850 +Wire Wire Line + 4900 3850 4950 3950 +Wire Wire Line + 9700 3850 9750 3950 +Wire Wire Line + 9700 3950 9750 3850 +Wire Wire Line + 5500 3950 5550 3850 +Wire Wire Line + 5500 3850 5550 3950 +Text Notes 800 3950 2 50 ~ 0 +RA wr +Wire Wire Line + 9700 3050 9750 2950 +Wire Wire Line + 4300 3050 4350 2950 +Wire Wire Line + 4300 2950 4350 3050 +Wire Wire Line + 9100 2950 9150 3050 +Wire Wire Line + 9100 3050 9150 2950 +Wire Wire Line + 4900 3050 4950 2950 +Wire Wire Line + 4900 2950 4950 3050 +Text Notes 800 3050 2 50 ~ 0 +RA rd +Wire Wire Line + 6100 2600 6150 2500 +Wire Wire Line + 2250 2600 2800 2600 +Wire Wire Line + 2200 2500 2250 2600 +Wire Wire Line + 2800 2600 2850 2500 +Wire Wire Line + 1300 2600 1350 2500 +Wire Wire Line + 7600 2600 7050 2600 +Wire Wire Line + 7600 2600 7650 2500 +Wire Wire Line + 7000 2500 7050 2600 +Wire Wire Line + 9400 2500 9450 2600 +Wire Wire Line + 4600 2500 4650 2600 +Wire Wire Line + 900 2600 1300 2600 +Wire Wire Line + 1350 2500 2200 2500 +Wire Wire Line + 4650 2600 6100 2600 +Text Notes 800 2600 2 50 ~ 0 +~CAS~ rd +Text Notes 800 2750 2 50 ~ 0 +~CAS~r rd +Text Notes 800 2900 2 50 ~ 0 +~CAS~f rd +Text Notes 800 3650 2 50 ~ 0 +~CAS~r wr +Text Notes 800 3800 2 50 ~ 0 +~CAS~f wr +Wire Wire Line + 8250 1400 10300 1400 +Wire Wire Line + 8650 1450 8700 1550 +Wire Bus Line + 8200 850 8200 2250 +Wire Wire Line + 6150 1450 8650 1450 +Wire Wire Line + 3450 1550 6350 1550 +Wire Bus Line + 10300 1600 10300 2250 +Wire Wire Line + 8200 1450 8250 1550 +Wire Wire Line + 8250 1550 10300 1550 +Wire Wire Line + 10300 1550 10400 1550 +Wire Bus Line + 10300 850 10300 1600 +Wire Wire Line + 6150 2500 7000 2500 +Wire Wire Line + 5850 3400 7000 3400 +Wire Wire Line + 5550 3250 7300 3250 +Wire Wire Line + 4950 2350 7300 2350 +Wire Wire Line + 7300 2350 7350 2450 +Wire Wire Line + 7350 2450 7900 2450 +Wire Wire Line + 7900 2450 7950 2350 +Wire Wire Line + 7650 2500 9400 2500 +Wire Wire Line + 7950 2350 8800 2350 +Wire Wire Line + 7650 3400 10000 3400 +Wire Wire Line + 7950 3250 9400 3250 +Wire Wire Line + 3150 2350 4000 2350 +Wire Wire Line + 2850 2500 4600 2500 +Wire Wire Line + 7300 2750 7350 2650 +Wire Wire Line + 2500 2750 2550 2650 +Wire Wire Line + 9700 2650 9750 2750 +Wire Wire Line + 4900 2650 4950 2750 +Wire Wire Line + 900 2750 2500 2750 +Wire Wire Line + 5200 2900 5250 2800 +Wire Wire Line + 2250 2900 2800 2900 +Wire Wire Line + 2200 2800 2250 2900 +Wire Wire Line + 2800 2900 2850 2800 +Wire Wire Line + 7600 2900 7050 2900 +Wire Wire Line + 7600 2900 7650 2800 +Wire Wire Line + 7000 2800 7050 2900 +Wire Wire Line + 9400 2800 9450 2900 +Wire Wire Line + 4600 2800 4650 2900 +Wire Wire Line + 10000 2900 10050 2800 +Wire Wire Line + 4650 2900 5200 2900 +Wire Wire Line + 9450 2900 10000 2900 +Wire Wire Line + 7650 2800 9400 2800 +Wire Wire Line + 2850 2800 4600 2800 +Wire Wire Line + 900 2800 2200 2800 +Wire Wire Line + 4950 2750 7300 2750 +Wire Wire Line + 2550 2650 4900 2650 +Wire Wire Line + 5250 2800 7000 2800 +Wire Wire Line + 10050 2800 10400 2800 +Wire Wire Line + 9750 2750 10400 2750 +Wire Wire Line + 7350 2650 9700 2650 +Wire Wire Line + 2250 3800 2800 3800 +Wire Wire Line + 2200 3700 2250 3800 +Wire Wire Line + 2800 3800 2850 3700 +Wire Wire Line + 7600 3800 7050 3800 +Wire Wire Line + 7600 3800 7650 3700 +Wire Wire Line + 7000 3700 7050 3800 +Wire Wire Line + 900 3700 2200 3700 +Wire Wire Line + 5800 3800 5850 3700 +Wire Wire Line + 5200 3700 5250 3800 +Wire Wire Line + 5250 3800 5800 3800 +Wire Wire Line + 5850 3700 7000 3700 +Wire Wire Line + 2850 3700 5200 3700 +Wire Wire Line + 10000 3700 10050 3800 +Wire Wire Line + 10050 3800 10400 3800 +Wire Wire Line + 7650 3700 10000 3700 +Wire Wire Line + 900 3550 10400 3550 +Wire Wire Line + 2500 3250 1350 3250 +Wire Wire Line + 3150 3250 4600 3250 +Wire Wire Line + 2850 3400 5200 3400 +Wire Wire Line + 9450 2600 10300 2600 +Wire Wire Line + 10350 2500 10400 2500 +Wire Wire Line + 10300 2600 10350 2500 +Wire Wire Line + 4950 3850 5500 3850 +Wire Wire Line + 5500 3950 4950 3950 +Wire Wire Line + 1350 3850 4900 3850 +Wire Wire Line + 1350 3950 4900 3950 +Wire Wire Line + 4900 2950 4350 2950 +Wire Wire Line + 4350 3050 4900 3050 +Wire Wire Line + 4950 3050 9100 3050 +Wire Wire Line + 4950 2950 9100 2950 +Wire Wire Line + 8600 1450 8650 1550 +Wire Wire Line + 8550 1450 8600 1550 +Wire Wire Line + 8500 1450 8550 1550 +Wire Wire Line + 8450 1450 8500 1550 +Wire Wire Line + 8400 1450 8450 1550 +Wire Wire Line + 8300 1450 8350 1550 +Wire Wire Line + 8350 1450 8400 1550 +Wire Wire Line + 8250 1450 8300 1550 +Wire Wire Line + 3800 1450 3850 1550 +Wire Wire Line + 3750 1450 3800 1550 +Wire Wire Line + 3700 1450 3750 1550 +Wire Wire Line + 3650 1450 3700 1550 +Wire Wire Line + 3600 1450 3650 1550 +Wire Wire Line + 3550 1450 3600 1550 +Wire Wire Line + 3500 1450 3550 1550 +Wire Wire Line + 3450 1450 3500 1550 +Wire Wire Line + 6300 1550 6350 1450 +Wire Wire Line + 6250 1550 6300 1450 +Wire Wire Line + 6150 1550 6200 1450 +Wire Wire Line + 6200 1550 6250 1450 +Wire Wire Line + 10350 1450 10400 1450 +Wire Wire Line + 10350 1550 10400 1450 +Wire Wire Line + 10350 1600 10400 1700 +Wire Wire Line + 8250 1600 10400 1600 +Wire Wire Line + 6550 1600 6600 1700 +Wire Wire Line + 6500 1600 6550 1700 +Wire Wire Line + 6450 1600 6500 1700 +Wire Wire Line + 6400 1600 6450 1700 +Wire Wire Line + 6350 1600 6400 1700 +Wire Wire Line + 6250 1600 6300 1700 +Wire Wire Line + 6200 1600 6250 1700 +Wire Wire Line + 6300 1600 6350 1700 +Text Notes 800 1700 2 50 ~ 0 +PHI0d $EndSCHEMATC diff --git a/GR8RAM.pdf b/GR8RAM.pdf index 8b4cbd2..c6ead9a 100644 Binary files a/GR8RAM.pdf and b/GR8RAM.pdf differ diff --git a/GR8RAM.pro b/GR8RAM.pro index 7bc8f05..68ae8b9 100644 --- a/GR8RAM.pro +++ b/GR8RAM.pro @@ -1,4 +1,4 @@ -update=Sunday, October 13, 2019 at 01:11:09 AM +update=Friday, October 18, 2019 at 03:04:35 PM version=1 last_client=kicad [general] diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..a5f69d5 --- /dev/null +++ b/LICENSE @@ -0,0 +1,27 @@ +Copyright (c) 2019, Garrett's Workshop +All rights reserved. + +Redistribution and use in source, binary, and manufactued forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code and design files must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary or manufactured form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + or hardware must display the following acknowledgement: + This product includes software and hardware developed by Garrett's Workshop. +4. Neither the name of Garrett's Workshop nor the + names of its contributors may be used to endorse or promote products + derived from this software or hardware without specific prior written permission. + +THIS SOFTWARE AND HARDWARE IS PROVIDED BY GARRETT'S WORKSHOP ''AS IS'' AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL GARRETT'S WORKSHOP BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE AND HARDWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE \ No newline at end of file diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf old mode 100755 new mode 100644 diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws index c08b644..64a4f37 100755 Binary files a/cpld/GR8RAM.qws and b/cpld/GR8RAM.qws differ diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 5bae5a2..559b23a 100755 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -69,8 +69,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, output nROE = ~nWE; // need this for flash ROM output nRWE = nWE | (nDEVSEL & nIOSEL & nIOSTRB); // for ROM & DRAM output nRAS = ~(RASr | RASf); - output nCAS0 = ~(CAS0r | (CASf & RAMSEL & ~Addr[22])); // DRAM CAS bank 0 - output nCAS1 = ~(CAS1r | (CASf & RAMSEL & Addr[22])); // DRAM CAS bank 1 + output nCAS0 = ~(CAS0f | (CASr & RAMSEL & ~Addr[22])); // DRAM CAS bank 0 + output nCAS1 = ~(CAS1f | (CASr & RAMSEL & Addr[22])); // DRAM CAS bank 1 /* 6502-accessible Registers */ reg [7:0] Bank = 0; // Bank register for ROM access @@ -80,12 +80,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0; /* CAS rising/falling edge components */ - // These are combined to create the CAS outputs. - reg CAS0r = 1'b0; - reg CAS1r = 1'b0; - reg CASf = 0; - reg RASr = 0; - reg RASf = 0; + reg CASr = 0, CAS0f = 0, CAS1f = 0; + reg RASr = 0, RASf = 0; /* State Counters */ reg PHI1reg = 0; // Saved PHI1 at last rising clock edge @@ -129,7 +125,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, S==7 ? 3'h7 : S+1; // Refresh counter allows DRAM refresh once every 13 cycles - if (S==3) Ref <= (Ref[3:2] == 2'b11) ? 4'h0 : Ref+1; + if (S==3) Ref <= (Ref[3:2]==2'b11) ? 4'h0 : Ref+1; // Disable IOSTRB ROM when accessing 0xCFFF. if (S==3 & ~nIOSTRB & A[10:0]==11'h7FF) IOROMEN <= 1'b0; @@ -175,8 +171,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, Addr[23:16] <= Addr[23:16]+1; end - // Set register in middle of S5 if accessed. - if (S==5) begin + // Set register in middle of S6 if accessed. + if (S==6) begin if (BankWR) Bank[7:0] <= D[7:0]; // Bank if (SetWR) FullIOEN <= D[7:0] == 8'hE5; @@ -194,38 +190,30 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, /* DRAM RAS/CAS */ always @(posedge C7M, negedge nRES) begin if (~nRES) begin - RASr <= 1'b0; - ASel <= 1'b0; - CAS0r <= 1'b0; - CAS1r <= 1'b0; + RASr <= 1'b0; ASel <= 1'b0; CASr <= 1'b0; end else begin - // RAS already asserted in middle of S4, - // so hold RAS through S5 - RASr <= (S==4 & RAMSEL); + RASr <= (S==1 & Ref==0) | // Refresh + (S==4 & RAMSEL & nWE) | // Read: Early RAS + (S==5 & RAMSEL & ~nWE); // Write: Late RAS // Multiplex DRAM address in at end of S4 through S6. - ASel = RAMSEL & (S==4 | S==5); + ASel = (RAMSEL & nWE & S==4) | // Read: mux address early + (RAMSEL & ~nWE & S==5); // Write: mux address late - // Refresh at end of S1 (i.e. through S2) - // CAS whenever RAM seleced - CAS0r <= (S==1 & Ref==0) | (S==5 & RAMSEL & ~Addr[22]); - - // Refresh at end of S1 (i.e. through S2) - // CAS whenever RAM seleced - CAS1r <= (S==1 & Ref==0) | (S==5 & RAMSEL & Addr[22]); + // Read: long, early CAS, gated later by RAMSEL + CASr <= (RAMSEL & ~nWE & (S==5 | S==6 | S==7)); end end - always @(negedge C7M_2, negedge nRES) begin - if (~nRES) begin RASf <= 1'b0; CASf <= 1'b0; + always @(negedge C7M, negedge nRES) begin + if (~nRES) begin RASf <= 1'b0; CAS0f <= 1'b0; CAS1f <= 1'b0; end else begin - // Refresh in S2 - // Row activate in S4 when accessing RAM - // Hold RAS in S5 when not doing late CAS for write. - RASf <= (S==2 & Ref==0) | (RAMSEL & (S==4 | (S==5 /*& ~nWE*/))); + RASf <= (S==4 & RAMSEL & nWE) | // Read: Early RAS + (S==5 & RAMSEL & ~nWE); // Write: Late RAS - // CASf gated by nDEVSEL; no need to predicate on RAMSEL. - // Early CAS in S5 for read operations. - CASf <= (S==5 & nWE) | (S==6) | (S==7); + CAS0f <= (S==1 & Ref==0) | // Refresh + (S==6 & RAMSEL & ~Addr[22] & ~nWE); // Write: Late CAS + CAS1f <= (S==1 & Ref==0) | // Refresh + (S==6 & RAMSEL & Addr[22] & ~nWE); // Write: Late CAS end end endmodule diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 03d7ce8..4a51f9a 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index 58fd575..1f03815 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(1).cnf.cdb b/cpld/db/GR8RAM.(1).cnf.cdb index 06500e7..61ebbcf 100755 Binary files a/cpld/db/GR8RAM.(1).cnf.cdb and b/cpld/db/GR8RAM.(1).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(1).cnf.hdb b/cpld/db/GR8RAM.(1).cnf.hdb index dcda520..998b154 100755 Binary files a/cpld/db/GR8RAM.(1).cnf.hdb and b/cpld/db/GR8RAM.(1).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(10).cnf.cdb b/cpld/db/GR8RAM.(10).cnf.cdb deleted file mode 100755 index d0d7d07..0000000 Binary files a/cpld/db/GR8RAM.(10).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(10).cnf.hdb b/cpld/db/GR8RAM.(10).cnf.hdb deleted file mode 100755 index 9e876a0..0000000 Binary files a/cpld/db/GR8RAM.(10).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(11).cnf.cdb b/cpld/db/GR8RAM.(11).cnf.cdb deleted file mode 100755 index 6be5881..0000000 Binary files a/cpld/db/GR8RAM.(11).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(11).cnf.hdb b/cpld/db/GR8RAM.(11).cnf.hdb deleted file mode 100755 index 79507bc..0000000 Binary files a/cpld/db/GR8RAM.(11).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(12).cnf.cdb b/cpld/db/GR8RAM.(12).cnf.cdb deleted file mode 100755 index 3909e38..0000000 Binary files a/cpld/db/GR8RAM.(12).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(12).cnf.hdb b/cpld/db/GR8RAM.(12).cnf.hdb deleted file mode 100755 index 79507bc..0000000 Binary files a/cpld/db/GR8RAM.(12).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(13).cnf.cdb b/cpld/db/GR8RAM.(13).cnf.cdb deleted file mode 100755 index 9d100ca..0000000 Binary files a/cpld/db/GR8RAM.(13).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(13).cnf.hdb b/cpld/db/GR8RAM.(13).cnf.hdb deleted file mode 100755 index 2d9bb73..0000000 Binary files a/cpld/db/GR8RAM.(13).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(14).cnf.cdb b/cpld/db/GR8RAM.(14).cnf.cdb deleted file mode 100755 index 8eb47e8..0000000 Binary files a/cpld/db/GR8RAM.(14).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(14).cnf.hdb b/cpld/db/GR8RAM.(14).cnf.hdb deleted file mode 100755 index c0a9d09..0000000 Binary files a/cpld/db/GR8RAM.(14).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(2).cnf.cdb b/cpld/db/GR8RAM.(2).cnf.cdb index 3feb6ee..28cf338 100755 Binary files a/cpld/db/GR8RAM.(2).cnf.cdb and b/cpld/db/GR8RAM.(2).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(2).cnf.hdb b/cpld/db/GR8RAM.(2).cnf.hdb index ececb3c..3650ddf 100755 Binary files a/cpld/db/GR8RAM.(2).cnf.hdb and b/cpld/db/GR8RAM.(2).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(3).cnf.cdb b/cpld/db/GR8RAM.(3).cnf.cdb index a562bf0..1fd43af 100755 Binary files a/cpld/db/GR8RAM.(3).cnf.cdb and b/cpld/db/GR8RAM.(3).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(3).cnf.hdb b/cpld/db/GR8RAM.(3).cnf.hdb index 2d9bb73..ff23662 100755 Binary files a/cpld/db/GR8RAM.(3).cnf.hdb and b/cpld/db/GR8RAM.(3).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(4).cnf.cdb b/cpld/db/GR8RAM.(4).cnf.cdb index 4e3346a..e5f1873 100755 Binary files a/cpld/db/GR8RAM.(4).cnf.cdb and b/cpld/db/GR8RAM.(4).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(4).cnf.hdb b/cpld/db/GR8RAM.(4).cnf.hdb index 6cae88f..cd35397 100755 Binary files a/cpld/db/GR8RAM.(4).cnf.hdb and b/cpld/db/GR8RAM.(4).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(5).cnf.cdb b/cpld/db/GR8RAM.(5).cnf.cdb index d476ffa..b03acd1 100755 Binary files a/cpld/db/GR8RAM.(5).cnf.cdb and b/cpld/db/GR8RAM.(5).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(5).cnf.hdb b/cpld/db/GR8RAM.(5).cnf.hdb index 6cae88f..cd35397 100755 Binary files a/cpld/db/GR8RAM.(5).cnf.hdb and b/cpld/db/GR8RAM.(5).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(6).cnf.cdb b/cpld/db/GR8RAM.(6).cnf.cdb index 264d04a..549e341 100755 Binary files a/cpld/db/GR8RAM.(6).cnf.cdb and b/cpld/db/GR8RAM.(6).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(6).cnf.hdb b/cpld/db/GR8RAM.(6).cnf.hdb index 86ab305..1eca760 100755 Binary files a/cpld/db/GR8RAM.(6).cnf.hdb and b/cpld/db/GR8RAM.(6).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(7).cnf.cdb b/cpld/db/GR8RAM.(7).cnf.cdb index 1c9ee3a..2197967 100755 Binary files a/cpld/db/GR8RAM.(7).cnf.cdb and b/cpld/db/GR8RAM.(7).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(7).cnf.hdb b/cpld/db/GR8RAM.(7).cnf.hdb index 76e8cba..0e2f064 100755 Binary files a/cpld/db/GR8RAM.(7).cnf.hdb and b/cpld/db/GR8RAM.(7).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(8).cnf.cdb b/cpld/db/GR8RAM.(8).cnf.cdb index 8b471bf..6a5ae79 100755 Binary files a/cpld/db/GR8RAM.(8).cnf.cdb and b/cpld/db/GR8RAM.(8).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(8).cnf.hdb b/cpld/db/GR8RAM.(8).cnf.hdb index 71408d2..02f9293 100755 Binary files a/cpld/db/GR8RAM.(8).cnf.hdb and b/cpld/db/GR8RAM.(8).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(9).cnf.cdb b/cpld/db/GR8RAM.(9).cnf.cdb deleted file mode 100755 index 8a926a3..0000000 Binary files a/cpld/db/GR8RAM.(9).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(9).cnf.hdb b/cpld/db/GR8RAM.(9).cnf.hdb deleted file mode 100755 index 28674a2..0000000 Binary files a/cpld/db/GR8RAM.(9).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.ace_cmp.cdb b/cpld/db/GR8RAM.ace_cmp.cdb index 4b86b24..daa5866 100755 Binary files a/cpld/db/GR8RAM.ace_cmp.cdb and b/cpld/db/GR8RAM.ace_cmp.cdb differ diff --git a/cpld/db/GR8RAM.ace_cmp.hdb b/cpld/db/GR8RAM.ace_cmp.hdb index 05bc474..141b6d6 100755 Binary files a/cpld/db/GR8RAM.ace_cmp.hdb and b/cpld/db/GR8RAM.ace_cmp.hdb differ diff --git a/cpld/db/GR8RAM.acvq.rdb b/cpld/db/GR8RAM.acvq.rdb new file mode 100755 index 0000000..c8cc1a6 Binary files /dev/null and b/cpld/db/GR8RAM.acvq.rdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 95d4743..cd64c88 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,5 +1,5 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571014478456 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571014478457 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 13 20:54:38 2019 " "Processing started: Sun Oct 13 20:54:38 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571014478457 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571014478457 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571014478457 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571014478586 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571014478743 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 13 20:54:38 2019 " "Processing ended: Sun Oct 13 20:54:38 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571014478743 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571014478743 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571014478743 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571014478743 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571425321919 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571425321919 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 18 15:02:01 2019 " "Processing started: Fri Oct 18 15:02:01 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571425321919 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571425321919 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571425321919 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571425324153 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571425324622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 18 15:02:04 2019 " "Processing ended: Fri Oct 18 15:02:04 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571425324622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571425324622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571425324622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571425324622 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index 5535136..78ae4cd 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index c994ecd..daa5866 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index 8f9b529..141b6d6 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 0aaadd2..d53b01f 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index bb82b8a..1fbf81c 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.db_info b/cpld/db/GR8RAM.db_info index 25b80cb..74daac8 100755 --- a/cpld/db/GR8RAM.db_info +++ b/cpld/db/GR8RAM.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Sun Oct 13 20:54:29 2019 +Creation_Time = Fri Oct 18 15:01:17 2019 diff --git a/cpld/db/GR8RAM.eco.cdb b/cpld/db/GR8RAM.eco.cdb index 1d5bd0c..325d843 100755 Binary files a/cpld/db/GR8RAM.eco.cdb and b/cpld/db/GR8RAM.eco.cdb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index f35646a..2584916 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,3 +1,3 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571014477034 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571014477052 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571014477434 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 13 20:54:37 2019 " "Processing ended: Sun Oct 13 20:54:37 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571014477434 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571014477434 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571014477434 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571014477434 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571425319684 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571425319700 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571425320231 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 18 15:02:00 2019 " "Processing ended: Fri Oct 18 15:02:00 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571425320231 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571425320231 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571425320231 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571425320231 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index a336be0..ce97121 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -1,7 +1,6 @@ |GR8RAM C7M => always1.IN0 -C7M => CAS1r.CLK -C7M => CAS0r.CLK +C7M => CASr.CLK C7M => RASr.CLK C7M => ASel.CLK C7M => CSDBEN.CLK @@ -16,7 +15,7 @@ C7M => S[1].CLK C7M => S[2].CLK C7M => PHI0seen.CLK C7M => PHI1reg.CLK -C7M_2 => always3.IN0 +C7M_2 => ~NO_FANOUT~ Q3 => ~NO_FANOUT~ PHI0in => ~NO_FANOUT~ PHI1in => comb.IN0 @@ -81,7 +80,8 @@ nWE => comb.IN0 nWE => comb.IN0 nWE => comb.IN0 nWE => comb.IN1 -nWE => CASf.IN1 +nWE => RASr.IN1 +nWE => ASel.IN0 D[0] <> D[0] D[1] <> D[1] D[2] <> D[2] diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index 7182c18..c0cdcfb 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.ipinfo b/cpld/db/GR8RAM.ipinfo index fa2304d..6ff9cf3 100755 Binary files a/cpld/db/GR8RAM.ipinfo and b/cpld/db/GR8RAM.ipinfo differ diff --git a/cpld/db/GR8RAM.lpc.rdb b/cpld/db/GR8RAM.lpc.rdb index adf8589..f46ce48 100755 Binary files a/cpld/db/GR8RAM.lpc.rdb and b/cpld/db/GR8RAM.lpc.rdb differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index d6d2da7..83fd4b3 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index 9907caf..ac5a460 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index ff618fd..9cf6e44 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,33 +1,33 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571014473956 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571014473956 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 13 20:54:33 2019 " "Processing started: Sun Oct 13 20:54:33 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571014473956 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571014473956 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571014473956 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571014474336 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571014474390 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571014474391 ""} -{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(195) " "Verilog HDL information at GR8RAM.v(195): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 195 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1571014474391 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571014474392 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571014474392 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571014474549 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474551 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(127) " "Verilog HDL assignment warning at GR8RAM.v(127): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 127 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474552 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474553 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(164) " "Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474553 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(169) " "Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474554 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(175) " "Verilog HDL assignment warning at GR8RAM.v(175): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 175 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474554 "|GR8RAM"} -{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571014474704 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 175 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571014474704 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474808 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474808 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571014474808 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571014474839 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474861 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474941 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474958 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474976 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474993 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014475008 ""} -{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1571014475152 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1571014475152 ""} -{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1571014475258 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1571014475258 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1571014475258 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1571014475471 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571014475472 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571014475472 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1571014475472 ""} { "Info" "ICUT_CUT_TM_MCELLS" "105 " "Implemented 105 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1571014475472 ""} { "Info" "ICUT_CUT_TM_SEXPS" "2 " "Implemented 2 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1571014475472 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571014475472 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1571014475667 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571014475712 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 13 20:54:35 2019 " "Processing ended: Sun Oct 13 20:54:35 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571014475712 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571014475712 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571014475712 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571014475712 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571425306699 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571425306715 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 18 15:01:46 2019 " "Processing started: Fri Oct 18 15:01:46 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571425306715 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571425306715 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571425306715 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571425310715 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571425310840 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571425310840 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(191) " "Verilog HDL information at GR8RAM.v(191): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 191 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1571425310840 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571425310856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571425310856 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571425311215 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(123) " "Verilog HDL assignment warning at GR8RAM.v(123): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 123 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(128) " "Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 128 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(160) " "Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(165) " "Verilog HDL assignment warning at GR8RAM.v(165): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 165 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(171) " "Verilog HDL assignment warning at GR8RAM.v(171): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"} +{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311543 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571425311543 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311559 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 165 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311559 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311559 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 171 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311559 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571425311559 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311965 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425311965 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425311965 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425311965 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571425311965 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571425312246 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312465 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312653 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312653 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312903 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425313121 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425313121 ""} +{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1571425313559 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1571425313559 ""} +{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1571425313762 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1571425313762 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1571425313762 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1571425314121 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "167 " "Implemented 167 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571425314137 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571425314137 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1571425314137 ""} { "Info" "ICUT_CUT_TM_MCELLS" "105 " "Implemented 105 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1571425314137 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1571425314137 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571425314137 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1571425314418 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "308 " "Peak virtual memory: 308 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571425314559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 18 15:01:54 2019 " "Processing ended: Fri Oct 18 15:01:54 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571425314559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571425314559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571425314559 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571425314559 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 8de912e..3bc96c8 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index 284bc1b..83a6aa8 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.pti_db_list.ddb b/cpld/db/GR8RAM.pti_db_list.ddb index 89aa9b4..61ca8da 100755 Binary files a/cpld/db/GR8RAM.pti_db_list.ddb and b/cpld/db/GR8RAM.pti_db_list.ddb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index ecea7f4..1414cf3 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index 461e2b1..0d729c3 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index bcfd05c..2c428f3 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb index bf4c983..e6e4232 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg_swap.cdb and b/cpld/db/GR8RAM.rtlv_sg_swap.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index 907198a..93bc30e 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index c741de1..80f576c 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sld_design_entry.sci b/cpld/db/GR8RAM.sld_design_entry.sci index 1d6d60f..754b594 100755 Binary files a/cpld/db/GR8RAM.sld_design_entry.sci and b/cpld/db/GR8RAM.sld_design_entry.sci differ diff --git a/cpld/db/GR8RAM.sld_design_entry_dsc.sci b/cpld/db/GR8RAM.sld_design_entry_dsc.sci index 1d6d60f..754b594 100755 Binary files a/cpld/db/GR8RAM.sld_design_entry_dsc.sci and b/cpld/db/GR8RAM.sld_design_entry_dsc.sci differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index aeb7ec3..c6ee32d 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,22 +1,22 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571014479898 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571014479899 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 13 20:54:39 2019 " "Processing started: Sun Oct 13 20:54:39 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571014479899 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571014479899 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571014479899 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571014479975 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571014480068 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571014480077 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571014480080 ""} -{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1571014480114 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571014480132 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571014480132 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480133 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480133 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480133 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571014480135 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1571014480150 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2074.000 C7M " " -47.500 -2074.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571014480165 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571014480170 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -468.000 C7M " " -4.500 -468.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1571014480251 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571014480272 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571014480273 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571014480340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 13 20:54:40 2019 " "Processing ended: Sun Oct 13 20:54:40 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571014480340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571014480340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571014480340 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571014480340 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571425328372 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571425328388 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 18 15:02:06 2019 " "Processing started: Fri Oct 18 15:02:06 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571425328388 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571425328388 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571425328388 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571425328497 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571425330310 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571425330325 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571425330325 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1571425330403 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571425330450 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571425330450 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330450 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330450 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571425330466 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1571425330560 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2169.500 C7M " " -47.500 -2169.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571425330622 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571425330638 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330653 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330653 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -486.000 C7M " " -4.500 -486.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330653 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571425330653 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1571425330794 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571425330872 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571425330872 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "259 " "Peak virtual memory: 259 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571425331044 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 18 15:02:11 2019 " "Processing ended: Fri Oct 18 15:02:11 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571425331044 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571425331044 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571425331044 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571425331044 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index ef0fd24..a62dbe0 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.15_slow.tdb b/cpld/db/GR8RAM.sta_cmp.15_slow.tdb index e9a2969..424e955 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.15_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.15_slow.tdb differ diff --git a/cpld/db/GR8RAM.tis_db_list.ddb b/cpld/db/GR8RAM.tis_db_list.ddb index 91bbe10..42a925d 100755 Binary files a/cpld/db/GR8RAM.tis_db_list.ddb and b/cpld/db/GR8RAM.tis_db_list.ddb differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info index 432dd94..56b0461 100755 --- a/cpld/db/GR8RAM.tmw_info +++ b/cpld/db/GR8RAM.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:08 -start_analysis_synthesis:s:00:00:04-start_full_compilation +start_full_compilation:s:00:00:26 +start_analysis_synthesis:s:00:00:10-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:02-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation +start_fitter:s:00:00:05-start_full_compilation +start_assembler:s:00:00:05-start_full_compilation +start_timing_analyzer:s:00:00:06-start_full_compilation diff --git a/cpld/db/add_sub_rnh.tdf b/cpld/db/add_sub_rnh.tdf index 9106a37..9dbea30 100644 --- a/cpld/db/add_sub_rnh.tdf +++ b/cpld/db/add_sub_rnh.tdf @@ -1,5 +1,5 @@ --lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END -- Copyright (C) 1991-2013 Altera Corporation diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 87e67ad..3982b9f 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 9e575cb..03274d9 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,6 +1,6 @@ Assembler report for GR8RAM -Sun Oct 13 20:54:38 2019 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Fri Oct 18 15:02:04 2019 +Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -10,7 +10,7 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof + 5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof 6. Assembler Messages @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Oct 13 20:54:38 2019 ; +; Assembler Status ; Successful - Fri Oct 18 15:02:04 2019 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; @@ -73,39 +73,39 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+----------+---------------+ -+--------------------------------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------------------------------+ -; File Name ; -+--------------------------------------------------------------------+ -; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; -+--------------------------------------------------------------------+ ++----------------------------------------------+ +; Assembler Generated Files ; ++----------------------------------------------+ +; File Name ; ++----------------------------------------------+ +; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ; ++----------------------------------------------+ -+----------------------------------------------------------------------------------------------+ -; Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; -+----------------+-----------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------------------------------+ -; Device ; EPM7128SLC84-15 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x0017D17D ; -+----------------+-----------------------------------------------------------------------------+ ++------------------------------------------------------------------------+ +; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ; ++----------------+-------------------------------------------------------+ +; Option ; Setting ; ++----------------+-------------------------------------------------------+ +; Device ; EPM7128SLC84-15 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x0017D399 ; ++----------------+-------------------------------------------------------+ +--------------------+ ; Assembler Messages ; +--------------------+ Info: ******************************************************************* -Info: Running Quartus II 64-Bit Assembler +Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Oct 13 20:54:38 2019 + Info: Processing started: Fri Oct 18 15:02:01 2019 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115030): Assembler is generating device programming files -Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 4522 megabytes - Info: Processing ended: Sun Oct 13 20:54:38 2019 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 +Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 277 megabytes + Info: Processing ended: Fri Oct 18 15:02:04 2019 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 3a6a2f0..8e5ac79 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Sun Oct 13 20:54:40 2019 +Fri Oct 18 15:02:11 2019 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 0238351..4d8c530 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,6 +1,6 @@ Fitter report for GR8RAM -Sun Oct 13 20:54:37 2019 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Fri Oct 18 15:02:00 2019 +Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -9,27 +9,26 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 1. Legal Notice 2. Fitter Summary 3. Fitter Settings - 4. Parallel Compilation - 5. Pin-Out File - 6. Fitter Resource Usage Summary - 7. Input Pins - 8. Output Pins - 9. Bidir Pins - 10. All Package Pins - 11. I/O Standard - 12. Dedicated Inputs I/O - 13. Output Pin Default Load For Reported TCO - 14. Fitter Resource Utilization by Entity - 15. Control Signals - 16. Global & Other Fast Signals - 17. Non-Global High Fan-Out Signals - 18. Other Routing Usage Summary - 19. LAB External Interconnect - 20. LAB Macrocells - 21. Shareable Expander - 22. Logic Cell Interconnection - 23. Fitter Device Options - 24. Fitter Messages + 4. Pin-Out File + 5. Fitter Resource Usage Summary + 6. Input Pins + 7. Output Pins + 8. Bidir Pins + 9. All Package Pins + 10. I/O Standard + 11. Dedicated Inputs I/O + 12. Output Pin Default Load For Reported TCO + 13. Fitter Resource Utilization by Entity + 14. Control Signals + 15. Global & Other Fast Signals + 16. Non-Global High Fan-Out Signals + 17. Other Routing Usage Summary + 18. LAB External Interconnect + 19. LAB Macrocells + 20. Shareable Expander + 21. Logic Cell Interconnection + 22. Fitter Device Options + 23. Fitter Messages @@ -55,8 +54,8 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Sun Oct 13 20:54:37 2019 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Fitter Status ; Successful - Fri Oct 18 15:02:00 2019 ; +; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; @@ -87,21 +86,10 @@ applicable agreement for further details. +----------------------------------------------------------------------------+-----------------------+---------------+ -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 8 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin. +The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------------------------------------------------+ @@ -111,19 +99,19 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp +------------------------------+--------------------+ ; Logic cells ; 105 / 128 ( 82 % ) ; ; Registers ; 54 / 128 ( 42 % ) ; -; Number of pterms used ; 267 ; +; Number of pterms used ; 272 ; ; I/O pins ; 65 / 68 ( 96 % ) ; ; -- Clock pins ; 2 / 2 ( 100 % ) ; ; -- Dedicated input pins ; 2 / 2 ( 100 % ) ; ; ; ; ; Global signals ; 2 ; -; Shareable expanders ; 2 / 128 ( 2 % ) ; +; Shareable expanders ; 1 / 128 ( < 1 % ) ; ; Parallel expanders ; 0 / 120 ( 0 % ) ; ; Cells using turbo bit ; 16 / 128 ( 13 % ) ; ; Maximum fan-out ; 54 ; -; Highest non-global fan-out ; 54 ; -; Total fan-out ; 862 ; -; Average fan-out ; 5.01 ; +; Highest non-global fan-out ; 53 ; +; Total fan-out ; 866 ; +; Average fan-out ; 5.06 ; +------------------------------+--------------------+ @@ -148,8 +136,8 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp ; A[7] ; 5 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; ; A[8] ; 9 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; ; A[9] ; 10 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; C7M ; 83 ; -- ; -- ; 52 ; 0 ; yes ; no ; TTL ; User ; -; C7M_2 ; 84 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ; +; C7M ; 83 ; -- ; -- ; 54 ; 0 ; yes ; no ; TTL ; User ; +; C7M_2 ; 84 ; -- ; -- ; 0 ; 0 ; no ; no ; TTL ; User ; ; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; ; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ; ; Q3 ; 6 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; @@ -158,7 +146,7 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp ; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ; ; nMode ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ; ; nRES ; 1 ; -- ; -- ; 54 ; 0 ; yes ; no ; TTL ; User ; -; nWE ; 20 ; -- ; 2 ; 10 ; 0 ; no ; no ; TTL ; User ; +; nWE ; 20 ; -- ; 2 ; 15 ; 0 ; no ; no ; TTL ; User ; +---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ @@ -357,18 +345,17 @@ Note: User assignments will override these defaults. The user specified values a ; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ; ; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ; ; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ; -; BankWR_MC ; LC102 ; 8 ; Clock enable ; no ; -- ; -- ; -; C7M ; PIN_83 ; 52 ; Clock ; yes ; On ; -- ; -; C7M_2 ; PIN_84 ; 2 ; Clock ; no ; -- ; -- ; -; PHI1b9_MC ; LC123 ; 5 ; Clock enable ; no ; -- ; -- ; -; REGEN ; LC36 ; 7 ; Clock enable ; no ; -- ; -- ; -; S[0] ; LC122 ; 50 ; Clock enable ; no ; -- ; -- ; -; S[1] ; LC124 ; 53 ; Clock enable ; no ; -- ; -- ; -; S[2] ; LC117 ; 54 ; Clock enable ; no ; -- ; -- ; +; BankWR_MC ; LC110 ; 8 ; Clock enable ; no ; -- ; -- ; +; C7M ; PIN_83 ; 54 ; Clock ; yes ; On ; -- ; +; PHI1b9_MC ; LC41 ; 5 ; Clock enable ; no ; -- ; -- ; +; REGEN ; LC98 ; 7 ; Clock enable ; no ; -- ; -- ; +; S[0] ; LC128 ; 52 ; Clock enable ; no ; -- ; -- ; +; S[1] ; LC118 ; 51 ; Clock enable ; no ; -- ; -- ; +; S[2] ; LC113 ; 53 ; Clock enable ; no ; -- ; -- ; ; nDEVSEL ; PIN_21 ; 16 ; Clock enable ; no ; -- ; -- ; ; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ; ; nRES ; PIN_1 ; 54 ; Async. clear ; yes ; On ; -- ; -; nWE ; PIN_20 ; 10 ; Clock enable ; no ; -- ; -- ; +; nWE ; PIN_20 ; 15 ; Clock enable ; no ; -- ; -- ; +-----------+----------+---------+--------------+--------+----------------------+------------------+ @@ -377,7 +364,7 @@ Note: User assignments will override these defaults. The user specified values a +------+----------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +------+----------+---------+----------------------+------------------+ -; C7M ; PIN_83 ; 52 ; On ; -- ; +; C7M ; PIN_83 ; 54 ; On ; -- ; ; nRES ; PIN_1 ; 54 ; On ; -- ; +------+----------+---------+----------------------+------------------+ @@ -387,31 +374,32 @@ Note: User assignments will override these defaults. The user specified values a +-------------------------------+---------+ ; Name ; Fan-Out ; +-------------------------------+---------+ -; S[2] ; 54 ; -; S[1] ; 53 ; -; S[0] ; 50 ; +; S[2] ; 53 ; +; S[0] ; 52 ; +; S[1] ; 51 ; ; nDEVSEL ; 16 ; +; nWE ; 15 ; ; A[3] ; 15 ; ; A[2] ; 15 ; ; A[1] ; 15 ; ; A[0] ; 15 ; ; nIOSEL ; 13 ; ; nIOSTRB ; 12 ; -; IncAddrM ; 11 ; ; Addr[8] ; 11 ; ; Addr[0] ; 11 ; ; ASel ; 11 ; -; nWE ; 10 ; +; IncAddrL ; 11 ; +; IncAddrM ; 10 ; ; Addr[9] ; 10 ; ; Addr[1] ; 10 ; ; Addr[16] ; 10 ; -; IncAddrL ; 10 ; ; IncAddrH ; 9 ; ; Addr[10] ; 9 ; ; Addr[17] ; 9 ; ; Addr[2] ; 9 ; ; AddrLWR_MC ; 9 ; ; AddrMWR_MC ; 9 ; +; RAMSEL_MC ; 9 ; ; D[7]~7 ; 8 ; ; FullIOEN ; 8 ; ; Addr[11] ; 8 ; @@ -420,7 +408,6 @@ Note: User assignments will override these defaults. The user specified values a ; Bank[0] ; 8 ; ; BankWR_MC ; 8 ; ; AddrHWR_MC ; 8 ; -; RAMSEL_MC ; 8 ; ; RDOE~1 ; 8 ; ; DOE~5 ; 8 ; ; Addr[22] ; 7 ; @@ -458,10 +445,9 @@ Note: User assignments will override these defaults. The user specified values a ; PHI0seen ; 3 ; ; PHI1reg ; 3 ; ; PHI1in ; 2 ; -; C7M_2 ; 2 ; ; Addr[23] ; 2 ; ; Bank[6] ; 2 ; -; CASf ; 2 ; +; CASr ; 2 ; ; RD[7]~7 ; 1 ; ; RD[6]~6 ; 1 ; ; RD[5]~5 ; 1 ; @@ -487,18 +473,17 @@ Note: User assignments will override these defaults. The user specified values a ; RA~79 ; 1 ; ; RA~73 ; 1 ; ; Bank[7] ; 1 ; -; IncAddrH~9 ; 1 ; ; IncAddrM~9 ; 1 ; ; comb~38 ; 1 ; ; comb~34 ; 1 ; -; CAS1r ; 1 ; -; CAS0r ; 1 ; +; CAS0f ; 1 ; +; CAS1f ; 1 ; ; RA~68 ; 1 ; ; RA~65 ; 1 ; ; RA~62 ; 1 ; ; comb~31 ; 1 ; -; RASf ; 1 ; ; RASr ; 1 ; +; RASf ; 1 ; ; comb~29 ; 1 ; ; PHI1b8_MC ; 1 ; ; PHI1b7_MC ; 1 ; @@ -536,15 +521,15 @@ Note: User assignments will override these defaults. The user specified values a ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ ; Output enables ; 2 / 6 ( 33 % ) ; -; PIA buffers ; 211 / 288 ( 73 % ) ; -; PIAs ; 249 / 288 ( 86 % ) ; +; PIA buffers ; 206 / 288 ( 72 % ) ; +; PIAs ; 241 / 288 ( 84 % ) ; +-----------------------------+--------------------+ +-----------------------------------------------------------------------------+ ; LAB External Interconnect ; +-----------------------------------------------+-----------------------------+ -; LAB External Interconnects (Average = 31.13) ; Number of LABs (Total = 8) ; +; LAB External Interconnects (Average = 30.13) ; Number of LABs (Total = 8) ; +-----------------------------------------------+-----------------------------+ ; 0 - 2 ; 0 ; ; 3 - 5 ; 0 ; @@ -555,9 +540,8 @@ Note: User assignments will override these defaults. The user specified values a ; 18 - 20 ; 0 ; ; 21 - 23 ; 0 ; ; 24 - 26 ; 0 ; -; 27 - 29 ; 1 ; -; 30 - 32 ; 6 ; -; 33 - 35 ; 1 ; +; 27 - 29 ; 3 ; +; 30 - 32 ; 5 ; +-----------------------------------------------+-----------------------------+ @@ -575,138 +559,138 @@ Note: User assignments will override these defaults. The user specified values a ; 6 ; 0 ; ; 7 ; 0 ; ; 8 ; 0 ; -; 9 ; 1 ; -; 10 ; 1 ; +; 9 ; 2 ; +; 10 ; 0 ; ; 11 ; 1 ; ; 12 ; 1 ; ; 13 ; 0 ; ; 14 ; 0 ; -; 15 ; 1 ; -; 16 ; 3 ; +; 15 ; 0 ; +; 16 ; 4 ; +-----------------------------------------+-----------------------------+ +-------------------------------------------------------------------------------+ ; Shareable Expander ; +-------------------------------------------------+-----------------------------+ -; Number of shareable expanders (Average = 0.25) ; Number of LABs (Total = 2) ; +; Number of shareable expanders (Average = 0.13) ; Number of LABs (Total = 1) ; +-------------------------------------------------+-----------------------------+ -; 0 ; 6 ; -; 1 ; 2 ; +; 0 ; 7 ; +; 1 ; 1 ; +-------------------------------------------------+-----------------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Logic Cell Interconnection ; -+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; LAB ; Logic Cell ; Input ; Output ; -+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[1], S[2], S[0], Addr[11], IncAddrM, Addr[10], Addr[9], Addr[8] ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~73 ; -; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[7]~120, Addr[7], IncAddrM, RA~108 ; -; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~101 ; -; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ; -; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[1], S[2], S[0], Addr[9], IncAddrM, Addr[8] ; Dout[1]~84, Addr[9], Addr[10], Addr[11], RA~65, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; -; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~87 ; -; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[1], S[2], S[0], Addr[10], IncAddrM, Addr[9], Addr[8] ; Dout[2]~90, Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RA~68, Addr[15], IncAddrH ; -; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[1], S[2], S[0], Addr[12], IncAddrM, Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[4]~102, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~120 ; -; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[1], S[2], S[0], Addr[13], IncAddrM, Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[5]~108, Addr[13], Addr[14], Addr[15], IncAddrH, RA~79 ; -; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~79 ; -; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[1], S[2], S[0], Addr[14], IncAddrM, Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[6]~114, Addr[14], Addr[15], IncAddrH, RA~80 ; -; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[1], S[2], S[0], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], Addr[11], RA~62, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; -; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], IncAddrL ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~120 ; -; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[1], S[2], S[0], Addr[15], IncAddrM, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[7]~120, Addr[15], IncAddrH, RA~87 ; -; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[2], S[1], S[0], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~73 ; -; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~94 ; -; B ; LC17 ; ; nINH ; -; B ; LC18 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~108 ; -; B ; LC32 ; C7M, nRES, D[7], AddrHWR_MC, S[2], S[1], S[0], Addr[23], IncAddrH, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[7]~120, Addr[23] ; -; B ; LC26 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[1], S[0], IncAddrM, IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrM, Addr[15], IncAddrH~9, IncAddrH ; -; B ; LC28 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~101, RA~108 ; -; B ; LC24 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[1], S[0], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], CAS0r, CAS1r, comb~34, comb~38, Addr[23] ; -; B ; LC29 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[1], S[0], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~68, Addr[22], Addr[23] ; -; B ; LC19 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~94, RA~101, RA~108 ; -; B ; LC22 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~87, RA~94, RA~101, RA~108 ; -; B ; LC27 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~62, Addr[20], Addr[21], Addr[22], Addr[23] ; -; B ; LC30 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~80, RA~87, RA~94, RA~101, RA~108 ; -; B ; LC21 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~101 ; -; B ; LC23 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108 ; -; B ; LC31 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~108 ; -; B ; LC20 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ; -; B ; LC25 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[1], S[0], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~65, Addr[21], Addr[22], Addr[23] ; -; C ; LC33 ; PHI1b4_MC ; PHI1b6_MC ; -; C ; LC42 ; PHI1b2_MC ; PHI1b4_MC ; -; C ; LC34 ; PHI1b5_MC ; PHI1b7_MC ; -; C ; LC47 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~94 ; -; C ; LC38 ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4] ; D[4] ; -; C ; LC36 ; C7M, nRES, S[0], nIOSEL, S[2], S[1] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN ; -; C ; LC45 ; RD[7], nDEVSEL, A[0], A[1], A[2], A[3], Addr[15], Addr[23], Addr[7] ; D[7] ; -; C ; LC43 ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6] ; D[6] ; -; C ; LC35 ; PHI1b1_MC ; PHI1b3_MC ; -; C ; LC40 ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5] ; D[5] ; -; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ; -; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ; -; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ; -; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ; -; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ; -; D ; LC53 ; Addr[22], CASf, RAMSEL_MC, CAS0r ; nCAS0 ; -; D ; LC51 ; Addr[22], CASf, RAMSEL_MC, CAS1r ; nCAS1 ; -; D ; LC50 ; PHI1b0_MC ; PHI1b2_MC ; -; D ; LC54 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~29 ; -; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ; -; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ; -; E ; LC74 ; C7M, nRES, S[0], RAMSEL_MC, S[2], S[1] ; comb~31 ; -; E ; LC79 ; C7M, nRES, IncAddrL, S[0], S[1], RAMSEL_MC, S[2] ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ; -; E ; LC65 ; PHI1b6_MC ; PHI1b8_MC ; -; E ; LC68 ; C7M, nRES, RAMSEL_MC, S[2], S[1] ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ; -; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ; -; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ; -; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ; -; E ; LC71 ; PHI1b7_MC ; PHI1b9_MC ; -; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ; -; E ; LC67 ; nWE ; nROE ; -; F ; LC90 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ; -; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ; -; F ; LC93 ; RASr, RASf ; nRAS ; -; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ; -; F ; LC89 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ; -; F ; LC87 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ; -; F ; LC81 ; PHI1b3_MC ; PHI1b5_MC ; -; F ; LC94 ; D[7] ; RD[7] ; -; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ; -; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ; -; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ; -; G ; LC103 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; -; G ; LC111 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23] ; -; G ; LC108 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; ASel, IncAddrL, RASr, RASf, CAS0r, CAS1r, comb~34, comb~38 ; -; G ; LC110 ; C7M, nRES, S[0], nIOSEL, S[2], S[1], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~29 ; -; G ; LC112 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ; -; G ; LC105 ; D[3] ; RD[3] ; -; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ; -; G ; LC99 ; D[6] ; RD[6] ; -; G ; LC97 ; D[5] ; RD[5] ; -; G ; LC101 ; D[4] ; RD[4] ; -; G ; LC98 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[0], S[2], S[1], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ; -; G ; LC107 ; D[2] ; RD[2] ; -; G ; LC109 ; D[1] ; RD[1] ; -; G ; LC102 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ; -; G ; LC106 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ; -; H ; LC117 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, CASf, lpm_counter:Ref_rtl_0|dffs[1], ASel, IncAddrL, RASr, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASf, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0r, CAS1r, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH~9, IncAddrH, Addr[23], Bank[7], FullIOEN ; -; H ; LC122 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, CASf, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, RASr, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASf, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0r, CAS1r, Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ; -; H ; LC128 ; nRES, S[2], S[1], nWE, S[0], C7M_2 ; comb~34, comb~38 ; -; H ; LC113 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASf, CAS0r, CAS1r ; -; H ; LC123 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ; -; H ; LC126 ; C7M, nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], Addr[22], RAMSEL_MC ; comb~34 ; -; H ; LC125 ; C7M, nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], Addr[22], RAMSEL_MC ; comb~38 ; -; H ; LC116 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASf, CAS0r, CAS1r ; -; H ; LC118 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASf, CAS0r, CAS1r ; -; H ; LC119 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASf, CAS0r, CAS1r ; -; H ; LC120 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ; -; H ; LC115 ; D[0] ; RD[0] ; -; H ; LC121 ; nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], RAMSEL_MC, C7M_2 ; comb~31 ; -; H ; LC124 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, CASf, lpm_counter:Ref_rtl_0|dffs[1], ASel, IncAddrL, RASr, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASf, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0r, CAS1r, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH~9, IncAddrH, Addr[23], Bank[7], FullIOEN ; -; H ; LC127 ; PHI1in ; PHI1b1_MC ; -; H ; LC114 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[2], S[0], S[1], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM, IncAddrH~9, IncAddrH ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], IncAddrH, Addr[23] ; -+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Logic Cell Interconnection ; ++-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; LAB ; Logic Cell ; Input ; Output ; ++-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ; +; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~120 ; +; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~101 ; +; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], Addr[11], RA~62, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; +; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~87 ; +; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~79 ; +; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~73 ; +; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~94 ; +; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~120, Addr[7], IncAddrM, RA~108 ; +; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], IncAddrM, Addr[9], Addr[8] ; Dout[2]~90, Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RA~68, Addr[15], IncAddrH ; +; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], IncAddrM, Addr[8] ; Dout[1]~84, Addr[9], Addr[10], Addr[11], RA~65, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; +; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], IncAddrM, Addr[10], Addr[9], Addr[8] ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~73 ; +; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], IncAddrM, Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[6]~114, Addr[14], Addr[15], IncAddrH, RA~80 ; +; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], IncAddrM, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[7]~120, Addr[15], IncAddrH, RA~87 ; +; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], IncAddrM, Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[5]~108, Addr[13], Addr[14], Addr[15], IncAddrH, RA~79 ; +; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], IncAddrM, Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[4]~102, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~120 ; +; B ; LC26 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~87, RA~94, RA~101, RA~108 ; +; B ; LC20 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~101 ; +; B ; LC28 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108 ; +; B ; LC24 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~108 ; +; B ; LC25 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ; +; B ; LC22 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], CAS1f, CAS0f, comb~34, comb~38, Addr[23] ; +; B ; LC19 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~101, RA~108 ; +; B ; LC27 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[1], S[2], S[0], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], IncAddrH, Addr[23] ; +; B ; LC18 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~68, Addr[22], Addr[23] ; +; B ; LC30 ; C7M, nRES, D[7], AddrHWR_MC, S[2], S[0], S[1], Addr[23], IncAddrH, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[7]~120, Addr[23] ; +; B ; LC31 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~94, RA~101, RA~108 ; +; B ; LC17 ; ; nINH ; +; B ; LC23 ; PHI1b0_MC ; PHI1b2_MC ; +; B ; LC21 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~65, Addr[21], Addr[22], Addr[23] ; +; B ; LC32 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~80, RA~87, RA~94, RA~101, RA~108 ; +; B ; LC29 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~62, Addr[20], Addr[21], Addr[22], Addr[23] ; +; C ; LC38 ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4] ; D[4] ; +; C ; LC40 ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5] ; D[5] ; +; C ; LC43 ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6] ; D[6] ; +; C ; LC39 ; PHI1b4_MC ; PHI1b6_MC ; +; C ; LC36 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ; +; C ; LC48 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ; +; C ; LC41 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ; +; C ; LC33 ; PHI1in ; PHI1b1_MC ; +; C ; LC45 ; RD[7], nDEVSEL, A[0], A[1], A[2], A[3], Addr[15], Addr[23], Addr[7] ; D[7] ; +; C ; LC37 ; PHI1b7_MC ; PHI1b9_MC ; +; C ; LC35 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ; +; C ; LC34 ; PHI1b3_MC ; PHI1b5_MC ; +; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ; +; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ; +; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ; +; D ; LC56 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ; +; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ; +; D ; LC63 ; PHI1b6_MC ; PHI1b8_MC ; +; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ; +; D ; LC53 ; Addr[22], CASr, RAMSEL_MC, CAS0f ; nCAS0 ; +; D ; LC51 ; Addr[22], CASr, RAMSEL_MC, CAS1f ; nCAS1 ; +; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ; +; E ; LC78 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~29 ; +; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ; +; E ; LC67 ; nWE ; nROE ; +; E ; LC71 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ; +; E ; LC68 ; C7M, nRES, D[0], AddrHWR_MC, S[1], S[2], Addr[16], S[0], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~94 ; +; E ; LC79 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~108 ; +; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ; +; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ; +; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ; +; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ; +; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ; +; F ; LC94 ; D[7] ; RD[7] ; +; F ; LC87 ; PHI1b1_MC ; PHI1b3_MC ; +; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ; +; F ; LC89 ; PHI1b5_MC ; PHI1b7_MC ; +; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ; +; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ; +; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ; +; F ; LC93 ; RASr, RASf ; nRAS ; +; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ; +; G ; LC99 ; D[6] ; RD[6] ; +; G ; LC97 ; D[5] ; RD[5] ; +; G ; LC101 ; D[4] ; RD[4] ; +; G ; LC107 ; D[2] ; RD[2] ; +; G ; LC109 ; D[1] ; RD[1] ; +; G ; LC112 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ; +; G ; LC110 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ; +; G ; LC100 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ; +; G ; LC111 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; +; G ; LC108 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23] ; +; G ; LC106 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; IncAddrL, CASr, ASel, RASf, RASr, CAS1f, CAS0f, comb~34, comb~38 ; +; G ; LC102 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[0], S[2], S[1], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ; +; G ; LC103 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~29 ; +; G ; LC98 ; C7M, nRES, nIOSEL, S[2], S[1], S[0] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN ; +; G ; LC105 ; D[3] ; RD[3] ; +; H ; LC114 ; PHI1b2_MC ; PHI1b4_MC ; +; H ; LC115 ; D[0] ; RD[0] ; +; H ; LC116 ; C7M, nRES, nWE, S[0], RAMSEL_MC, S[2], S[1] ; comb~31 ; +; H ; LC125 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0], Addr[22], nWE, RAMSEL_MC ; comb~38 ; +; H ; LC122 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0], Addr[22], nWE, RAMSEL_MC ; comb~34 ; +; H ; LC120 ; C7M, nRES, nWE, S[0], RAMSEL_MC, S[2], S[1] ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ; +; H ; LC119 ; C7M, nRES, S[1], S[2], nWE, RAMSEL_MC, S[0] ; comb~34, comb~38 ; +; H ; LC126 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ; +; H ; LC121 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[1], S[0], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrM, Addr[15], IncAddrH ; +; H ; LC123 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ; +; H ; LC124 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ; +; H ; LC127 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ; +; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], CASr, Addr[16], ASel, RASf, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ; +; H ; LC118 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], CASr, Addr[16], ASel, RASf, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ; +; H ; LC128 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], CASr, Addr[16], ASel, RASf, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ; +; H ; LC117 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0], nWE, RAMSEL_MC ; comb~31 ; ++-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------+ @@ -729,10 +713,10 @@ Note: User assignments will override these defaults. The user specified values a +-----------------+ Warning (20028): Parallel compilation is not licensed and has been disabled Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM" -Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 4708 megabytes - Info: Processing ended: Sun Oct 13 20:54:37 2019 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 +Info: Quartus II 32-bit Fitter was successful. 0 errors, 1 warning + Info: Peak virtual memory: 287 megabytes + Info: Processing ended: Fri Oct 18 15:02:00 2019 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:04 diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index d2e5ea7..2e657a1 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,5 +1,5 @@ -Fitter Status : Successful - Sun Oct 13 20:54:37 2019 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Fitter Status : Successful - Fri Oct 18 15:02:00 2019 +Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX7000S diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index d90af59..4a69498 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,6 +1,6 @@ Flow report for GR8RAM -Sun Oct 13 20:54:40 2019 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Fri Oct 18 15:02:10 2019 +Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -40,8 +40,8 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Sun Oct 13 20:54:38 2019 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Flow Status ; Successful - Fri Oct 18 15:02:04 2019 ; +; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; @@ -57,40 +57,40 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 10/13/2019 20:54:34 ; +; Start date & time ; 10/18/2019 15:01:50 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ -+-------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+--------------------------------------------+---------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+--------------------------------------------+---------------------------------+---------------+-------------+------------+ -; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; -; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ; -; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ; -; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 207120313862967.157101447412556 ; -- ; -- ; -- ; -; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ; -; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ; -; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ; -; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ; -; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; -; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ; -; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; -; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ; -; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ; -; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ; -; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ; -; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; -+--------------------------------------------+---------------------------------+---------------+-------------+------------+ ++---------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------------+-----------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------------+-----------------------------+---------------+-------------+------------+ +; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; +; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ; +; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ; +; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 52238299365.157142531003212 ; -- ; -- ; -- ; +; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ; +; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ; +; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ; +; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ; +; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; +; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ; +; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; +; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ; +; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ; +; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ; +; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ; +; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ++--------------------------------------------+-----------------------------+---------------+-------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------+ @@ -98,24 +98,24 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4587 MB ; 00:00:01 ; -; Fitter ; 00:00:01 ; 1.0 ; 4708 MB ; 00:00:01 ; -; Assembler ; 00:00:00 ; 1.0 ; 4522 MB ; 00:00:00 ; -; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4530 MB ; 00:00:00 ; -; Total ; 00:00:04 ; -- ; -- ; 00:00:02 ; +; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 308 MB ; 00:00:08 ; +; Fitter ; 00:00:05 ; 1.0 ; 287 MB ; 00:00:04 ; +; Assembler ; 00:00:03 ; 1.0 ; 275 MB ; 00:00:03 ; +; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 259 MB ; 00:00:05 ; +; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -+----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; -; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; -; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; -; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; -+---------------------------+------------------+-----------+------------+----------------+ ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ; +; Fitter ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ; +; Assembler ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ; +; TimeQuest Timing Analyzer ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ; ++---------------------------+------------------+------------+------------+----------------+ ------------ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 58a3c3a..fde5e98 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 7dd90f8..201c803 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,6 +1,6 @@ Analysis & Synthesis report for GR8RAM -Sun Oct 13 20:54:35 2019 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Fri Oct 18 15:01:54 2019 +Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -9,17 +9,16 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings - 4. Parallel Compilation - 5. Analysis & Synthesis Source Files Read - 6. Analysis & Synthesis Resource Usage Summary - 7. Analysis & Synthesis Resource Utilization by Entity - 8. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 - 9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 - 10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4 - 11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 - 12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5 - 13. Analysis & Synthesis Messages - 14. Analysis & Synthesis Suppressed Messages + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 + 8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 + 9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4 + 10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 + 11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5 + 12. Analysis & Synthesis Messages + 13. Analysis & Synthesis Suppressed Messages @@ -45,8 +44,8 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Oct 13 20:54:35 2019 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Analysis & Synthesis Status ; Successful - Fri Oct 18 15:01:54 2019 ; +; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; @@ -119,23 +118,12 @@ applicable agreement for further details. +----------------------------------------------------------------------------+-----------------+---------------+ -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 8 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ -; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ; +; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ; ; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ; ; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ; ; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; @@ -168,11 +156,11 @@ Parallel compilation was disabled, but you have multiple processors available. E ; Logic cells ; 105 ; ; Total registers ; 54 ; ; I/O pins ; 61 ; -; Shareable expanders ; 2 ; -; Maximum fan-out node ; S[2] ; +; Shareable expanders ; 1 ; +; Maximum fan-out node ; C7M ; ; Maximum fan-out ; 54 ; -; Total fan-out ; 862 ; -; Average fan-out ; 5.13 ; +; Total fan-out ; 866 ; +; Average fan-out ; 5.19 ; +----------------------+----------------------+ @@ -329,20 +317,20 @@ Note: In order to hide this table in the UI and the text report file, please set ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* -Info: Running Quartus II 64-Bit Analysis & Synthesis +Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Oct 13 20:54:33 2019 + Info: Processing started: Fri Oct 18 15:01:46 2019 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12023): Found entity 1: GR8RAM Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(127): truncated value with size 32 to match size of target (3) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (4) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(175): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(123): truncated value with size 32 to match size of target (3) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(165): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(171): truncated value with size 32 to match size of target (8) Info (19000): Inferred 1 megafunctions from design logic Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0" Info (278001): Inferred 4 megafunctions from design logic @@ -372,7 +360,8 @@ Info (13014): Ignored 32 buffer(s) Info (280013): Promoted pin-driven signal(s) to global signal Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal -Warning (21074): Design contains 8 input pin(s) that do not drive logic +Warning (21074): Design contains 9 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "C7M_2" Warning (15610): No output dependent on input pin "Q3" Warning (15610): No output dependent on input pin "PHI0in" Warning (15610): No output dependent on input pin "nMode" @@ -381,23 +370,23 @@ Warning (21074): Design contains 8 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "A[13]" Warning (15610): No output dependent on input pin "A[14]" Warning (15610): No output dependent on input pin "A[15]" -Info (21057): Implemented 168 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 167 device resources after synthesis - the final resource count might be different Info (21058): Implemented 27 input pins Info (21059): Implemented 18 output pins Info (21060): Implemented 16 bidirectional pins Info (21063): Implemented 105 macrocells - Info (21073): Implemented 2 shareable expanders -Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings - Info: Peak virtual memory: 4587 megabytes - Info: Processing ended: Sun Oct 13 20:54:35 2019 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 + Info (21073): Implemented 1 shareable expanders +Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 17 warnings + Info: Peak virtual memory: 308 megabytes + Info: Processing ended: Fri Oct 18 15:01:54 2019 + Info: Elapsed time: 00:00:08 + Info: Total CPU time (on all processors): 00:00:08 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg. +The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg. diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index ec1071c..665ef80 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,3 +1,3 @@ Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z" Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z" -Warning (10268): Verilog HDL information at GR8RAM.v(195): always construct contains both blocking and non-blocking assignments +Warning (10268): Verilog HDL information at GR8RAM.v(191): always construct contains both blocking and non-blocking assignments diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index d04376e..d9592ce 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,5 +1,5 @@ -Analysis & Synthesis Status : Successful - Sun Oct 13 20:54:35 2019 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Analysis & Synthesis Status : Successful - Fri Oct 18 15:01:54 2019 +Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX7000S diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin index 5e6034e..1c847c1 100755 --- a/cpld/output_files/GR8RAM.pin +++ b/cpld/output_files/GR8RAM.pin @@ -56,7 +56,7 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 3784295..d736123 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index ca44841..dcb81ec 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,6 +1,6 @@ TimeQuest Timing Analyzer report for GR8RAM -Sun Oct 13 20:54:40 2019 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Fri Oct 18 15:02:11 2019 +Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -8,36 +8,32 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary - 3. Parallel Compilation - 4. Clocks - 5. Fmax Summary - 6. Setup Summary - 7. Hold Summary - 8. Recovery Summary - 9. Removal Summary - 10. Minimum Pulse Width Summary - 11. Setup: 'C7M' - 12. Setup: 'C7M_2' - 13. Hold: 'C7M_2' - 14. Hold: 'C7M' - 15. Minimum Pulse Width: 'C7M_2' - 16. Minimum Pulse Width: 'C7M' - 17. Setup Times - 18. Hold Times - 19. Clock to Output Times - 20. Minimum Clock to Output Times - 21. Propagation Delay - 22. Minimum Propagation Delay - 23. Output Enable Times - 24. Minimum Output Enable Times - 25. Output Disable Times - 26. Minimum Output Disable Times - 27. Setup Transfers - 28. Hold Transfers - 29. Report TCCS - 30. Report RSKM - 31. Unconstrained Paths - 32. TimeQuest Timing Analyzer Messages + 3. Clocks + 4. Fmax Summary + 5. Setup Summary + 6. Hold Summary + 7. Recovery Summary + 8. Removal Summary + 9. Minimum Pulse Width Summary + 10. Setup: 'C7M' + 11. Hold: 'C7M' + 12. Minimum Pulse Width: 'C7M' + 13. Setup Times + 14. Hold Times + 15. Clock to Output Times + 16. Minimum Clock to Output Times + 17. Propagation Delay + 18. Minimum Propagation Delay + 19. Output Enable Times + 20. Minimum Output Enable Times + 21. Output Disable Times + 22. Minimum Output Disable Times + 23. Setup Transfers + 24. Hold Transfers + 25. Report TCCS + 26. Report RSKM + 27. Unconstrained Paths + 28. TimeQuest Timing Analyzer Messages @@ -73,25 +69,13 @@ applicable agreement for further details. +--------------------+-------------------------------------------------------------------+ -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 8 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; C7M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C7M } ; -; C7M_2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C7M_2 } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; C7M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C7M } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +-------------------------------------------------+ @@ -109,19 +93,17 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ -; C7M ; -47.500 ; -2074.000 ; -; C7M_2 ; -27.500 ; -33.000 ; +; C7M ; -47.500 ; -2169.500 ; +-------+---------+---------------+ -+--------------------------------+ -; Hold Summary ; -+-------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+---------------+ -; C7M_2 ; -1.500 ; -3.000 ; -; C7M ; 5.000 ; 0.000 ; -+-------+--------+---------------+ ++-------------------------------+ +; Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; C7M ; 5.000 ; 0.000 ; ++-------+-------+---------------+ -------------------- @@ -141,8 +123,7 @@ No paths to report. +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C7M_2 ; -5.500 ; -22.000 ; -; C7M ; -4.500 ; -468.000 ; +; C7M ; -4.500 ; -486.000 ; +-------+--------+---------------+ @@ -178,125 +159,92 @@ No paths to report. ; -47.500 ; REGEN ; Addr[23] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; RASf ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Bank[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Bank[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Bank[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Bank[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Bank[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Bank[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; CAS1f ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; CAS0f ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Bank[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.500 ; REGEN ; Bank[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; CASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; CAS0r ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; CAS1r ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -46.500 ; S[2] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; ; -46.500 ; S[2] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; -; -46.500 ; S[1] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; -; -46.500 ; S[1] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; -; -46.000 ; IncAddrM ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ; -; -25.500 ; Addr[22] ; CAS0r ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; Addr[22] ; CAS1r ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -46.500 ; S[0] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; +; -46.000 ; IncAddrL ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ; ; -25.500 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[1] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[1] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[1] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[0] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[1] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[1] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; ; -25.500 ; S[2] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +---------+-----------+----------+--------------+-------------+--------------+------------+------------+ -+-------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'C7M_2' ; -+---------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ -; -27.500 ; REGEN ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 44.000 ; -; -5.500 ; S[2] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; S[1] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; S[0] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; S[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; S[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -; -5.500 ; S[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; -+---------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'C7M_2' ; -+--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ -; -1.500 ; S[2] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; S[1] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; S[0] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; S[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; S[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; -1.500 ; S[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; -; 20.500 ; REGEN ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 44.000 ; -+--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ - - +----------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold: 'C7M' ; +--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ +; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; @@ -307,18 +255,14 @@ No paths to report. ; 5.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; @@ -343,9 +287,9 @@ No paths to report. ; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[23] ; Addr[23] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; @@ -371,159 +315,140 @@ No paths to report. ; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; IncAddrM ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ -+------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'C7M_2' ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ -; -5.500 ; 0.500 ; 6.000 ; High Pulse Width ; C7M_2 ; Fall ; CASf ; -; -5.500 ; 0.500 ; 6.000 ; Low Pulse Width ; C7M_2 ; Fall ; CASf ; -; -5.500 ; 0.500 ; 6.000 ; High Pulse Width ; C7M_2 ; Fall ; RASf ; -; -5.500 ; 0.500 ; 6.000 ; Low Pulse Width ; C7M_2 ; Fall ; RASf ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; C7M_2|dataout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; C7M_2|dataout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; CASf|[4] ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; CASf|[4] ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; RASf|[8] ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; RASf|[8] ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ - - -+----------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'C7M' ; -+--------+--------------+----------------+------------------+-------+------------+-------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-------------------------------+ -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; ASel ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; ASel ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[10] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[10] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[11] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[11] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[12] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[12] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[13] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[13] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[14] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[14] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[15] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[15] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[16] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[16] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[17] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[17] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[18] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[18] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[19] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[19] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[1] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[20] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[20] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[21] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[21] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[22] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[22] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[23] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[23] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[2] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[2] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[3] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[3] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[4] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[4] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[5] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[5] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[6] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[6] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[7] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[7] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[8] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[8] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[9] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[9] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[1] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[2] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[2] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[3] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[3] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[4] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[4] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[5] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[5] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[6] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[6] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[7] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[7] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CAS0r ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CAS0r ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CAS1r ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CAS1r ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSDBEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSDBEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; FullIOEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; FullIOEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOROMEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrH ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrH ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrL ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrL ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrM ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrM ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI0seen ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI0seen ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI1reg ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI1reg ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; RASr ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; RASr ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; REGEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; REGEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[1] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[2] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[2] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[1] ; -+--------+--------------+----------------+------------------+-------+------------+-------------------------------+ ++-------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'C7M' ; ++--------+--------------+----------------+------------------+-------+------------+----------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+----------+ +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; ASel ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; ASel ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[0] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[0] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[10] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[10] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[11] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[11] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[12] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[12] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[13] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[13] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[14] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[14] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[15] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[15] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[16] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[16] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[17] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[17] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[18] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[18] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[19] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[19] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[1] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[1] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[20] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[20] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[21] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[21] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[22] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[22] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[23] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[23] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[2] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[2] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[3] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[3] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[4] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[4] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[5] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[5] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[6] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[6] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[7] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[7] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[8] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[8] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[9] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[9] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[0] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[0] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[1] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[1] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[2] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[2] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[3] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[3] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[4] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[4] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[5] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[5] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[6] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[6] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[7] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[7] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; CAS0f ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; CAS0f ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; CAS1f ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; CAS1f ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CASr ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CASr ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSDBEN ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSDBEN ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; FullIOEN ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; FullIOEN ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOROMEN ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrH ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrH ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrL ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrL ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrM ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrM ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI0seen ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI0seen ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI1reg ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI1reg ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; RASf ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; RASf ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; RASr ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; RASr ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; REGEN ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; REGEN ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[0] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[0] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[1] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[1] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[2] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[2] ; ++--------+--------------+----------------+------------------+-------+------------+----------+ +---------------------------------------------------------------------------+ @@ -547,6 +472,7 @@ No paths to report. ; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; ; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; nIOSTRB ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; +; nWE ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; A[*] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; ; A[0] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; ; A[1] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; @@ -563,13 +489,6 @@ No paths to report. ; D[7] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; ; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; ; nWE ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; -; A[*] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; -; A[0] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; -; A[1] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; -; A[2] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; -; A[3] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; -; nDEVSEL ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; -; nWE ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; +-----------+------------+---------+---------+------------+-----------------+ @@ -594,6 +513,7 @@ No paths to report. ; nDEVSEL ; C7M ; -38.000 ; -38.000 ; Rise ; C7M ; ; nIOSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; ; nIOSTRB ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; +; nWE ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; ; A[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; ; A[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; ; A[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; @@ -610,13 +530,6 @@ No paths to report. ; D[7] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; ; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; ; nWE ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; A[*] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; -; A[0] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; -; A[1] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; -; A[2] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; -; A[3] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; -; nDEVSEL ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; -; nWE ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; +-----------+------------+---------+---------+------------+-----------------+ @@ -664,9 +577,7 @@ No paths to report. ; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; ; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; ; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; -; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; -; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; +; nRAS ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -714,9 +625,7 @@ No paths to report. ; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; ; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; ; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; -; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; -; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; +; nRAS ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -1087,8 +996,7 @@ No paths to report. +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C7M ; C7M ; 98 ; 2 ; 334 ; 210 ; -; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ; +; C7M ; C7M ; 95 ; 0 ; 362 ; 213 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1098,8 +1006,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C7M ; C7M ; 98 ; 2 ; 334 ; 210 ; -; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ; +; C7M ; C7M ; 95 ; 0 ; 362 ; 213 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1124,7 +1031,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 33 ; 33 ; -; Unconstrained Input Port Paths ; 477 ; 477 ; +; Unconstrained Input Port Paths ; 487 ; 487 ; ; Unconstrained Output Ports ; 33 ; 33 ; ; Unconstrained Output Port Paths ; 266 ; 266 ; +---------------------------------+-------+------+ @@ -1134,9 +1041,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* -Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer +Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Oct 13 20:54:39 2019 + Info: Processing started: Fri Oct 18 15:02:06 2019 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -1147,33 +1054,29 @@ Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8 Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name C7M C7M - Info (332105): create_clock -period 1.000 -name C7M_2 C7M_2 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -47.500 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -47.500 -2074.000 C7M - Info (332119): -27.500 -33.000 C7M_2 -Info (332146): Worst-case hold slack is -1.500 + Info (332119): -47.500 -2169.500 C7M +Info (332146): Worst-case hold slack is 5.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -1.500 -3.000 C7M_2 Info (332119): 5.000 0.000 C7M Info (332140): No Recovery paths to report Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -5.500 +Info (332146): Worst-case minimum pulse width slack is -4.500 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -5.500 -22.000 C7M_2 - Info (332119): -4.500 -468.000 C7M + Info (332119): -4.500 -486.000 C7M Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 4530 megabytes - Info: Processing ended: Sun Oct 13 20:54:40 2019 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:00 +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 259 megabytes + Info: Processing ended: Fri Oct 18 15:02:11 2019 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 0c647be..1538917 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -4,26 +4,14 @@ TimeQuest Timing Analyzer Summary Type : Setup 'C7M' Slack : -47.500 -TNS : -2074.000 - -Type : Setup 'C7M_2' -Slack : -27.500 -TNS : -33.000 - -Type : Hold 'C7M_2' -Slack : -1.500 -TNS : -3.000 +TNS : -2169.500 Type : Hold 'C7M' Slack : 5.000 TNS : 0.000 -Type : Minimum Pulse Width 'C7M_2' -Slack : -5.500 -TNS : -22.000 - Type : Minimum Pulse Width 'C7M' Slack : -4.500 -TNS : -468.000 +TNS : -486.000 ------------------------------------------------------------