forked from Apple-2-HW/GR8RAM
297 lines
24 KiB
Plaintext
Executable File
297 lines
24 KiB
Plaintext
Executable File
Analysis & Synthesis report for GR8RAM
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Sat Aug 31 22:53:29 2019
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Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Analysis & Synthesis Source Files Read
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5. Analysis & Synthesis Resource Usage Summary
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6. Analysis & Synthesis Resource Utilization by Entity
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7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
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8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add2
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9. Analysis & Synthesis Messages
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10. Analysis & Synthesis Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+-------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+-----------------------------+-------------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Sat Aug 31 22:53:29 2019 ;
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; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
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; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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; Family ; MAX7000S ;
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; Total macrocells ; 96 ;
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; Total pins ; 63 ;
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+-----------------------------+-------------------------------------------------+
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+--------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+----------------------------------------------------------------------------+-----------------+---------------+
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; Option ; Setting ; Default Value ;
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+----------------------------------------------------------------------------+-----------------+---------------+
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; Device ; EPM7128SLC84-15 ; ;
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; Top-level entity name ; GR8RAM ; GR8RAM ;
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; Family name ; MAX7000S ; Cyclone IV GX ;
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; State Machine Processing ; User-Encoded ; Auto ;
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; Parallel Synthesis ; Off ; On ;
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; Ignore LCELL Buffers ; Off ; Auto ;
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; Auto Resource Sharing ; On ; Off ;
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; Analysis & Synthesis Message Level ; High ; Medium ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; Off ; Off ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Speed ; Speed ;
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; Allow XOR Gate Usage ; On ; On ;
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; Auto Logic Cell Insertion ; On ; On ;
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; Parallel Expander Chain Length ; 4 ; 4 ;
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; Auto Parallel Expanders ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Maximum Fan-in Per Macrocell ; 100 ; 100 ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Block Design Naming ; Auto ; Auto ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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; Synthesis Seed ; 1 ; 1 ;
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+----------------------------------------------------------------------------+-----------------+---------------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
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; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
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+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
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; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
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; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
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; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
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; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
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; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
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; cmpconst.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cmpconst.inc ; ;
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; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc ; ;
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; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc ; ;
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; dffeea.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffeea.inc ; ;
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; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ;
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; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ;
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; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ;
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; addcore.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.inc ; ;
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; look_add.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/look_add.inc ; ;
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; bypassff.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc ; ;
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; altshift.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc ; ;
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; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ;
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; addcore.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf ; ;
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; a_csnbuffer.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_csnbuffer.inc ; ;
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; a_csnbuffer.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_csnbuffer.tdf ; ;
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; look_add.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/look_add.tdf ; ;
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; altshift.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.tdf ; ;
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+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
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+---------------------------------------------+
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; Analysis & Synthesis Resource Usage Summary ;
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+----------------------+----------------------+
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; Resource ; Usage ;
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+----------------------+----------------------+
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; Logic cells ; 96 ;
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; Total registers ; 48 ;
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; I/O pins ; 63 ;
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; Shareable expanders ; 10 ;
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; Maximum fan-out node ; nRES ;
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; Maximum fan-out ; 50 ;
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; Total fan-out ; 1124 ;
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; Average fan-out ; 6.65 ;
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+----------------------+----------------------+
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+-----------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+----------------------------+------------+------+-------------------------------+--------------+
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; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
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+----------------------------+------------+------+-------------------------------+--------------+
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; |GR8RAM ; 96 ; 63 ; |GR8RAM ; work ;
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; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
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+----------------------------+------------+------+-------------------------------+--------------+
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+------------------------------------------------------------------------+
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; Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 ;
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+------------------------+-------------------+---------------------------+
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; Parameter Name ; Value ; Type ;
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+------------------------+-------------------+---------------------------+
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; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
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; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
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; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
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; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
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; LPM_WIDTH ; 4 ; Untyped ;
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; LPM_DIRECTION ; UP ; Untyped ;
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; LPM_MODULUS ; 0 ; Untyped ;
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; LPM_AVALUE ; UNUSED ; Untyped ;
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; LPM_SVALUE ; UNUSED ; Untyped ;
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; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
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; DEVICE_FAMILY ; MAX7000S ; Untyped ;
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; CARRY_CHAIN ; MANUAL ; Untyped ;
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; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
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; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
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; CARRY_CNT_EN ; SMART ; Untyped ;
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; LABWIDE_SCLR ; ON ; Untyped ;
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; USE_NEW_VERSION ; TRUE ; Untyped ;
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; CBXI_PARAMETER ; NOTHING ; Untyped ;
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+------------------------+-------------------+---------------------------+
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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
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+-------------------------------------------------------------------+
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; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add2 ;
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+------------------------+-------------+----------------------------+
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; Parameter Name ; Value ; Type ;
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+------------------------+-------------+----------------------------+
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; LPM_WIDTH ; 23 ; Untyped ;
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; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
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; LPM_DIRECTION ; ADD ; Untyped ;
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; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
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; LPM_PIPELINE ; 0 ; Untyped ;
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; MAXIMIZE_SPEED ; 5 ; Untyped ;
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; REGISTERED_AT_END ; 0 ; Untyped ;
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; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
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; USE_CS_BUFFERS ; 1 ; Untyped ;
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; CARRY_CHAIN ; MANUAL ; Untyped ;
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; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
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; DEVICE_FAMILY ; MAX7000S ; Untyped ;
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; USE_WYS ; OFF ; Untyped ;
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; STYLE ; FAST ; Untyped ;
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; CBXI_PARAMETER ; add_sub_8ph ; Untyped ;
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; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
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; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
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; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
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; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
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+------------------------+-------------+----------------------------+
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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
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+-------------------------------+
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; Analysis & Synthesis Messages ;
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+-------------------------------+
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Info: *******************************************************************
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Info: Running Quartus II 32-bit Analysis & Synthesis
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Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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Info: Processing started: Sat Aug 31 22:53:19 2019
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
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Warning (20028): Parallel compilation is not licensed and has been disabled
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Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
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Info (12023): Found entity 1: GR8RAM
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Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
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Warning (10230): Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (3)
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Warning (10230): Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (4)
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Warning (10230): Verilog HDL assignment warning at GR8RAM.v(153): truncated value with size 32 to match size of target (23)
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Info (19000): Inferred 1 megafunctions from design logic
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Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
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Info (278001): Inferred 1 megafunctions from design logic
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Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add2"
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Info (12130): Elaborated megafunction instantiation "lpm_counter:Ref_rtl_0"
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Info (12133): Instantiated megafunction "lpm_counter:Ref_rtl_0" with the following parameter:
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Info (12134): Parameter "LPM_WIDTH" = "4"
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Info (12134): Parameter "LPM_DIRECTION" = "UP"
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Info (12134): Parameter "LPM_TYPE" = "LPM_COUNTER"
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Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add2"
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Info (12133): Instantiated megafunction "lpm_add_sub:Add2" with the following parameter:
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Info (12134): Parameter "LPM_WIDTH" = "23"
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Info (12134): Parameter "LPM_DIRECTION" = "ADD"
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Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
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Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
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Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder[2]", which is child of megafunction instantiation "lpm_add_sub:Add2"
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Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder[2]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add2"
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Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder[2]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add2"
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Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder[1]", which is child of megafunction instantiation "lpm_add_sub:Add2"
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Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add2"
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Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add2"
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Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add2"
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Info (13014): Ignored 23 buffer(s)
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Info (13019): Ignored 23 SOFT buffer(s)
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Info (280013): Promoted pin-driven signal(s) to global signal
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Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal
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Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal
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Info (280013): Promoted pin-driven signal(s) to global signal
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Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal
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Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal
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Warning (21074): Design contains 2 input pin(s) that do not drive logic
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Warning (15610): No output dependent on input pin "Q3"
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Warning (15610): No output dependent on input pin "PHI0in"
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Info (21057): Implemented 169 device resources after synthesis - the final resource count might be different
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Info (21058): Implemented 27 input pins
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Info (21059): Implemented 20 output pins
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Info (21060): Implemented 16 bidirectional pins
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Info (21063): Implemented 96 macrocells
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Info (21073): Implemented 10 shareable expanders
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Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
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Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 7 warnings
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Info: Peak virtual memory: 308 megabytes
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Info: Processing ended: Sat Aug 31 22:53:29 2019
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Info: Elapsed time: 00:00:10
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Info: Total CPU time (on all processors): 00:00:10
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+------------------------------------------+
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; Analysis & Synthesis Suppressed Messages ;
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+------------------------------------------+
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The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
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