Zane Kaminski 66fc09b402 Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

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GR8RAM.asm.rpt

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.cdf

1MB CPLD design seems to work, fails Apple BIST

2019-09-01 21:18:44 -04:00

GR8RAM.done

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.fit.rpt

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.fit.summary

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.flow.rpt

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.jdi

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.map.rpt

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.map.smsg

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.map.summary

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.pin

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.pof

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.sta.rpt

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00

GR8RAM.sta.summary

Made AddrH high bit variable with mode input

2019-09-07 21:16:23 -04:00