/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */
/* Module Version: 1.2 */
/* Thu Jul 27 11:56:36 2017 */

/* parameterized module instance */
spiFlash __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), 
    .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), 
    .spi_clk( ), .spi_miso( ), .spi_mosi( ), .spi_scsn( ), .spi_csn( ));