forked from Apple-2-HW/fpga-disk-controller
296 lines
12 KiB
Verilog
296 lines
12 KiB
Verilog
`timescale 1 ns / 1 ps
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module iwm(
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// bus interface
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input [3:0] addr, // A3-A1 selects one of 8 bits in the state register to be updated. A0 is the new state value.
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// A0 is also the /READ input, enables IWM to send the register selected by the state onto the data bus
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input _devsel, // Device enable: falling edge latches A3-A0. Rising edge of (Q3 or _devsel) qualifies write register data
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input fclk, // Clock for serial communication, either 7 or 8 MHz (7 MHz on Apple II)
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input q3, // 2 MHz non-symmetrical clock, used to qualify the timing of the serial data being written out for synchronous mode
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input _reset, // system reset
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input [7:0] dataIn, // Bidirectional data bus on a real IWM. Verilog model has separate input and output data ports.
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output reg [7:0] dataOut,
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// disk interface
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output reg wrdata, // serial data output - a transition occurs for each 1 bit
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output reg [3:0] phase, // programmable output, used in different ways depending on type of disk
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output _wrreq, // write request
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output _enbl1, // disk 1 enable
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output _enbl2, // disk 2 enable
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input sense, // input from disk, used for write protect or handshake, can be polled via status register
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input rddata // serial data input - falling transition of each pulse is synchronized by IWM
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);
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// internal private state
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//reg [4:0] mode; // we're ignoring all these
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reg [7:0] shifter;
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reg [7:0] buffer; // when Q6Q7 is 00, functions as read register. When Q7 is 1, write register.
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reg motorOn;
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reg driveSelect;
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reg q6, q7;
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reg _underrun;
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reg writeBufferEmpty;
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// state pseudo-register
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// the bits in this register are individually addressed by A3-A1
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// The data on A0 is latched into the addressed state bit by /DEV low [the falling edge of /DEV latches information on A0-A3]
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// All bits are reset to 0 by _reset low
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always @(negedge _devsel or negedge _reset) begin
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if (_reset == 0) begin
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phase <= 4'b0000;
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motorOn <= 0;
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driveSelect <= 0;
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q6 <= 0;
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q7 <= 0;
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end
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else begin
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case (addr[3:1])
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3'h0: // ph0
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phase[0] <= addr[0];
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3'h1: // ph1
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phase[1] <= addr[0];
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3'h2: // ph2
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phase[2] <= addr[0];
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3'h3: // ph3
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phase[3] <= addr[0];
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3'h4: // motor on
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motorOn <= addr[0];
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3'h5: // drive select
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driveSelect <= addr[0];
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3'h6: // Q6
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q6 <= addr[0];
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3'h7: // Q7
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q7 <= addr[0];
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endcase
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end
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end
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// drive enable outputs are determined from motorOn and driveSelect
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// no more than one enable may be low at a time
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assign _enbl1 = ~(motorOn & ~driveSelect);
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assign _enbl2 = ~(motorOn & driveSelect);
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// The combination of Q7 and Motor-On and /undderrun enable /wrreq low
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assign _wrreq = ~(q7 & _underrun & (_enbl1 == 0 | _enbl2 == 0));
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/* IWM mode register: S C M H L
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(could save some macrocells here by assuming all the Apple II values)
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(all mode bits are reset to 0 by _reset low)
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S Clock speed:
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0 = 7 MHz (Apple II)
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1 = 8 MHz (Macintosh)
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C Bit cell time:
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0 = 4 usec/bit (for 5.25 drives and Smartport) (Apple II)
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1 = 2 usec/bit (for 3.5 drives) (Macintosh mode)
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M Motor-off timer:
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0 = leave drive on for 1 sec after program turns it off (Apple II)
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1 = no delay (Macintosh mode)
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H Handshake protocol:
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0 = synchronous (software must supply proper timing for writing data) (Apple II)
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1 = asynchronous (IWM supplies timing) (Macintosh Mode)
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*In synchronous mode, the time of the Q7Q6 01 to 11 transition and every 8 Q3 periods (4 us)
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thereafter, until Q7 is cleared, marks the beginning of a write window. The duration of the
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write window is 4 periods of the Q3 input (2 us). The data written at the last write access
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occurring within this write window will load the shift register with the data to be shifted
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out. If the next write access has not occurred 32 us (64 Q3 period) after a load, the write
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will be extended in multiples of 4 us (8 Q3 periods) until another write access, and zeroes
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will be shifted out. In synchronous mode, Q3 clock input is used internally to generate the
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32 and 40 us timings, which would then be 64 and 80 Q3 clock periods in duration, respectively,
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and the bit cell timings, 8 Q3 periods per bit cell time in slow mode.
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*In asynchronous mode, the write shift register is buffered and, when the buffer is empty, the
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iwm sets the MSB of the write-handhake register to a one to indicate that the next data nibble
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can be written to the buffer. The buffer register may be written at any time during the write
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state. Only the data last written into the buffer register, before the contents of the buffer
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register is transferred to the write shift register, is used. In asynchronous mode CLK is used
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to generate the bit cell timings. In fast mode CLK is equivalent to the clock input on FCLK. In
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slow mode CLK is equivalent to the clock input on FCLK
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divided by two. Therefore, in 7M and slow mode the bit cell time will be 28 FCLK periods, in 8M
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and slow mode the cell time will be 32 periods, and in 8M and
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fast mode the cell time will be 16 periods. In asynchronous mode the write shift register is loaded
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every 8 bit cell times starting seven clock periods after the write state begins.
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*Normally data written to the IWM is sampled by the zero to one transition of the logial OR of
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Q3 and /DEV. In asynchronous mode the Q3 input may be tied low.
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*An underrun occurs when data has not been written to the buffer register between the time the
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write-handshake bit indicates and empty buffer and the time the buffer is transferred to the
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write shift register. If an underrun occurs in asynchronous mode /WRREQ will be disabled and
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the underrun flag will be set to 0. This occurrance can be detected by reading the write-
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handshake register before clearing the state bit Q7. Clearing the state bit Q7 will reset the
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underrun flag.
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L Latch mode (should be set in asynchronous mode):
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0 = read-data stays valid for about 2 usec (Apple II)
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1 = read-data stays valid for full byte time (Macintosh mode)
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In latch mode, the MSB of the read data is latched internally during /DEV low. This internally
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latched MSB is then used for the determination of a valid data read.
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*/
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/* When reading serial data, a falling transition within a bit cell window is considered to be
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a 1, and no falling transition within a window is a 0. The receive data input on RDDATA is
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synchronized internally with the CLK clock. The synchronized falling transition is then discriminated
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to the nearest bit cell window using the 7/8 MHz FCLK signal in fast mode and the FCLK signal
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divided by two in slow mode.
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In read state, data is shifted into the LSB of the shift register, and it shifts from LSB to
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MSB. A full data nibble is considered to be shifted in when a 1 is shifted into the MSB. When
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a full nibble is shifted in, the data will be latched by the read data register and the shift
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register will be cleared to all zeroes.
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In synchronous mode, the shift register is readable in any intermediate state with this
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exception: when a 1 is shifted into the MSB, the shift register will appear, to the data bus,
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to be stalled for a period of two bit times plus four CLK periods. This is to allow the host
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processor time to poll the MSB to determine when data is valid. In asynchronous mode the data
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register will latch the shift register when a one is shifted into the MSB and will be cleared
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14 FCLK periods (about 2 us) after a valid data read takes place (a valid data read being
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defined as both /DEV being low and D7 (the MSB) outputting a 1 from the data register for at
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least one FCLK period.
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*/
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// read registers
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// Q7 Q6 Moton-On Operation
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// 0 0 0 read all 1's
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// 0 0 1 read data register Read
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// 0 1 x read status register Write-protect sense
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// 1 0 x read write-handshake reg Write
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always @(*) begin
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case ({q7,q6})
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2'b00: // data-in register (from disk drive) - MSB is 1 when data is valid. Reads all 1's if motor is off.
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dataOut <= buffer;
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2'b01: // IWM status register
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dataOut <= { sense, 1'b0, motorOn, 5'b00111 /*mode*/ };
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default: // 2'b10 handshake register
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dataOut <= { writeBufferEmpty, _underrun, 6'b000000 };
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endcase
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end
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// Mode and data register writes, disk serial I/O
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// this assumes the mode register SCMHL is 00111
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reg [1:0] rddataSync;
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always @(posedge fclk) begin
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rddataSync <= { rddataSync[0], rddata };
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end
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wire q3orDev = q3 | _devsel;
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reg [5:0] bitTimer; // max value 42
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reg [2:0] bitCounter; // max value 7
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reg [3:0] clearBufferTimer; // max value 14
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always @(posedge fclk or negedge _reset) begin
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if (_reset == 0) begin
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_underrun <= 1'b1;
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writeBufferEmpty <= 1'b1;
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bitCounter <= 0;
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buffer <= 0;
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clearBufferTimer <= 0;
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wrdata <= 0;
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//mode <= 5'b00000;
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end
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else begin
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// READ FROM DISK
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if (q7 == 0 && q6 == 0) begin
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if (clearBufferTimer == 0) begin
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// if the timer isn't already running and there is a valid read from the data buffer?
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if (_devsel == 0 && addr[0] == 0 && buffer[7] == 1'b1) begin
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clearBufferTimer <= 1; // start the timer
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end
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end
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else begin
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// have about 2 us elapsed since the last valid read from the buffer?
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if (clearBufferTimer == 4'hE /* 14 FCLK periods */) begin
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buffer[7] <= 0; // only the MSB really needs to be cleared. Saves some CPLD logic vs clearing the whole buffer.
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clearBufferTimer <= 0; // stop the timer
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end
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else begin
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clearBufferTimer <= clearBufferTimer + 1'b1;
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end
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end
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// was there a falling transition on rddata?
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if (rddataSync[1] & ~rddataSync[0]) begin
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// has at least half a bit cell time elpased since the last cell boundary?
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// don't shift any bits if the clock count was less than half a bit cell time
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if (bitTimer >= 14) begin
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shifter <= { shifter[6:0], 1'b1 }; // shift in a 1 bit
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end
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bitTimer <= 0;
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end
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else begin
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// have one and a half bit cell times elapsed?
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if (bitTimer >= 42) begin
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shifter <= { shifter[6:0], 1'b0 }; // shift in a 0 bit
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bitTimer <= 14; // reset to half bit cell time
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end
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else begin
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// has a complete byte been shifted in?
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if (shifter[7] == 1) begin
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buffer <= shifter; // latch the byte
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shifter <= 0; // clear the byte from the shifter
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end
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bitTimer <= bitTimer + 1'b1;
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end
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end
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end
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// WRITE TO DISK
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if (q7 == 1'b1) begin
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// is it time for a new bit?
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if (bitTimer == 28) begin
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bitTimer <= 0;
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// is the entire byte done?
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if (bitCounter == 7) begin
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bitCounter <= 0;
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// is there a new byte ready?
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if (writeBufferEmpty == 0) begin
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// move the next byte into the shifter
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shifter <= buffer;
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writeBufferEmpty <= 1'b1;
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end
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else begin
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_underrun <= 0; // error
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end
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end
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else begin
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// there are still more bits remaining, so shift the next bit
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bitCounter <= bitCounter + 1'b1;
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shifter <= { shifter[6:0], 1'b0 }; // left shift
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end
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end
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else begin
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bitTimer <= bitTimer + 1'b1;
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end
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// wrdata transition at start of a bit cell indicates a logical 1 bit
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if (bitTimer == 1 && shifter[7] == 1) begin
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wrdata <= ~wrdata;
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end
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end
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else begin
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_underrun <= 1; // clear error when Q7 is 0
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end
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// WRITE REGISTERS
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// a register is written when both Q6 and Q7 are set or are being set, and A0 is 1
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// Q7 Q6 Moton-On Operation
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// 1 1 0 write mode register Mode Set
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// 1 1 1 write data register Write Load
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// The IWM spec says register writes are qualified by the rising edge of (Q3 or _devsel),
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// but that's a problem for buffer and writeBufferEmpty, which would then need to be clocked
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// by both FCLK and (Q3 or _devsel). Instead we'll perform a register write at any FCLK
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// edge when (Q3 or _devsel) is low, treating it like a load enable. A review of timing
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// diagrams looks like this will work.
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if (q3orDev == 0 && q7 && q6 && addr[0]) begin
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if (motorOn) begin
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buffer <= dataIn; // data for disk write
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writeBufferEmpty <= 0;
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writeBufferEmpty <= 0;
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end
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else begin
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//mode <= data[4:0];
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end
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end
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end
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end
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// TODO: clear read buffer after a valid read
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// TODO: clear shifter at start of a read operation?
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// TODO: set writeBufferEmpty at start of a write?
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endmodule |